From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3C31C433E9 for ; Fri, 8 Jan 2021 14:06:40 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 90C2823A02 for ; Fri, 8 Jan 2021 14:06:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726871AbhAHOG0 (ORCPT ); Fri, 8 Jan 2021 09:06:26 -0500 Received: from m43-15.mailgun.net ([69.72.43.15]:28885 "EHLO m43-15.mailgun.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725926AbhAHOG0 (ORCPT ); Fri, 8 Jan 2021 09:06:26 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1610114766; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=NolXsxXc4LnP1hy9iZM7qEDax7wxHeKW7dI9mmmMmqw=; b=MMYicWq2rH34P5q0rcq8ez8SKY88Dcly9fZn88IrEHZfW6YQpzBJAONLWOYBpp3/RNqRsYvs NS/ekjZYaWVfpUgKV+J3E8e9dVv1bgO3IQKybQhaqVMITgBcXEfYRVauMrjcQwHD1+PhPbtF F3WImDzL4daBw0VM+eQ439d97gY= X-Mailgun-Sending-Ip: 69.72.43.15 X-Mailgun-Sid: WyI1MzIzYiIsICJsaW51eC1hcm0tbXNtQHZnZXIua2VybmVsLm9yZyIsICJiZTllNGEiXQ== Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n10.prod.us-west-2.postgun.com with SMTP id 5ff866ae4c4e6d4a2bc86c63 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 08 Jan 2021 14:05:34 GMT Sender: saiprakash.ranjan=codeaurora.org@mg.codeaurora.org Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 78D35C43465; Fri, 8 Jan 2021 14:05:34 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 726EDC433C6; Fri, 8 Jan 2021 14:05:33 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII; format=flowed Content-Transfer-Encoding: 7bit Date: Fri, 08 Jan 2021 19:35:33 +0530 From: Sai Prakash Ranjan To: Konrad Dybcio Cc: robdclark@gmail.com, airlied@linux.ie, airlied@redhat.com, akhilpo@codeaurora.org, angelogioacchino.delregno@somainline.org, bjorn.andersson@linaro.org, daniel@ffwll.ch, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, jcrouse@codeaurora.org, jonathan@marek.ca, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, marijn.suijten@somainline.org, martin.botka@somainline.org, phone-devel@vger.kernel.org, sean@poorly.run, shawn.guo@linaro.org, smasetty@codeaurora.org, ~postmarketos/upstreaming@lists.sr.ht Subject: Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx In-Reply-To: References: <20210108122601.14993-1-saiprakash.ranjan@codeaurora.org> Message-ID: <43c8779bc5f03be2e8072c6484dfcabb@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 2021-01-08 19:09, Konrad Dybcio wrote: >> Konrad, can you please test this below change without your change? > > This brings no difference, a BUG still happens. We're still calling > to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330 > into an A640.. > > Also, relying on disabling LLCC in the config is out of question as it > makes the arm32 kernel not compile with DRM/MSM and it just removes > the functionality on devices with a6xx.. (unless somebody removes the > dependency on it, which in my opinion is even worse and will cause > more problems for developers!). > Disabling LLCC is not the suggestion, I was under the impression that was the cause here for the smmu bug. Anyways, the check for llc slice in case llcc is disabled is not correct as well. I will send a patch for that as well. > The bigger question is how and why did that piece of code ever make it > to adreno_gpu.c and not a6xx_gpu.c? > My mistake, I will move it. > To solve it in a cleaner way I propose to move it to an a6xx-specific > file, or if it's going to be used with next-gen GPUs, perhaps manage > calling of this code via an adreno quirk/feature in adreno_device.c. > Now that I think about it, A5xx GPMU en/disable could probably managed > like that, instead of using tons of if-statements for each GPU model > that has it.. > > While we're at it, do ALL (and I truly do mean ALL, including the > low-end ones, this will be important later on) A6xx GPUs make use of > that feature? > I do not have a list of all A6XX GPUs with me currently, but from what I know, A618, A630, A640, A650 has the support. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02D35C433E6 for ; Sat, 9 Jan 2021 11:47:01 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BBEE123A31 for ; Sat, 9 Jan 2021 11:47:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BBEE123A31 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 53D826E93B; Sat, 9 Jan 2021 11:46:49 +0000 (UTC) Received: from so254-31.mailgun.net (so254-31.mailgun.net [198.61.254.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id DC74C6E82C for ; Fri, 8 Jan 2021 14:05:37 +0000 (UTC) DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1610114739; h=Message-ID: References: In-Reply-To: Subject: Cc: To: From: Date: Content-Transfer-Encoding: Content-Type: MIME-Version: Sender; bh=NolXsxXc4LnP1hy9iZM7qEDax7wxHeKW7dI9mmmMmqw=; b=jpxa842rf8MY3PYM1ijOIlW7Yt0EISqKf4TL6q5CtQ278rGiUuzGP/y6BG3ZBjMOT6HgHwRT Vep6bcoBo1AhCt7GMMIuUyc7/6AVxmzl5FYzsejJLeyWsaBpABmWFTIq9lssW4S5bwjXnQjw Q0RHFtFPMxIa93Kzyk/T+Zh3iuo= X-Mailgun-Sending-Ip: 198.61.254.31 X-Mailgun-Sid: WyJkOTU5ZSIsICJkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by smtp-out-n07.prod.us-east-1.postgun.com with SMTP id 5ff866af9f9cd52344f26554 (version=TLS1.2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256); Fri, 08 Jan 2021 14:05:35 GMT Received: by smtp.codeaurora.org (Postfix, from userid 1001) id 6ED23C43463; Fri, 8 Jan 2021 14:05:34 +0000 (UTC) Received: from mail.codeaurora.org (localhost.localdomain [127.0.0.1]) (using TLSv1 with cipher ECDHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) (Authenticated sender: saiprakash.ranjan) by smtp.codeaurora.org (Postfix) with ESMTPSA id 726EDC433C6; Fri, 8 Jan 2021 14:05:33 +0000 (UTC) MIME-Version: 1.0 Date: Fri, 08 Jan 2021 19:35:33 +0530 From: Sai Prakash Ranjan To: Konrad Dybcio Subject: Re: [PATCH] drm/msm: Only enable A6xx LLCC code on A6xx In-Reply-To: References: <20210108122601.14993-1-saiprakash.ranjan@codeaurora.org> Message-ID: <43c8779bc5f03be2e8072c6484dfcabb@codeaurora.org> X-Sender: saiprakash.ranjan@codeaurora.org User-Agent: Roundcube Webmail/1.3.9 X-Mailman-Approved-At: Sat, 09 Jan 2021 11:46:48 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: sean@poorly.run, jonathan@marek.ca, airlied@linux.ie, linux-arm-msm@vger.kernel.org, smasetty@codeaurora.org, martin.botka@somainline.org, akhilpo@codeaurora.org, dri-devel@lists.freedesktop.org, bjorn.andersson@linaro.org, marijn.suijten@somainline.org, ~postmarketos/upstreaming@lists.sr.ht, angelogioacchino.delregno@somainline.org, airlied@redhat.com, phone-devel@vger.kernel.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 2021-01-08 19:09, Konrad Dybcio wrote: >> Konrad, can you please test this below change without your change? > > This brings no difference, a BUG still happens. We're still calling > to_a6xx_gpu on ANY device that's probed! Too bad it won't turn my A330 > into an A640.. > > Also, relying on disabling LLCC in the config is out of question as it > makes the arm32 kernel not compile with DRM/MSM and it just removes > the functionality on devices with a6xx.. (unless somebody removes the > dependency on it, which in my opinion is even worse and will cause > more problems for developers!). > Disabling LLCC is not the suggestion, I was under the impression that was the cause here for the smmu bug. Anyways, the check for llc slice in case llcc is disabled is not correct as well. I will send a patch for that as well. > The bigger question is how and why did that piece of code ever make it > to adreno_gpu.c and not a6xx_gpu.c? > My mistake, I will move it. > To solve it in a cleaner way I propose to move it to an a6xx-specific > file, or if it's going to be used with next-gen GPUs, perhaps manage > calling of this code via an adreno quirk/feature in adreno_device.c. > Now that I think about it, A5xx GPMU en/disable could probably managed > like that, instead of using tons of if-statements for each GPU model > that has it.. > > While we're at it, do ALL (and I truly do mean ALL, including the > low-end ones, this will be important later on) A6xx GPUs make use of > that feature? > I do not have a list of all A6XX GPUs with me currently, but from what I know, A618, A630, A640, A650 has the support. Thanks, Sai -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel