From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marek Vasut Date: Sun, 30 Sep 2018 18:39:13 +0200 Subject: [U-Boot] [PATCH 3/3] ARM: imx6: DHCOM i.MX6 PDK: ddr init for 32bit bus and 4GBit chips In-Reply-To: <1530775428-19269-3-git-send-email-lzenz@dh-electronics.de> References: <1530775428-19269-1-git-send-email-lzenz@dh-electronics.de> <1530775428-19269-3-git-send-email-lzenz@dh-electronics.de> Message-ID: <440e7c41-42b1-4766-493b-cbb7517604b9@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 07/05/2018 09:23 AM, lzenz at dh-electronics.de wrote: > From: Ludwig Zenz > > Support 1GIB + 2GIB DDR3 with 64bit bus width and 512MIB + 1GIB with 32bit bus width > > Signed-off-by: Ludwig Zenz > --- > board/dhelectronics/dh_imx6/dh_imx6_spl.c | 191 +++++++++++++++++++++++++++--- > 1 file changed, 173 insertions(+), 18 deletions(-) > > diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c [...] This patch causes memory instability on 1GiB MX6Q part. Can you check that and fix it ? Thanks. -- Best regards, Marek Vasut