From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751830AbdFJEnb (ORCPT ); Sat, 10 Jun 2017 00:43:31 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:35549 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750945AbdFJEn3 (ORCPT ); Sat, 10 Jun 2017 00:43:29 -0400 Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (1.0) Subject: Re: [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup From: Hoeun Ryu X-Mailer: iPhone Mail (14F89) In-Reply-To: <1496803173-4894-1-git-send-email-hoeun.ryu@gmail.com> Date: Sat, 10 Jun 2017 13:43:24 +0900 Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Content-Transfer-Encoding: 7bit Message-Id: <448EF961-9178-4A3F-8995-F4E3466F4A92@gmail.com> References: <1496803173-4894-1-git-send-email-hoeun.ryu@gmail.com> To: Robin Murphy , Russell King Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello, Russell and Robin. Would you please review this patch ? Than you > On Jun 7, 2017, at 11:39 AM, Hoeun Ryu wrote: > > Reading TTBCR in early boot stage might return the value of the previous > kernel's configuration, especially in case of kexec. For example, if > normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <= > PAGE_OFFSET and crash kernel (second kernel) is running on a configuration > PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the > reserved area for crash kernel, reading TTBCR and using the value to OR > other bit fields might be risky because it doesn't have a reset value for > TTBCR. > > Suggested-by: Robin Murphy > Signed-off-by: Hoeun Ryu > --- > > * v1: amended based on > - "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when > PHYS_OFFSET > PAGE_OFFSET" > - https://lkml.org/lkml/2017/6/5/239 > > arch/arm/mm/proc-v7-3level.S | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S > index 5e5720e..7d16bbc 100644 > --- a/arch/arm/mm/proc-v7-3level.S > +++ b/arch/arm/mm/proc-v7-3level.S > @@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext) > .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp > ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address > cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET? > - mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister > - orr \tmp, \tmp, #TTB_EAE > + mov \tmp, #TTB_EAE @ for TTB control egister > ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP) > ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP) > ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16) > -- > 2.7.4 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: hoeun.ryu@gmail.com (Hoeun Ryu) Date: Sat, 10 Jun 2017 13:43:24 +0900 Subject: [PATCH] arm:lpae: build TTB control register value from scratch in v7_ttb_setup In-Reply-To: <1496803173-4894-1-git-send-email-hoeun.ryu@gmail.com> References: <1496803173-4894-1-git-send-email-hoeun.ryu@gmail.com> Message-ID: <448EF961-9178-4A3F-8995-F4E3466F4A92@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hello, Russell and Robin. Would you please review this patch ? Than you > On Jun 7, 2017, at 11:39 AM, Hoeun Ryu wrote: > > Reading TTBCR in early boot stage might return the value of the previous > kernel's configuration, especially in case of kexec. For example, if > normal kernel (first kernel) had run on a configuration of PHYS_OFFSET <= > PAGE_OFFSET and crash kernel (second kernel) is running on a configuration > PHYS_OFFSET > PAGE_OFFSET, which can happen because it depends on the > reserved area for crash kernel, reading TTBCR and using the value to OR > other bit fields might be risky because it doesn't have a reset value for > TTBCR. > > Suggested-by: Robin Murphy > Signed-off-by: Hoeun Ryu > --- > > * v1: amended based on > - "[PATCHv2] arm: LPAE: kexec: clear TTBCR.T1SZ explicitly when > PHYS_OFFSET > PAGE_OFFSET" > - https://lkml.org/lkml/2017/6/5/239 > > arch/arm/mm/proc-v7-3level.S | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S > index 5e5720e..7d16bbc 100644 > --- a/arch/arm/mm/proc-v7-3level.S > +++ b/arch/arm/mm/proc-v7-3level.S > @@ -129,8 +129,7 @@ ENDPROC(cpu_v7_set_pte_ext) > .macro v7_ttb_setup, zero, ttbr0l, ttbr0h, ttbr1, tmp > ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address > cmp \ttbr1, \tmp, lsr #12 @ PHYS_OFFSET > PAGE_OFFSET? > - mrc p15, 0, \tmp, c2, c0, 2 @ TTB control egister > - orr \tmp, \tmp, #TTB_EAE > + mov \tmp, #TTB_EAE @ for TTB control egister > ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP) > ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP) > ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16) > -- > 2.7.4 >