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([2602:ae:1598:4c01:35a2:c45d:7485:f488]) by smtp.gmail.com with ESMTPSA id i12-20020a170902eb4c00b0019a773419a6sm5478538pli.170.2023.05.30.10.21.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 30 May 2023 10:21:49 -0700 (PDT) Message-ID: <44d4f3e3-2c3e-f3a3-8917-72399a084356@linaro.org> Date: Tue, 30 May 2023 10:21:47 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [RFC PATCH] target/arm: use x86 intrinsics to implement AES instructions Content-Language: en-US To: Ard Biesheuvel Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Peter Maydell , =?UTF-8?Q?Alex_Benn=c3=a9e?= , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20230530135204.2903761-1-ardb@kernel.org> <666b4b6c-380e-142e-9348-823006b35312@linaro.org> From: Richard Henderson In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 5/30/23 09:58, Ard Biesheuvel wrote: > On Tue, 30 May 2023 at 18:43, Richard Henderson > wrote: >> >> On 5/30/23 06:52, Ard Biesheuvel wrote: >>> +#ifdef __x86_64__ >>> + if (have_aes()) { >>> + __m128i *d = (__m128i *)rd; >>> + >>> + *d = decrypt ? _mm_aesdeclast_si128(rk.vec ^ st.vec, (__m128i){}) >>> + : _mm_aesenclast_si128(rk.vec ^ st.vec, (__m128i){}); >> >> Do I correctly understand that the ARM xor is pre-shift >> >>> + return; >>> + } >>> +#endif >>> + >>> /* xor state vector with round key */ >>> rk.l[0] ^= st.l[0]; >>> rk.l[1] ^= st.l[1]; >> >> (like so) >> >> whereas the x86 xor is post-shift >> >>> void glue(helper_aesenclast, SUFFIX)(CPUX86State *env, Reg *d, Reg *v, Reg *s) >>> { >>> int i; >>> Reg st = *v; >>> Reg rk = *s; >>> >>> for (i = 0; i < 8 << SHIFT; i++) { >>> d->B(i) = rk.B(i) ^ (AES_sbox[st.B(AES_shifts[i & 15] + (i & ~15))]); >>> } >> >> (like so, from target/i386/ops_sse.h)? >> > > Indeed. Using the primitive operations defined in the AES paper, we > basically have the following for n rounds of AES (for n in {10, 12, > 14}) > > for (n-1 rounds) { > AddRoundKey > ShiftRows > SubBytes > MixColumns > } > AddRoundKey > ShiftRows > SubBytes > AddRoundKey > > AddRoundKey is just XOR, but it is incorporated into the instructions > that combine a couple of these steps. > > So on x86, we have > > aesenc: > ShiftRows > SubBytes > MixColumns > AddRoundKey > > aesenclast: > ShiftRows > SubBytes > AddRoundKey > > and on ARM we have > > aese: > AddRoundKey > ShiftRows > SubBytes > > aesmc: > MixColumns > > >> What might help: could we do the reverse -- emulate the x86 aesdeclast instruction with >> the aarch64 aesd instruction? >> > > Help in what sense? To emulate the x86 instructions on a ARM host? Well that too. I meant help me understand the two primitives. > But yes, aesenclast can be implement using aese in a similar way, > i.e., by passing a {0} vector as the round key into the instruction, > and performing the XOR explicitly using the real round key afterwards. Excellent, thanks. r~