From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC3C6C48BDF for ; Tue, 15 Jun 2021 14:08:33 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9AED061446 for ; Tue, 15 Jun 2021 14:08:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230305AbhFOOKh (ORCPT ); Tue, 15 Jun 2021 10:10:37 -0400 Received: from eu-smtp-delivery-151.mimecast.com ([185.58.85.151]:50504 "EHLO eu-smtp-delivery-151.mimecast.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230120AbhFOOKf (ORCPT ); Tue, 15 Jun 2021 10:10:35 -0400 Received: from AcuMS.aculab.com (156.67.243.121 [156.67.243.121]) (Using TLS) by relay.mimecast.com with ESMTP id uk-mta-10-0BSCW0PNMeiUs_3ZDkVtBw-1; Tue, 15 Jun 2021 15:08:28 +0100 X-MC-Unique: 0BSCW0PNMeiUs_3ZDkVtBw-1 Received: from AcuMS.Aculab.com (10.202.163.4) by AcuMS.aculab.com (10.202.163.4) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Tue, 15 Jun 2021 15:08:27 +0100 Received: from AcuMS.Aculab.com ([fe80::994c:f5c2:35d6:9b65]) by AcuMS.aculab.com ([fe80::994c:f5c2:35d6:9b65%12]) with mapi id 15.00.1497.018; Tue, 15 Jun 2021 15:08:27 +0100 From: David Laight To: 'Bin Meng' , Gary Guo CC: Palmer Dabbelt , Paul Walmsley , "aou@eecs.berkeley.edu" , "nickhu@andestech.com" , "nylon7@andestech.com" , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH] riscv: fix memmove and optimise memcpy when misalign Thread-Topic: [PATCH] riscv: fix memmove and optimise memcpy when misalign Thread-Index: AQHXT3WL0lTofUR6TU66MVYMSFr0J6rxS6gAgCPtaRCAAANAsA== Date: Tue, 15 Jun 2021 14:08:27 +0000 Message-ID: <44e4e70491164ef5b777d06f48b6684f@AcuMS.aculab.com> References: <20210522232256.00003f08@garyguo.net> <17637b10e71b41b89126cbb1b2fa61cf@AcuMS.aculab.com> <20210525153431.0000508d@garyguo.net> In-Reply-To: Accept-Language: en-GB, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.202.205.107] MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=C51A453 smtp.mailfrom=david.laight@aculab.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: aculab.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: base64 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org RnJvbTogQmluIE1lbmcNCj4gU2VudDogMTUgSnVuZSAyMDIxIDE0OjQwDQouLi4NCj4gPiBJIHBy ZWZlciBDIHZlcnNpb25zIGFzIHdlbGwsIGFuZCBhY3R1YWxseSBiZWZvcmUgY29tbWl0IDA0MDkx ZDYgd2UgYXJlDQo+ID4gaW5kZWVkIHVzaW5nIHRoZSBnZW5lcmljIEMgdmVyc2lvbi4gVGhlIGlz c3VlIGlzIHRoYXQgMDQwOTFkNg0KPiA+IGludHJvZHVjZXMgYW4gYXNzZW1ibHkgdmVyc2lvbiB0 aGF0J3MgdmVyeSBicm9rZW4uIEl0IGRvZXMgbm90IG9mZmVyDQo+ID4gYW5kIHBlcmZvcm1hbmNl IGltcHJvdmVtZW50IHRvIHRoZSBDIHZlcnNpb24sIGFuZCBicmVha3MgYWxsIHByb2Nlc3NvcnMN Cj4gPiB3aXRob3V0IGhhcmR3YXJlIG1pc2FsaWdubWVudCBzdXBwb3J0DQoNClRoZXJlIG1heSBu ZWVkIHRvIGJlIGEgZmV3IEMgaW1wbGVtZW50YXRpb25zIGZvciBkaWZmZXJlbnQgY3B1DQppbnN0 cnVjdGlvbiBzZXRzLg0KV2hpbGUgdGhlIGNvbXBpbGVyIG1pZ2h0IG1hbmFnZSB0byBEVFJUIChv ciB0aGUgd3JvbmcgdGhpbmcgZ2l2ZW4NCnRoZSByaWdodCBzb3VyY2UpIHVzaW5nIGEgbG9vcCB0 aGF0IG1hdGNoZXMgdGhlIGluc3RydWN0aW9uIHNldA0KaXMgYSBnb29kIGlkZWEuDQoNCkZvciBp bnN0YW5jZSwgeDg2IGNhbiBkbyAqKHJlZ18xICsgcmVnXzIgKiAoMXwyfDR8OCkgKyBjb25zdGFu dCkNCnNvIHlvdSBjYW4gaW5jcmVtZW50IHJlZ18yIGFuZCB1c2UgaXQgZm9yIGJvdGggYnVmZmVy cyB3aGlsZQ0Kc3RpbGwgdW5yb2xsaW5nIGVub3VnaCB0byBoaXQgbWVtb3J5IGJhbmR3aWR0aC4N Cg0KV2l0aCBvbmx5ICoocmVnXzEgKyBjb25zdGFudCkgeW91IG5lZWQgdG8gaW5jcmVtZW50IGJv dGggdGhlDQpzb3VyY2UgYW5kIGRlc3RpbmF0aW9uIGFkZHJlc3Nlcy4NCg0KT1RPSCB5b3UgY2Fu IHNhdmUgYW4gaW5zdHJ1Y3Rpb24gb24geDg2IGJ5IGFkZGluZyB0byAncmVnXzInDQp1bnRpbCBp dCBiZWNvbWVzIHplcm8gKHNvIHlvdSBkb24ndCBuZWVkIGFkZCwgY21wIGFuZCBqbXApLg0KDQpC dXQgYSBtaXBzLWxpa2UgaW5zdHJ1Y3Rpb24gc2V0IChpbmNsdWRlcyByaXNjdiBhbmQgbmlvczIp DQpoYXMgJ2NvbXBhcmUgYW5kIGJyYW5jaCcgc28geW91IG9ubHkgZXZlciBuZWVkIG9uZSBpbnN0 cnVjdGlvbg0KYXQgdGhlIGVuZCBvZiB0aGUgbG9vcC4NCg0KSGF2aW5nIHRvIGhhbmRsZSBtaXNh bGlnbmVkIGNvcGllcyBpcyBhbm90aGVyIGRpc3RpbmN0IGlzc3VlLg0KRm9yIHNvbWUgMzJiaXQg Y3B1IGJ5dGUgY29waWVzIG1heSBiZSBhcyBmYXN0IGFzIGFueSBzaGlmdA0KYW5kIG1hc2sgY29k ZS4NCg0KPiA+ICh5ZXMsIGZpcm13YXJlIGlzIGV4cGVjdGVkIHRvDQo+ID4gdHJhcCBhbmQgaGFu ZGxlIHRoZXNlLCBidXQgdGhleSBhcmUgcGFpbmZ1bGx5IHNsb3cpLg0KDQpZZXMsIHRvIHRoZSBw b2ludCB3aGVyZSB0aGUgc3lzdGVtIHNob3VsZCBqdXN0IHBhbmljIGFuZA0KZm9yY2UgeW91IHRv IGZpeCB0aGUgY29kZS4NCg0KV2hlbiBJIHdlcmUgYSBsYWQgd2UgZm9yY2VkIGV2ZXJ5b25lIHRv IGZpeCB0aGVyZSBjb2RlDQpzbyBpdCB3b3VsZCBydW4gb24gc3BhcmMuDQoNCglEYXZpZA0KDQot DQpSZWdpc3RlcmVkIEFkZHJlc3MgTGFrZXNpZGUsIEJyYW1sZXkgUm9hZCwgTW91bnQgRmFybSwg TWlsdG9uIEtleW5lcywgTUsxIDFQVCwgVUsNClJlZ2lzdHJhdGlvbiBObzogMTM5NzM4NiAoV2Fs ZXMpDQo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD747C48BE5 for ; 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Tue, 15 Jun 2021 15:08:27 +0100 Received: from AcuMS.Aculab.com ([fe80::994c:f5c2:35d6:9b65]) by AcuMS.aculab.com ([fe80::994c:f5c2:35d6:9b65%12]) with mapi id 15.00.1497.018; Tue, 15 Jun 2021 15:08:27 +0100 From: David Laight To: 'Bin Meng' , Gary Guo CC: Palmer Dabbelt , Paul Walmsley , "aou@eecs.berkeley.edu" , "nickhu@andestech.com" , "nylon7@andestech.com" , "linux-riscv@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH] riscv: fix memmove and optimise memcpy when misalign Thread-Topic: [PATCH] riscv: fix memmove and optimise memcpy when misalign Thread-Index: AQHXT3WL0lTofUR6TU66MVYMSFr0J6rxS6gAgCPtaRCAAANAsA== Date: Tue, 15 Jun 2021 14:08:27 +0000 Message-ID: <44e4e70491164ef5b777d06f48b6684f@AcuMS.aculab.com> References: <20210522232256.00003f08@garyguo.net> <17637b10e71b41b89126cbb1b2fa61cf@AcuMS.aculab.com> <20210525153431.0000508d@garyguo.net> In-Reply-To: Accept-Language: en-GB, en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.202.205.107] MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=C51A453 smtp.mailfrom=david.laight@aculab.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: aculab.com Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210615_070901_606847_58044EB8 X-CRM114-Status: GOOD ( 16.65 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Bin Meng > Sent: 15 June 2021 14:40 ... > > I prefer C versions as well, and actually before commit 04091d6 we are > > indeed using the generic C version. The issue is that 04091d6 > > introduces an assembly version that's very broken. It does not offer > > and performance improvement to the C version, and breaks all processors > > without hardware misalignment support There may need to be a few C implementations for different cpu instruction sets. While the compiler might manage to DTRT (or the wrong thing given the right source) using a loop that matches the instruction set is a good idea. For instance, x86 can do *(reg_1 + reg_2 * (1|2|4|8) + constant) so you can increment reg_2 and use it for both buffers while still unrolling enough to hit memory bandwidth. With only *(reg_1 + constant) you need to increment both the source and destination addresses. OTOH you can save an instruction on x86 by adding to 'reg_2' until it becomes zero (so you don't need add, cmp and jmp). But a mips-like instruction set (includes riscv and nios2) has 'compare and branch' so you only ever need one instruction at the end of the loop. Having to handle misaligned copies is another distinct issue. For some 32bit cpu byte copies may be as fast as any shift and mask code. > > (yes, firmware is expected to > > trap and handle these, but they are painfully slow). Yes, to the point where the system should just panic and force you to fix the code. When I were a lad we forced everyone to fix there code so it would run on sparc. David - Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK Registration No: 1397386 (Wales) _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv