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[188.85.180.35]) by smtp.gmail.com with ESMTPSA id o10-20020a5d47ca000000b0020a992ce36esm12918917wrc.1.2022.04.26.03.28.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 26 Apr 2022 03:28:23 -0700 (PDT) Message-ID: <4561a64e-0675-8f26-3c0c-53e422b65ab8@gmail.com> Date: Tue, 26 Apr 2022 12:28:21 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile Content-Language: en-US To: "allen-kh.cheng" , Rob Herring , Kishon Vijay Abraham I , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck Cc: hsinyi@chromium.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-watchdog@vger.kernel.org References: <20220311130732.22706-1-allen-kh.cheng@mediatek.com> <20220311130732.22706-5-allen-kh.cheng@mediatek.com> <8c27fbbdf109b53cff5472e89da83741bee4b202.camel@mediatek.com> From: Matthias Brugger In-Reply-To: <8c27fbbdf109b53cff5472e89da83741bee4b202.camel@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220426_032828_839956_BC8FB9DB X-CRM114-Status: GOOD ( 24.07 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org Hi Allen, On 30/03/2022 09:34, allen-kh.cheng wrote: > Hi Matthias, > > On Tue, 2022-03-29 at 16:56 +0200, Matthias Brugger wrote: >> >> On 11/03/2022 14:07, Allen-KH Cheng wrote: >>> From: Allen-KH Cheng >>> >>> Add basic chip support for Mediatek MT8186. >>> >> >> Thanks for your patch. I would love to wait a bit longer to see if we >> can get >> the clock driver accepted. This way we could get rid of all the dummy >> clocks >> defined in here. >> >> Please send a new version once the clock driver is accepeted by >> Stephen, or ping >> this series in a few month. >> >> Thanks, >> Matthias >> > > Sure, that's great. > > I will send a new version after the clock driver is accepted. > I've seen that the clock driver got accepted. Can you please send a new patch adding the correct clocks to the nodes? Thanks a lot. Matthias > Thanks, > Allen > >>> Signed-off-by: Allen-KH Cheng >>> --- >>> arch/arm64/boot/dts/mediatek/Makefile | 1 + >>> arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++ >>> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356 >>> ++++++++++++++++++++ >>> 3 files changed, 381 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts >>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi >>> >>> diff --git a/arch/arm64/boot/dts/mediatek/Makefile >>> b/arch/arm64/boot/dts/mediatek/Makefile >>> index 8c1e18032f9f..d32fdcf9afc6 100644 >>> --- a/arch/arm64/boot/dts/mediatek/Makefile >>> +++ b/arch/arm64/boot/dts/mediatek/Makefile >>> @@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui- >>> kodama-sku32.dtb >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb >>> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts >>> b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts >>> new file mode 100644 >>> index 000000000000..eb23d1f19f87 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts >>> @@ -0,0 +1,24 @@ >>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT) >>> +/* >>> + * Copyright (C) 2022 MediaTek Inc. >>> + */ >>> +/dts-v1/; >>> +#include "mt8186.dtsi" >>> + >>> +/ { >>> + model = "MediaTek MT8186 evaluation board"; >>> + compatible = "mediatek,mt8186-evb", "mediatek,mt8186"; >>> + >>> + aliases { >>> + serial0 = &uart0; >>> + }; >>> + >>> + chosen { >>> + stdout-path = "serial0:921600n8"; >>> + }; >>> + >>> + memory { >>> + device_type = "memory"; >>> + reg = <0 0x40000000 0 0x80000000>; >>> + }; >>> +}; >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi >>> b/arch/arm64/boot/dts/mediatek/mt8186.dtsi >>> new file mode 100644 >>> index 000000000000..aa45c75b18c7 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi >>> @@ -0,0 +1,356 @@ >>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT) >>> +/* >>> + * Copyright (C) 2022 MediaTek Inc. >>> + * Author: Allen-KH Cheng >>> + */ >>> +/dts-v1/; >>> + >>> +#include >>> +#include >>> +#include >>> + >>> +/ { >>> + compatible = "mediatek,mt8186"; >>> + interrupt-parent = <&gic>; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + >>> + clk13m: oscillator0 { >>> + compatible = "fixed-clock"; >>> + #clock-cells = <0>; >>> + clock-frequency = <13000000>; >>> + clock-output-names = "clk13m"; >>> + }; >>> + >>> + clk26m: oscillator1 { >>> + compatible = "fixed-clock"; >>> + #clock-cells = <0>; >>> + clock-frequency = <26000000>; >>> + clock-output-names = "clk26m"; >>> + }; >>> + >>> + clk32k: oscillator2 { >>> + compatible = "fixed-clock"; >>> + #clock-cells = <0>; >>> + clock-frequency = <32000>; >>> + clock-output-names = "clk32k"; >>> + }; >>> + >>> + cpus { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + cpu0: cpu@000 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0000>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu1: cpu@100 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0100>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu2: cpu@200 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0200>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu3: cpu@300 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0300>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu4: cpu@400 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0400>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu5: cpu@500 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0500>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu6: cpu@600 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a75", "arm,armv8"; >>> + reg = <0x0600>; >>> + enable-method = "psci"; >>> + clock-frequency = <2050000000>; >>> + cpu-idle-states = <&cpuoff_b &clusteroff_b>; >>> + next-level-cache = <&l2_1>; >>> + }; >>> + >>> + cpu7: cpu@700 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a75", "arm,armv8"; >>> + reg = <0x0700>; >>> + enable-method = "psci"; >>> + clock-frequency = <2050000000>; >>> + cpu-idle-states = <&cpuoff_b &clusteroff_b>; >>> + next-level-cache = <&l2_1>; >>> + }; >>> + >>> + cpu-map { >>> + cluster0 { >>> + core0 { >>> + cpu = <&cpu0>; >>> + }; >>> + >>> + core1 { >>> + cpu = <&cpu1>; >>> + }; >>> + >>> + core2 { >>> + cpu = <&cpu2>; >>> + }; >>> + >>> + core3 { >>> + cpu = <&cpu3>; >>> + }; >>> + >>> + core4 { >>> + cpu = <&cpu4>; >>> + }; >>> + >>> + core5 { >>> + cpu = <&cpu5>; >>> + }; >>> + }; >>> + >>> + cluster1 { >>> + core0 { >>> + cpu = <&cpu6>; >>> + }; >>> + >>> + core1 { >>> + cpu = <&cpu7>; >>> + }; >>> + }; >>> + }; >>> + >>> + idle-states { >>> + entry-method = "arm,psci"; >>> + >>> + cpuoff_l: cpu-off-l { >>> + compatible = "arm,idle-state"; >>> + arm,psci-suspend-param = <0x00010001>; >>> + local-timer-stop; >>> + entry-latency-us = <50>; >>> + exit-latency-us = <100>; >>> + min-residency-us = <1600>; >>> + }; >>> + >>> + cpuoff_b: cpu-off-b { >>> + compatible = "arm,idle-state"; >>> + arm,psci-suspend-param = <0x00010001>; >>> + local-timer-stop; >>> + entry-latency-us = <50>; >>> + exit-latency-us = <100>; >>> + min-residency-us = <1400>; >>> + }; >>> + >>> + clusteroff_l: cluster-off-l { >>> + compatible = "arm,idle-state"; >>> + arm,psci-suspend-param = <0x01010001>; >>> + local-timer-stop; >>> + entry-latency-us = <100>; >>> + exit-latency-us = <250>; >>> + min-residency-us = <2100>; >>> + }; >>> + >>> + clusteroff_b: cluster-off-b { >>> + compatible = "arm,idle-state"; >>> + arm,psci-suspend-param = <0x01010001>; >>> + local-timer-stop; >>> + entry-latency-us = <100>; >>> + exit-latency-us = <250>; >>> + min-residency-us = <1900>; >>> + }; >>> + }; >>> + >>> + l2_0: l2-cache0 { >>> + compatible = "cache"; >>> + next-level-cache = <&l3_0>; >>> + }; >>> + >>> + l2_1: l2-cache1 { >>> + compatible = "cache"; >>> + next-level-cache = <&l3_0>; >>> + }; >>> + >>> + l3_0: l3-cache { >>> + compatible = "cache"; >>> + }; >>> + }; >>> + >>> + psci { >>> + compatible = "arm,psci-1.0"; >>> + method = "smc"; >>> + }; >>> + >>> + timer: timer { >>> + compatible = "arm,armv8-timer"; >>> + interrupt-parent = <&gic>; >>> + interrupts = , >>> + , >>> + , >>> + ; >>> + clock-frequency = <13000000>; >>> + }; >>> + >>> + soc { >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + compatible = "simple-bus"; >>> + ranges; >>> + >>> + gic: interrupt-controller@c000000 { >>> + compatible = "arm,gic-v3"; >>> + #interrupt-cells = <3>; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + #redistributor-regions = <1>; >>> + interrupt-parent = <&gic>; >>> + interrupt-controller; >>> + reg = <0 0x0c000000 0 0x40000>, // distributor >>> + <0 0x0c040000 0 0x200000>; // >>> redistributor >>> + interrupts = ; >>> + }; >>> + >>> + watchdog: watchdog@10007000 { >>> + compatible = "mediatek,mt8186-wdt", >>> + "mediatek,mt6589-wdt"; >>> + mediatek,disable-extrst; >>> + reg = <0 0x10007000 0 0x1000>; >>> + #reset-cells = <1>; >>> + }; >>> + >>> + systimer: timer@10017000 { >>> + compatible = "mediatek,mt8186-timer", >>> + "mediatek,mt6765-timer"; >>> + reg = <0 0x10017000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk13m>; >>> + }; >>> + >>> + uart0: serial@11002000 { >>> + compatible = "mediatek,mt8186-uart", >>> + "mediatek,mt6577-uart"; >>> + reg = <0 0x11002000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk26m>, <&clk26m>; >>> + clock-names = "baud", "bus"; >>> + }; >>> + >>> + uart1: serial@11003000 { >>> + compatible = "mediatek,mt8186-uart", >>> + "mediatek,mt6577-uart"; >>> + reg = <0 0x11003000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk26m>, <&clk26m>; >>> + clock-names = "baud", "bus"; >>> + status = "disabled"; >>> + }; >>> + >>> + uart2: serial@11018000 { >>> + compatible = "mediatek,mt8186-uart", >>> + "mediatek,mt6577-uart"; >>> + reg = <0 0x11018000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk26m>, <&clk26m>; >>> + clock-names = "baud", "bus"; >>> + status = "disabled"; >>> + }; >>> + >>> + mmc0: mmc@11230000 { >>> + compatible = "mediatek,mt8186-mmc", >>> + "mediatek,mt8183-mmc"; >>> + reg = <0 0x11230000 0 0x1000>, >>> + <0 0x11cd0000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk26m>, <&clk26m>, <&clk26m>, >>> + <&clk26m>; >>> + clock-names = "source", "hclk", "source_cg", >>> "ahb_clk"; >>> + status = "disabled"; >>> + }; >>> + >>> + mmc1: mmc@11240000 { >>> + compatible = "mediatek,mt8186-mmc", >>> + "mediatek,mt8183-mmc"; >>> + reg = <0 0x11240000 0 0x1000>, >>> + <0 0x11c90000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk26m>, <&clk26m>, <&clk26m>; >>> + clock-names = "source", "hclk", "source_cg"; >>> + status = "disabled"; >>> + }; >>> + >>> + u3phy0: t-phy@11c80000 { >>> + compatible = "mediatek,mt8186-tphy", >>> + "mediatek,generic-tphy-v2"; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + ranges = <0x0 0x0 0x11c80000 0x1000>; >>> + >>> + u2port1: usb2-phy1@0 { >>> + reg = <0x0 0x700>; >>> + clocks = <&clk26m>; >>> + clock-names = "ref"; >>> + #phy-cells = <1>; >>> + }; >>> + >>> + u3port1: usb3-phy1@700 { >>> + reg = <0x700 0x900>; >>> + clocks = <&clk26m>; >>> + clock-names = "ref"; >>> + #phy-cells = <1>; >>> + }; >>> + }; >>> + >>> + u3phy1: t-phy@11ca0000 { >>> + compatible = "mediatek,mt8186-tphy", >>> + "mediatek,generic-tphy-v2"; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + ranges = <0x0 0x0 0x11ca0000 0x1000>; >>> + >>> + u2port0: usb-phy@0 { >>> + reg = <0x0 0x700>; >>> + clocks = <&clk26m>; >>> + clock-names = "ref"; >>> + #phy-cells = <1>; >>> + mediatek,discth = <0x8>; >>> + }; >>> + }; >>> + }; >>> +}; > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4616EC433F5 for ; Tue, 26 Apr 2022 10:35:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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[188.85.180.35]) by smtp.gmail.com with ESMTPSA id o10-20020a5d47ca000000b0020a992ce36esm12918917wrc.1.2022.04.26.03.28.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 26 Apr 2022 03:28:23 -0700 (PDT) Message-ID: <4561a64e-0675-8f26-3c0c-53e422b65ab8@gmail.com> Date: Tue, 26 Apr 2022 12:28:21 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile Content-Language: en-US To: "allen-kh.cheng" , Rob Herring , Kishon Vijay Abraham I , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck Cc: hsinyi@chromium.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-watchdog@vger.kernel.org References: <20220311130732.22706-1-allen-kh.cheng@mediatek.com> <20220311130732.22706-5-allen-kh.cheng@mediatek.com> <8c27fbbdf109b53cff5472e89da83741bee4b202.camel@mediatek.com> From: Matthias Brugger In-Reply-To: <8c27fbbdf109b53cff5472e89da83741bee4b202.camel@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220426_032828_839956_BC8FB9DB X-CRM114-Status: GOOD ( 24.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Allen, On 30/03/2022 09:34, allen-kh.cheng wrote: > Hi Matthias, > > On Tue, 2022-03-29 at 16:56 +0200, Matthias Brugger wrote: >> >> On 11/03/2022 14:07, Allen-KH Cheng wrote: >>> From: Allen-KH Cheng >>> >>> Add basic chip support for Mediatek MT8186. >>> >> >> Thanks for your patch. I would love to wait a bit longer to see if we >> can get >> the clock driver accepted. This way we could get rid of all the dummy >> clocks >> defined in here. >> >> Please send a new version once the clock driver is accepeted by >> Stephen, or ping >> this series in a few month. >> >> Thanks, >> Matthias >> > > Sure, that's great. > > I will send a new version after the clock driver is accepted. > I've seen that the clock driver got accepted. Can you please send a new patch adding the correct clocks to the nodes? Thanks a lot. Matthias > Thanks, > Allen > >>> Signed-off-by: Allen-KH Cheng >>> --- >>> arch/arm64/boot/dts/mediatek/Makefile | 1 + >>> arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++ >>> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356 >>> ++++++++++++++++++++ >>> 3 files changed, 381 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts >>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi >>> >>> diff --git a/arch/arm64/boot/dts/mediatek/Makefile >>> b/arch/arm64/boot/dts/mediatek/Makefile >>> index 8c1e18032f9f..d32fdcf9afc6 100644 >>> --- a/arch/arm64/boot/dts/mediatek/Makefile >>> +++ b/arch/arm64/boot/dts/mediatek/Makefile >>> @@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui- >>> kodama-sku32.dtb >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb >>> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts >>> b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts >>> new file mode 100644 >>> index 000000000000..eb23d1f19f87 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts >>> @@ -0,0 +1,24 @@ >>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT) >>> +/* >>> + * Copyright (C) 2022 MediaTek Inc. >>> + */ >>> +/dts-v1/; >>> +#include "mt8186.dtsi" >>> + >>> +/ { >>> + model = "MediaTek MT8186 evaluation board"; >>> + compatible = "mediatek,mt8186-evb", "mediatek,mt8186"; >>> + >>> + aliases { >>> + serial0 = &uart0; >>> + }; >>> + >>> + chosen { >>> + stdout-path = "serial0:921600n8"; >>> + }; >>> + >>> + memory { >>> + device_type = "memory"; >>> + reg = <0 0x40000000 0 0x80000000>; >>> + }; >>> +}; >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi >>> b/arch/arm64/boot/dts/mediatek/mt8186.dtsi >>> new file mode 100644 >>> index 000000000000..aa45c75b18c7 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi >>> @@ -0,0 +1,356 @@ >>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT) >>> +/* >>> + * Copyright (C) 2022 MediaTek Inc. >>> + * Author: Allen-KH Cheng >>> + */ >>> +/dts-v1/; >>> + >>> +#include >>> +#include >>> +#include >>> + >>> +/ { >>> + compatible = "mediatek,mt8186"; >>> + interrupt-parent = <&gic>; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + >>> + clk13m: oscillator0 { >>> + compatible = "fixed-clock"; >>> + #clock-cells = <0>; >>> + clock-frequency = <13000000>; >>> + clock-output-names = "clk13m"; >>> + }; >>> + >>> + clk26m: oscillator1 { >>> + compatible = "fixed-clock"; >>> + #clock-cells = <0>; >>> + clock-frequency = <26000000>; >>> + clock-output-names = "clk26m"; >>> + }; >>> + >>> + clk32k: oscillator2 { >>> + compatible = "fixed-clock"; >>> + #clock-cells = <0>; >>> + clock-frequency = <32000>; >>> + clock-output-names = "clk32k"; >>> + }; >>> + >>> + cpus { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + cpu0: cpu@000 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0000>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu1: cpu@100 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0100>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu2: cpu@200 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0200>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu3: cpu@300 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0300>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu4: cpu@400 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0400>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu5: cpu@500 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0500>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu6: cpu@600 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a75", "arm,armv8"; >>> + reg = <0x0600>; >>> + enable-method = "psci"; >>> + clock-frequency = <2050000000>; >>> + cpu-idle-states = <&cpuoff_b &clusteroff_b>; >>> + next-level-cache = <&l2_1>; >>> + }; >>> + >>> + cpu7: cpu@700 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a75", "arm,armv8"; >>> + reg = <0x0700>; >>> + enable-method = "psci"; >>> + clock-frequency = <2050000000>; >>> + cpu-idle-states = <&cpuoff_b &clusteroff_b>; >>> + next-level-cache = <&l2_1>; >>> + }; >>> + >>> + cpu-map { >>> + cluster0 { >>> + core0 { >>> + cpu = <&cpu0>; >>> + }; >>> + >>> + core1 { >>> + cpu = <&cpu1>; >>> + }; >>> + >>> + core2 { >>> + cpu = <&cpu2>; >>> + }; >>> + >>> + core3 { >>> + cpu = <&cpu3>; >>> + }; >>> + >>> + core4 { >>> + cpu = <&cpu4>; >>> + }; >>> + >>> + core5 { >>> + cpu = <&cpu5>; >>> + }; >>> + }; >>> + >>> + cluster1 { >>> + core0 { >>> + cpu = <&cpu6>; >>> + }; >>> + >>> + core1 { >>> + cpu = <&cpu7>; >>> + }; >>> + }; >>> + }; >>> + >>> + idle-states { >>> + entry-method = "arm,psci"; >>> + >>> + cpuoff_l: cpu-off-l { >>> + compatible = "arm,idle-state"; >>> + arm,psci-suspend-param = <0x00010001>; >>> + local-timer-stop; >>> + entry-latency-us = <50>; >>> + exit-latency-us = <100>; >>> + min-residency-us = <1600>; >>> + }; >>> + >>> + cpuoff_b: cpu-off-b { >>> + compatible = "arm,idle-state"; >>> + arm,psci-suspend-param = <0x00010001>; >>> + local-timer-stop; >>> + entry-latency-us = <50>; >>> + exit-latency-us = <100>; >>> + min-residency-us = <1400>; >>> + }; >>> + >>> + clusteroff_l: cluster-off-l { >>> + compatible = "arm,idle-state"; >>> + arm,psci-suspend-param = <0x01010001>; >>> + local-timer-stop; >>> + entry-latency-us = <100>; >>> + exit-latency-us = <250>; >>> + min-residency-us = <2100>; >>> + }; >>> + >>> + clusteroff_b: cluster-off-b { >>> + compatible = "arm,idle-state"; >>> + arm,psci-suspend-param = <0x01010001>; >>> + local-timer-stop; >>> + entry-latency-us = <100>; >>> + exit-latency-us = <250>; >>> + min-residency-us = <1900>; >>> + }; >>> + }; >>> + >>> + l2_0: l2-cache0 { >>> + compatible = "cache"; >>> + next-level-cache = <&l3_0>; >>> + }; >>> + >>> + l2_1: l2-cache1 { >>> + compatible = "cache"; >>> + next-level-cache = <&l3_0>; >>> + }; >>> + >>> + l3_0: l3-cache { >>> + compatible = "cache"; >>> + }; >>> + }; >>> + >>> + psci { >>> + compatible = "arm,psci-1.0"; >>> + method = "smc"; >>> + }; >>> + >>> + timer: timer { >>> + compatible = "arm,armv8-timer"; >>> + interrupt-parent = <&gic>; >>> + interrupts = , >>> + , >>> + , >>> + ; >>> + clock-frequency = <13000000>; >>> + }; >>> + >>> + soc { >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + compatible = "simple-bus"; >>> + ranges; >>> + >>> + gic: interrupt-controller@c000000 { >>> + compatible = "arm,gic-v3"; >>> + #interrupt-cells = <3>; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + #redistributor-regions = <1>; >>> + interrupt-parent = <&gic>; >>> + interrupt-controller; >>> + reg = <0 0x0c000000 0 0x40000>, // distributor >>> + <0 0x0c040000 0 0x200000>; // >>> redistributor >>> + interrupts = ; >>> + }; >>> + >>> + watchdog: watchdog@10007000 { >>> + compatible = "mediatek,mt8186-wdt", >>> + "mediatek,mt6589-wdt"; >>> + mediatek,disable-extrst; >>> + reg = <0 0x10007000 0 0x1000>; >>> + #reset-cells = <1>; >>> + }; >>> + >>> + systimer: timer@10017000 { >>> + compatible = "mediatek,mt8186-timer", >>> + "mediatek,mt6765-timer"; >>> + reg = <0 0x10017000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk13m>; >>> + }; >>> + >>> + uart0: serial@11002000 { >>> + compatible = "mediatek,mt8186-uart", >>> + "mediatek,mt6577-uart"; >>> + reg = <0 0x11002000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk26m>, <&clk26m>; >>> + clock-names = "baud", "bus"; >>> + }; >>> + >>> + uart1: serial@11003000 { >>> + compatible = "mediatek,mt8186-uart", >>> + "mediatek,mt6577-uart"; >>> + reg = <0 0x11003000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk26m>, <&clk26m>; >>> + clock-names = "baud", "bus"; >>> + status = "disabled"; >>> + }; >>> + >>> + uart2: serial@11018000 { >>> + compatible = "mediatek,mt8186-uart", >>> + "mediatek,mt6577-uart"; >>> + reg = <0 0x11018000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk26m>, <&clk26m>; >>> + clock-names = "baud", "bus"; >>> + status = "disabled"; >>> + }; >>> + >>> + mmc0: mmc@11230000 { >>> + compatible = "mediatek,mt8186-mmc", >>> + "mediatek,mt8183-mmc"; >>> + reg = <0 0x11230000 0 0x1000>, >>> + <0 0x11cd0000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk26m>, <&clk26m>, <&clk26m>, >>> + <&clk26m>; >>> + clock-names = "source", "hclk", "source_cg", >>> "ahb_clk"; >>> + status = "disabled"; >>> + }; >>> + >>> + mmc1: mmc@11240000 { >>> + compatible = "mediatek,mt8186-mmc", >>> + "mediatek,mt8183-mmc"; >>> + reg = <0 0x11240000 0 0x1000>, >>> + <0 0x11c90000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk26m>, <&clk26m>, <&clk26m>; >>> + clock-names = "source", "hclk", "source_cg"; >>> + status = "disabled"; >>> + }; >>> + >>> + u3phy0: t-phy@11c80000 { >>> + compatible = "mediatek,mt8186-tphy", >>> + "mediatek,generic-tphy-v2"; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + ranges = <0x0 0x0 0x11c80000 0x1000>; >>> + >>> + u2port1: usb2-phy1@0 { >>> + reg = <0x0 0x700>; >>> + clocks = <&clk26m>; >>> + clock-names = "ref"; >>> + #phy-cells = <1>; >>> + }; >>> + >>> + u3port1: usb3-phy1@700 { >>> + reg = <0x700 0x900>; >>> + clocks = <&clk26m>; >>> + clock-names = "ref"; >>> + #phy-cells = <1>; >>> + }; >>> + }; >>> + >>> + u3phy1: t-phy@11ca0000 { >>> + compatible = "mediatek,mt8186-tphy", >>> + "mediatek,generic-tphy-v2"; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + ranges = <0x0 0x0 0x11ca0000 0x1000>; >>> + >>> + u2port0: usb-phy@0 { >>> + reg = <0x0 0x700>; >>> + clocks = <&clk26m>; >>> + clock-names = "ref"; >>> + #phy-cells = <1>; >>> + mediatek,discth = <0x8>; >>> + }; >>> + }; >>> + }; >>> +}; > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71089C4332F for ; Tue, 26 Apr 2022 10:38:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1349296AbiDZKk5 (ORCPT ); Tue, 26 Apr 2022 06:40:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1349673AbiDZKj1 (ORCPT ); Tue, 26 Apr 2022 06:39:27 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C5B123BF2; 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[188.85.180.35]) by smtp.gmail.com with ESMTPSA id o10-20020a5d47ca000000b0020a992ce36esm12918917wrc.1.2022.04.26.03.28.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 26 Apr 2022 03:28:23 -0700 (PDT) Message-ID: <4561a64e-0675-8f26-3c0c-53e422b65ab8@gmail.com> Date: Tue, 26 Apr 2022 12:28:21 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v4 4/4] arm64: dts: Add Mediatek SoC MT8186 dts and evaluation board and Makefile Content-Language: en-US To: "allen-kh.cheng" , Rob Herring , Kishon Vijay Abraham I , Daniel Lezcano , Thomas Gleixner , Wim Van Sebroeck , Guenter Roeck Cc: hsinyi@chromium.org, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-watchdog@vger.kernel.org References: <20220311130732.22706-1-allen-kh.cheng@mediatek.com> <20220311130732.22706-5-allen-kh.cheng@mediatek.com> <8c27fbbdf109b53cff5472e89da83741bee4b202.camel@mediatek.com> From: Matthias Brugger In-Reply-To: <8c27fbbdf109b53cff5472e89da83741bee4b202.camel@mediatek.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Allen, On 30/03/2022 09:34, allen-kh.cheng wrote: > Hi Matthias, > > On Tue, 2022-03-29 at 16:56 +0200, Matthias Brugger wrote: >> >> On 11/03/2022 14:07, Allen-KH Cheng wrote: >>> From: Allen-KH Cheng >>> >>> Add basic chip support for Mediatek MT8186. >>> >> >> Thanks for your patch. I would love to wait a bit longer to see if we >> can get >> the clock driver accepted. This way we could get rid of all the dummy >> clocks >> defined in here. >> >> Please send a new version once the clock driver is accepeted by >> Stephen, or ping >> this series in a few month. >> >> Thanks, >> Matthias >> > > Sure, that's great. > > I will send a new version after the clock driver is accepted. > I've seen that the clock driver got accepted. Can you please send a new patch adding the correct clocks to the nodes? Thanks a lot. Matthias > Thanks, > Allen > >>> Signed-off-by: Allen-KH Cheng >>> --- >>> arch/arm64/boot/dts/mediatek/Makefile | 1 + >>> arch/arm64/boot/dts/mediatek/mt8186-evb.dts | 24 ++ >>> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 356 >>> ++++++++++++++++++++ >>> 3 files changed, 381 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-evb.dts >>> create mode 100644 arch/arm64/boot/dts/mediatek/mt8186.dtsi >>> >>> diff --git a/arch/arm64/boot/dts/mediatek/Makefile >>> b/arch/arm64/boot/dts/mediatek/Makefile >>> index 8c1e18032f9f..d32fdcf9afc6 100644 >>> --- a/arch/arm64/boot/dts/mediatek/Makefile >>> +++ b/arch/arm64/boot/dts/mediatek/Makefile >>> @@ -37,5 +37,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui- >>> kodama-sku32.dtb >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb >>> +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb >>> dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8186-evb.dts >>> b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts >>> new file mode 100644 >>> index 000000000000..eb23d1f19f87 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/mediatek/mt8186-evb.dts >>> @@ -0,0 +1,24 @@ >>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT) >>> +/* >>> + * Copyright (C) 2022 MediaTek Inc. >>> + */ >>> +/dts-v1/; >>> +#include "mt8186.dtsi" >>> + >>> +/ { >>> + model = "MediaTek MT8186 evaluation board"; >>> + compatible = "mediatek,mt8186-evb", "mediatek,mt8186"; >>> + >>> + aliases { >>> + serial0 = &uart0; >>> + }; >>> + >>> + chosen { >>> + stdout-path = "serial0:921600n8"; >>> + }; >>> + >>> + memory { >>> + device_type = "memory"; >>> + reg = <0 0x40000000 0 0x80000000>; >>> + }; >>> +}; >>> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi >>> b/arch/arm64/boot/dts/mediatek/mt8186.dtsi >>> new file mode 100644 >>> index 000000000000..aa45c75b18c7 >>> --- /dev/null >>> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi >>> @@ -0,0 +1,356 @@ >>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT) >>> +/* >>> + * Copyright (C) 2022 MediaTek Inc. >>> + * Author: Allen-KH Cheng >>> + */ >>> +/dts-v1/; >>> + >>> +#include >>> +#include >>> +#include >>> + >>> +/ { >>> + compatible = "mediatek,mt8186"; >>> + interrupt-parent = <&gic>; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + >>> + clk13m: oscillator0 { >>> + compatible = "fixed-clock"; >>> + #clock-cells = <0>; >>> + clock-frequency = <13000000>; >>> + clock-output-names = "clk13m"; >>> + }; >>> + >>> + clk26m: oscillator1 { >>> + compatible = "fixed-clock"; >>> + #clock-cells = <0>; >>> + clock-frequency = <26000000>; >>> + clock-output-names = "clk26m"; >>> + }; >>> + >>> + clk32k: oscillator2 { >>> + compatible = "fixed-clock"; >>> + #clock-cells = <0>; >>> + clock-frequency = <32000>; >>> + clock-output-names = "clk32k"; >>> + }; >>> + >>> + cpus { >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + cpu0: cpu@000 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0000>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu1: cpu@100 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0100>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu2: cpu@200 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0200>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu3: cpu@300 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0300>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu4: cpu@400 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0400>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu5: cpu@500 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a55", "arm,armv8"; >>> + reg = <0x0500>; >>> + enable-method = "psci"; >>> + clock-frequency = <2000000000>; >>> + cpu-idle-states = <&cpuoff_l &clusteroff_l>; >>> + next-level-cache = <&l2_0>; >>> + }; >>> + >>> + cpu6: cpu@600 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a75", "arm,armv8"; >>> + reg = <0x0600>; >>> + enable-method = "psci"; >>> + clock-frequency = <2050000000>; >>> + cpu-idle-states = <&cpuoff_b &clusteroff_b>; >>> + next-level-cache = <&l2_1>; >>> + }; >>> + >>> + cpu7: cpu@700 { >>> + device_type = "cpu"; >>> + compatible = "arm,cortex-a75", "arm,armv8"; >>> + reg = <0x0700>; >>> + enable-method = "psci"; >>> + clock-frequency = <2050000000>; >>> + cpu-idle-states = <&cpuoff_b &clusteroff_b>; >>> + next-level-cache = <&l2_1>; >>> + }; >>> + >>> + cpu-map { >>> + cluster0 { >>> + core0 { >>> + cpu = <&cpu0>; >>> + }; >>> + >>> + core1 { >>> + cpu = <&cpu1>; >>> + }; >>> + >>> + core2 { >>> + cpu = <&cpu2>; >>> + }; >>> + >>> + core3 { >>> + cpu = <&cpu3>; >>> + }; >>> + >>> + core4 { >>> + cpu = <&cpu4>; >>> + }; >>> + >>> + core5 { >>> + cpu = <&cpu5>; >>> + }; >>> + }; >>> + >>> + cluster1 { >>> + core0 { >>> + cpu = <&cpu6>; >>> + }; >>> + >>> + core1 { >>> + cpu = <&cpu7>; >>> + }; >>> + }; >>> + }; >>> + >>> + idle-states { >>> + entry-method = "arm,psci"; >>> + >>> + cpuoff_l: cpu-off-l { >>> + compatible = "arm,idle-state"; >>> + arm,psci-suspend-param = <0x00010001>; >>> + local-timer-stop; >>> + entry-latency-us = <50>; >>> + exit-latency-us = <100>; >>> + min-residency-us = <1600>; >>> + }; >>> + >>> + cpuoff_b: cpu-off-b { >>> + compatible = "arm,idle-state"; >>> + arm,psci-suspend-param = <0x00010001>; >>> + local-timer-stop; >>> + entry-latency-us = <50>; >>> + exit-latency-us = <100>; >>> + min-residency-us = <1400>; >>> + }; >>> + >>> + clusteroff_l: cluster-off-l { >>> + compatible = "arm,idle-state"; >>> + arm,psci-suspend-param = <0x01010001>; >>> + local-timer-stop; >>> + entry-latency-us = <100>; >>> + exit-latency-us = <250>; >>> + min-residency-us = <2100>; >>> + }; >>> + >>> + clusteroff_b: cluster-off-b { >>> + compatible = "arm,idle-state"; >>> + arm,psci-suspend-param = <0x01010001>; >>> + local-timer-stop; >>> + entry-latency-us = <100>; >>> + exit-latency-us = <250>; >>> + min-residency-us = <1900>; >>> + }; >>> + }; >>> + >>> + l2_0: l2-cache0 { >>> + compatible = "cache"; >>> + next-level-cache = <&l3_0>; >>> + }; >>> + >>> + l2_1: l2-cache1 { >>> + compatible = "cache"; >>> + next-level-cache = <&l3_0>; >>> + }; >>> + >>> + l3_0: l3-cache { >>> + compatible = "cache"; >>> + }; >>> + }; >>> + >>> + psci { >>> + compatible = "arm,psci-1.0"; >>> + method = "smc"; >>> + }; >>> + >>> + timer: timer { >>> + compatible = "arm,armv8-timer"; >>> + interrupt-parent = <&gic>; >>> + interrupts = , >>> + , >>> + , >>> + ; >>> + clock-frequency = <13000000>; >>> + }; >>> + >>> + soc { >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + compatible = "simple-bus"; >>> + ranges; >>> + >>> + gic: interrupt-controller@c000000 { >>> + compatible = "arm,gic-v3"; >>> + #interrupt-cells = <3>; >>> + #address-cells = <2>; >>> + #size-cells = <2>; >>> + #redistributor-regions = <1>; >>> + interrupt-parent = <&gic>; >>> + interrupt-controller; >>> + reg = <0 0x0c000000 0 0x40000>, // distributor >>> + <0 0x0c040000 0 0x200000>; // >>> redistributor >>> + interrupts = ; >>> + }; >>> + >>> + watchdog: watchdog@10007000 { >>> + compatible = "mediatek,mt8186-wdt", >>> + "mediatek,mt6589-wdt"; >>> + mediatek,disable-extrst; >>> + reg = <0 0x10007000 0 0x1000>; >>> + #reset-cells = <1>; >>> + }; >>> + >>> + systimer: timer@10017000 { >>> + compatible = "mediatek,mt8186-timer", >>> + "mediatek,mt6765-timer"; >>> + reg = <0 0x10017000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk13m>; >>> + }; >>> + >>> + uart0: serial@11002000 { >>> + compatible = "mediatek,mt8186-uart", >>> + "mediatek,mt6577-uart"; >>> + reg = <0 0x11002000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk26m>, <&clk26m>; >>> + clock-names = "baud", "bus"; >>> + }; >>> + >>> + uart1: serial@11003000 { >>> + compatible = "mediatek,mt8186-uart", >>> + "mediatek,mt6577-uart"; >>> + reg = <0 0x11003000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk26m>, <&clk26m>; >>> + clock-names = "baud", "bus"; >>> + status = "disabled"; >>> + }; >>> + >>> + uart2: serial@11018000 { >>> + compatible = "mediatek,mt8186-uart", >>> + "mediatek,mt6577-uart"; >>> + reg = <0 0x11018000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk26m>, <&clk26m>; >>> + clock-names = "baud", "bus"; >>> + status = "disabled"; >>> + }; >>> + >>> + mmc0: mmc@11230000 { >>> + compatible = "mediatek,mt8186-mmc", >>> + "mediatek,mt8183-mmc"; >>> + reg = <0 0x11230000 0 0x1000>, >>> + <0 0x11cd0000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk26m>, <&clk26m>, <&clk26m>, >>> + <&clk26m>; >>> + clock-names = "source", "hclk", "source_cg", >>> "ahb_clk"; >>> + status = "disabled"; >>> + }; >>> + >>> + mmc1: mmc@11240000 { >>> + compatible = "mediatek,mt8186-mmc", >>> + "mediatek,mt8183-mmc"; >>> + reg = <0 0x11240000 0 0x1000>, >>> + <0 0x11c90000 0 0x1000>; >>> + interrupts = ; >>> + clocks = <&clk26m>, <&clk26m>, <&clk26m>; >>> + clock-names = "source", "hclk", "source_cg"; >>> + status = "disabled"; >>> + }; >>> + >>> + u3phy0: t-phy@11c80000 { >>> + compatible = "mediatek,mt8186-tphy", >>> + "mediatek,generic-tphy-v2"; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + ranges = <0x0 0x0 0x11c80000 0x1000>; >>> + >>> + u2port1: usb2-phy1@0 { >>> + reg = <0x0 0x700>; >>> + clocks = <&clk26m>; >>> + clock-names = "ref"; >>> + #phy-cells = <1>; >>> + }; >>> + >>> + u3port1: usb3-phy1@700 { >>> + reg = <0x700 0x900>; >>> + clocks = <&clk26m>; >>> + clock-names = "ref"; >>> + #phy-cells = <1>; >>> + }; >>> + }; >>> + >>> + u3phy1: t-phy@11ca0000 { >>> + compatible = "mediatek,mt8186-tphy", >>> + "mediatek,generic-tphy-v2"; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + ranges = <0x0 0x0 0x11ca0000 0x1000>; >>> + >>> + u2port0: usb-phy@0 { >>> + reg = <0x0 0x700>; >>> + clocks = <&clk26m>; >>> + clock-names = "ref"; >>> + #phy-cells = <1>; >>> + mediatek,discth = <0x8>; >>> + }; >>> + }; >>> + }; >>> +}; >