From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:51622)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1bG5Gf-0000lJ-O6
	for qemu-devel@nongnu.org; Thu, 23 Jun 2016 10:06:06 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <rth7680@gmail.com>) id 1bG5Gb-0001WL-HF
	for qemu-devel@nongnu.org; Thu, 23 Jun 2016 10:06:04 -0400
Sender: Richard Henderson <rth7680@gmail.com>
References: <1466599029-3388432-1-git-send-email-afarallax@yandex.ru>
	<5d86b8ba-16e8-e94d-ba7f-e865cbcc938e@twiddle.net>
	<1793281466613020@web5h.yandex.ru>
	<6c24c820-4a26-848c-e62d-88ebce59125d@twiddle.net>
	<201241466676212@web21j.yandex.ru>
From: Richard Henderson <rth@twiddle.net>
Message-ID: <458f40bb-cb58-4e10-2237-a08cb35155bd@twiddle.net>
Date: Thu, 23 Jun 2016 07:05:48 -0700
MIME-Version: 1.0
In-Reply-To: <201241466676212@web21j.yandex.ru>
Content-Type: text/plain; charset=utf-8; format=flowed
Content-Transfer-Encoding: 7bit
Subject: Re: [Qemu-devel] [PATCH v2] Improve the alignment check
 infrastructure
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Sergey Sorokin <afarallax@yandex.ru>, "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>
Cc: Paolo Bonzini <pbonzini@redhat.com>, Peter Crosthwaite <crosthwaite.peter@gmail.com>, Alexander Graf <agraf@suse.de>, "qemu-arm@nongnu.org" <qemu-arm@nongnu.org>, Claudio Fontana <claudio.fontana@huawei.com>, Vassili Karpov <av1474@comtv.ru>

On 06/23/2016 03:03 AM, Sergey Sorokin wrote:
> So what's wrong in this part of the patch?

I think I just misread it.


>
> 22.06.2016, 20:12, "Richard Henderson" <rth@twiddle.net>:
>> On 06/22/2016 09:30 AM, Sergey Sorokin wrote:
>>>>       diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
>>>>       index da10052..3dc38fa 100644
>>>>       --- a/tcg/ppc/tcg-target.inc.c
>>>>       +++ b/tcg/ppc/tcg-target.inc.c
>>>>       @@ -1399,6 +1399,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s,
>>>>      TCGMemOp opc,
>>>>            int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
>>>>            TCGReg base = TCG_AREG0;
>>>>            TCGMemOp s_bits = opc & MO_SIZE;
>>>>       + int a_bits = get_alignment_bits(opc);
>>>>
>>>>            /* Extract the page index, shifted into place for tlb index. */
>>>>            if (TCG_TARGET_REG_BITS == 64) {
>>>>       @@ -1456,14 +1457,21 @@ static TCGReg tcg_out_tlb_read(TCGContext *s,
>>>>      TCGMemOp opc,
>>>>                 * the bottom bits and thus trigger a comparison failure on
>>>>                 * unaligned accesses
>>>>                 */
>>>>       + if (a_bits > 0) {
>>>>       + tcg_debug_assert((((1 << a_bits) - 1) & TLB_FLAGS_MASK) == 0);
>>>>       + } else {
>>>>       + a_bits = s_bits;
>>>>       + }
>>>>                tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0,
>>>>       + (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS);
>>>>
>>>>  ppc32 can certainly support over-alignment, just like every other target. It's
>>>>  just that there are some 32-bit parts that don't support unaligned accesses.
>>>
>>>  I don't understand your point here.
>>
>> ppc32 can support a_bits > s_bits.
>>
>> r~