Re: [PATCH v18 05/25] x86/fpu/xstate: Introduce CET MSR and XSAVES supervisor states - Yu, Yu-cheng

From: "Yu, Yu-cheng" <yu-cheng.yu@intel.com>
To: Dave Hansen <dave.hansen@intel.com>,
	x86@kernel.org, "H. Peter Anvin" <hpa@zytor.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>,
	linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
	linux-mm@kvack.org, linux-arch@vger.kernel.org,
	linux-api@vger.kernel.org, Arnd Bergmann <arnd@arndb.de>,
	Andy Lutomirski <luto@kernel.org>,
	Balbir Singh <bsingharora@gmail.com>,
	Borislav Petkov <bp@alien8.de>,
	Cyrill Gorcunov <gorcunov@gmail.com>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	Eugene Syromiatnikov <esyr@redhat.com>,
	Florian Weimer <fweimer@redhat.com>,
	"H.J. Lu" <hjl.tools@gmail.com>, Jann Horn <jannh@google.com>,
	Jonathan Corbet <corbet@lwn.net>,
	Kees Cook <keescook@chromium.org>,
	Mike Kravetz <mike.kravetz@oracle.com>,
	Nadav Amit <nadav.amit@gmail.com>,
	Oleg Nesterov <oleg@redhat.com>, Pavel Machek <pavel@ucw.cz>,
	Peter Zijlstra <peterz@infradead.org>,
	Randy Dunlap <rdunlap@infradead.org>,
	"Ravi V. Shankar" <ravi.v.shankar@intel.com>,
	Vedvyas Shanbhogue <vedvyas.shanbhogue@intel.com>,
	Dave Martin <Dave.Martin@arm.com>,
	Weijiang Yang <weijiang.yang@intel.com>,
	Pengfei Xu <pengfei.xu@intel.com>,
	Andrew Cooper <andrew.cooper3@citrix.com>
Subject: Re: [PATCH v18 05/25] x86/fpu/xstate: Introduce CET MSR and XSAVES supervisor states
Date: Mon, 1 Feb 2021 14:43:33 -0800	[thread overview]
Message-ID: <465836bd-9c80-fed9-d9af-89275ff810eb@intel.com> (raw)
In-Reply-To: <0a5a80c0-afc7-5f91-9e28-a300e30f1ab3@intel.com>

On 1/29/2021 2:53 PM, Dave Hansen wrote:
> On 1/29/21 2:35 PM, Yu, Yu-cheng wrote:
>>> Andy Cooper just mentioned on IRC about this nugget in the spec:
>>>
>>>      XRSTORS on CET state will do reserved bit and canonicality
>>>      checks on the state in similar manner as done by the WRMSR to
>>>      these state elements.
>>>
>>> We're using copy_kernel_to_xregs_err(), so the #GP *should* be OK.
>>> Could we prove this out in practice, please?
>>>>
>> Do we want to verify that setting reserved bits in CET XSAVES states
>> triggers GP?  Then, yes, I just verified it again.  Thanks for
>> reminding.  Do we have any particular case relating to this?
> 
> I want to confirm that it triggers #GP and kills userspace without the
> kernel WARN'ing or otherwise being visibly unhappy.

For sigreturn, shadow stack pointer is checked against its restore token 
and must be smaller than TASK_SIZE_MAX.  Sigreturn cannot set any 
MSR_IA32_U_CET reserved bits.

> 
> What about the return-to-userspace path after a ptracer writes content
> to the CET fields?   I don't see the same tolerance for errors in
> __fpregs_load_activate(), for instance.
> 

Good thought.  I have not sent out my revised PTRACE patch, but values 
from user will be checked for valid address and reserved bits.

--
Yu-cheng