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envelope-from=dfb1998@web.de; helo=mout.web.de X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?ISO-8859-1?Q?Herv=E9_Poussineau?= , Bernhard Beschow , qemu-devel@nongnu.org, Aurelien Jarno , =?ISO-8859-1?Q?Philippe_Mathieu-Daud=E9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Am 12=2E Februar 2022 19:30:43 MEZ schrieb Peter Maydell : >On Sat, 12 Feb 2022 at 17:02, BALATON Zoltan wro= te: >> >> On Sat, 12 Feb 2022, Peter Maydell wrote: >> > On Sat, 12 Feb 2022 at 13:42, BALATON Zoltan = wrote: >> >> By the way the corresponding member in struct PIIXState in >> >> include/hw/southbridge/piix=2Eh has a comment saying: >> >> >> >> /* This member isn't used=2E Just for save/load compatibility *= / >> >> int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; >> >> >> >> and only seems to be filled in piix3_pre_save() but never used=2E So= what's >> >> the point of this then? Maybe piix3 also uses a bitmap to store thes= e >> >> levels instead? There's a uint64_t pic_levels member above the unuse= d >> >> array but I haven't checked the implementation=2E >> > >> > I think what has happened here is that originally piix3 used >> > the same implementation piix4 currently does -- where it stores >> > locally the value of the (incoming) PCI IRQ levels, and then when it = wants >> > to know the value of the (outgoing) PIC IRQ levels it loops round >> > to effectively OR together all the PCI IRQ levels for those PCI >> > IRQs which are configured to that particular PIC interrupt=2E >> > >> > Then in commit e735b55a8c11 (in 2011) piix3 was changed to call >> > pci_bus_get_irq_level() to get the value of a PCI IRQ rather than >> > looking at its local cache of that information in the pci_irq_levels[= ] >> > array=2E This is the source of the "save/load compatibility" thing -- >> > before doing a vmsave piix3_pre_save() fills in that field so that >> > it appears in the outbound data stream and thus a migration from >> > a new QEMU to an old pre-e735b55a8c11 QEMU will still work=2E (This >> > was important at the time, but could probably be cleaned up now=2E) >> > >> > The next commit after that one is ab431c283e7055bcd, which >> > is an optimization that fixes the equivalent of the "XXX: optimize" >> > marker in the gt64120_pci_set_irq()/piix4 code -- this does >> > something slightly more complicated involving the pic_levels >> > field, in order to avoid having to do the "loop over all the >> > PCI IRQ levels" whenever it needs to set/reset a PIC interrupt=2E >> > >> > We could pick up one or both (or none!) of these two changes >> > for the piix4 code=2E (If we're breaking migration compat anyway >> > we wouldn't need to include the save-load compat part of >> > the first change=2E) >> >> I'm not sure I fully get this=2E Currently (before this series) PIIX4St= ate >> does not seem to have any fields to store irq state (in hw/isa/piix4=2E= c): >> >> struct PIIX4State { >> PCIDevice dev; >> qemu_irq cpu_intr; >> qemu_irq *isa; >> >> RTCState rtc; >> /* Reset Control Register */ >> MemoryRegion rcr_mem; >> uint8_t rcr; >> }; >> >> Patch 1 in this series introduces that by moving it from MaltaState=2E = Then >> we could have a patch 2 to clean it up and change to the way piix3 does= it >> and skip introducing the saving of this array into the migration state= =2E It >> may still break migration but not sure if MaltaState was saved already = so >> this may be already missing from migration anyway and if we do the same= as >> piix3 then maybe we don't need to change the piix4 state either (as thi= s >> is saved as part of the PCIHost state?) but I don't know much about thi= s >> so maybe I'm wrong=2E > >Yeah, that would work -- we weren't saving the old gt64xxx_pci=2Ec >pci_irq_levels[] global, so we don't break anything that wasn't >already broken by not putting the newly-introduced PIIX4State >array into migration state=2E Then when we do the equivalent of >e735b55a8c11 the array can just be deleted again=2E (We can't >conveniently switch to using pci_bus_get_irq_level() before doing >patch 1 of this series, because we need the pointer to the >piix4 device object and gt64120_pci_set_irq() is only passed >a pointer directly to a qemu_irq array=2E) > >> In any case PIIX3 and PIIX4 state seem to be different so there's no >> reason to worry aobut compatibility between them=2E > >Yep, that's right=2E The only reasons to copy changes from piix3 >are (a) because they're worth having in themselves and (b) >because having the two devices be the same is maybe less >confusing=2E (b)'s a pretty weak reason, and (a) depends on >the individual change=2E In this case I think making the equivalent >of e735b55a8c11 is worthwhile because it saves us having an >extra array field and migrating it, and the change is pretty >small=2E For ab431c283e7055bcd you could argue either way -- it's >clearly a better way to structure the irq handling, but it's only >an optimisation, not a bug fix=2E e735b55a8c11 seems like a very elegant way for fixing migration of the IRQ= levels=2E I'll have a look=2E Regards, Bernhard > >-- PMM