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[188.155.176.92]) by smtp.gmail.com with ESMTPSA id y24-20020a1709060a9800b006fe8a4ec62fsm4987024ejf.4.2022.06.27.05.39.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Jun 2022 05:39:43 -0700 (PDT) Message-ID: <47e1fcb4-237b-b880-b1b2-3910cc19e727@linaro.org> Date: Mon, 27 Jun 2022 14:39:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v4 4/4] arm64: dts: qcom: sdm845: Add CPU BWMON Content-Language: en-US To: Bjorn Andersson Cc: Rajendra Nayak , Andy Gross , Georgi Djakov , Rob Herring , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thara Gopinath References: <20220601101140.170504-1-krzysztof.kozlowski@linaro.org> <20220601101140.170504-5-krzysztof.kozlowski@linaro.org> <64eb52ee-b3ac-3d94-cfce-ceb1c88dddb6@linaro.org> <042cb765-113b-9335-edae-595addf50dd0@quicinc.com> <23320e3c-40c3-12bb-0a1c-7e659a1961f2@linaro.org> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 26/06/2022 05:28, Bjorn Andersson wrote: > On Thu 23 Jun 07:58 CDT 2022, Krzysztof Kozlowski wrote: > >> On 23/06/2022 08:48, Rajendra Nayak wrote: >>>>>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>>>> index 83e8b63f0910..adffb9c70566 100644 >>>>>> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>>>> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>>>> @@ -2026,6 +2026,60 @@ llcc: system-cache-controller@1100000 { >>>>>> interrupts = ; >>>>>> }; >>>>>> >>>>>> + pmu@1436400 { >>>>>> + compatible = "qcom,sdm845-cpu-bwmon"; >>>>>> + reg = <0 0x01436400 0 0x600>; >>>>>> + >>>>>> + interrupts = ; >>>>>> + >>>>>> + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, >>>>>> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; >>>>>> + interconnect-names = "ddr", "l3c"; >>>>> >>>>> Is this the pmu/bwmon instance between the cpu and caches or the one between the caches and DDR? >>>> >>>> To my understanding this is the one between CPU and caches. >>> >>> Ok, but then because the OPP table lists the DDR bw first and Cache bw second, isn't the driver >>> ending up comparing the bw values thrown by the pmu against the DDR bw instead of the Cache BW? >> >> I double checked now and you're right. >> >>> Atleast with my testing on sc7280 I found this to mess things up and I always was ending up at >>> higher OPPs even while the system was completely idle. Comparing the values against the Cache bw >>> fixed it.(sc7280 also has a bwmon4 instance between the cpu and caches and a bwmon5 between the cache >>> and DDR) >> >> In my case it exposes different issue - under performance. Somehow the >> bwmon does not report bandwidth high enough to vote for high bandwidth. >> >> After removing the DDR interconnect and bandwidth OPP values I have for: >> sysbench --threads=8 --time=60 --memory-total-size=20T --test=memory >> --memory-block-size=4M run >> >> 1. Vanilla: 29768 MB/s >> 2. Vanilla without CPU votes: 8728 MB/s >> 3. Previous bwmon (voting too high): 32007 MB/s >> 4. Fixed bwmon 24911 MB/s >> Bwmon does not vote for maximum L3 speed: >> bwmon report 9408 MB/s (thresholds set: <9216000 15052801> >> ) >> osm l3 aggregate 14355 MBps -> 897 MHz, level 7, bw 14355 MBps >> >> Maybe that's just problem with missing governor which would vote for >> bandwidth rounding up or anticipating higher needs. >> >>>>> Depending on which one it is, shouldn;t we just be scaling either one and not both the interconnect paths? >>>> >>>> The interconnects are the same as ones used for CPU nodes, therefore if >>>> we want to scale both when scaling CPU, then we also want to scale both >>>> when seeing traffic between CPU and cache. >>> >>> Well, they were both associated with the CPU node because with no other input to decide on _when_ >>> to scale the caches and DDR, we just put a mapping table which simply mapped a CPU freq to a L3 _and_ >>> DDR freq. So with just one input (CPU freq) we decided on what should be both the L3 freq and DDR freq. >>> >>> Now with 2 pmu's, we have 2 inputs, so we can individually scale the L3 based on the cache PMU >>> counters and DDR based on the DDR PMU counters, no? >>> >>> Since you said you have plans to add the other pmu support as well (bwmon5 between the cache and DDR) >>> how else would you have the OPP table associated with that pmu instance? Would you again have both the >>> L3 and DDR scale based on the inputs from that bwmon too? >> >> Good point, thanks for sharing. I think you're right. I'll keep only the >> l3c interconnect path. >> > > If I understand correctly, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 > SLAVE_OSM_L3> relates to the L3 cache speed, which sits inside the CPU > subsystem. As such traffic hitting this cache will not show up in either > bwmon instance. > > The path <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3> > affects the DDR frequency. So the traffic measured by the cpu-bwmon > would be the CPU subsystems traffic that missed the L1/L2/L3 caches and > hits the memory bus towards DDR. > > > If this is the case it seems to make sense to keep the L3 scaling in the > opp-tables for the CPU and make bwmon only scale the DDR path. What do > you think? The reported data throughput by this bwmon instance is beyond the DDR OPP table bandwidth, e.g.: 16-22 GB/s, so it seems it measures still within cache controller, not the memory bus. Best regards, Krzysztof From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E54FCC43334 for ; Mon, 27 Jun 2022 12:41:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=mOKUE3rIeRq7324rtdNaxOsCvDWDk/0xET0/OTF2j+Y=; b=NlXeR0MeVn3yAi pL4tdGcMOWs49nymDGllXzab5JKuXdRZ+4a2lKBgZYolGEBYEe+K9m3OhjRpErqPussMSRwzOeILf 76qZtx+i8TBdSV0TRtn6T8tDd5Gfc5cGIzzzJz1R4qcAXi6mtnvOHsXcrT+zLRnmwnlSqiL9n8XPX kB7LGFm/C8L86ibmvEihPSWyEFqJtoG/4a5+WGFKwhlxxNRBUC3QDPdVvZ9VbWeMhnbjXbuj29DGK NTqCebX53QHITMF+GHwVJqZZ8YIhuqqzyrK5q+uPRQNow3ZJ44y5X0jYyZjTXoXGmQ65FrxnB31dO UwbhIhCEcE329eGrFgKg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o5o2P-000wXs-IR; Mon, 27 Jun 2022 12:40:22 +0000 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o5o1p-000wGr-ON for linux-arm-kernel@lists.infradead.org; Mon, 27 Jun 2022 12:39:47 +0000 Received: by mail-ej1-x62f.google.com with SMTP id q6so18798632eji.13 for ; Mon, 27 Jun 2022 05:39:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=xmyY2TbGiQjUSbUXsv4bmxdmwb/1rWQHVm1rbAHDFtc=; b=WgCMA45z7oXe99Kbi//PSjt233asrGWvSstR+do7+vDXHYbH9jE8DEWkHR2IR7+3VD y1khmDOx6JyNs76tx30VI984zWqUWXybyXShrbzXKUuEp+MZ2KxcvqQVWnDuYrHqv3Au b4lmIJGkdBdYipjIbS6xyBdXgpUzF9/nK8+4saPjtHrrE7zE1jIIKGHCBsJSHGJ70A2V xMX59jFokLVHnb1zSWxhsf65P2+Vf/Ti+LC6zed1OWjgm2PcRrPQuXB9xwSZRJkhT1oW RpDGu63bCEv1Ko8kMZXzNwyVmt3lOUZ3amOTKIUfq4OSSS2iCdXWG9OVt6UncEMPE+fM YfAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=xmyY2TbGiQjUSbUXsv4bmxdmwb/1rWQHVm1rbAHDFtc=; b=ffiMGUnD2ZH5tbqF7hSypUYKPyKanFyIF1BhRnmKZpKzxmz0idMcKzJhxdGM3GXXqM ScK+tH398boNTWOGJMFJwISnnIwhEx0lQ0OJg0Q6XVQMS0dP9OGKdRwaBrosk+5YIYYX 2tB1nGClpiw6CrL9/SLj5lBThMvC7LuN3oWBIu78oT4d2QrXJYWzOVWpm3Hjef0JGwel bZJB3hyNyDtTi8ipEzM/nNNzFzhg32hSudWHLjdiNHj/oPRbFFtclwrZCRt0CzmuXPO3 z2JEa+eYTzWfoC6+oZO7Mmvp2kkxIVLyrbNaQ99EqIDXs6viY7suu+1wf517Y4iWbjqF zPsg== X-Gm-Message-State: AJIora8HlFIvNUYcJjY38EgSl01jwJtTHslpj3NcSCAwVX36fEUSckUq AKVLTzC8Q/hSlvDjnl7rNQwf0w== X-Google-Smtp-Source: AGRyM1tVT90h6/b8BA4X8bgZvAoehqjtWKBkZx2qsNMgdSgNwycwFWB/bXiCC/6GqZ24Lp0OXWDccA== X-Received: by 2002:a17:906:1c5:b0:715:7c69:870e with SMTP id 5-20020a17090601c500b007157c69870emr12665051ejj.348.1656333583617; Mon, 27 Jun 2022 05:39:43 -0700 (PDT) Received: from [192.168.0.249] (xdsl-188-155-176-92.adslplus.ch. [188.155.176.92]) by smtp.gmail.com with ESMTPSA id y24-20020a1709060a9800b006fe8a4ec62fsm4987024ejf.4.2022.06.27.05.39.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 27 Jun 2022 05:39:43 -0700 (PDT) Message-ID: <47e1fcb4-237b-b880-b1b2-3910cc19e727@linaro.org> Date: Mon, 27 Jun 2022 14:39:41 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.10.0 Subject: Re: [PATCH v4 4/4] arm64: dts: qcom: sdm845: Add CPU BWMON Content-Language: en-US To: Bjorn Andersson Cc: Rajendra Nayak , Andy Gross , Georgi Djakov , Rob Herring , Catalin Marinas , Will Deacon , linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thara Gopinath References: <20220601101140.170504-1-krzysztof.kozlowski@linaro.org> <20220601101140.170504-5-krzysztof.kozlowski@linaro.org> <64eb52ee-b3ac-3d94-cfce-ceb1c88dddb6@linaro.org> <042cb765-113b-9335-edae-595addf50dd0@quicinc.com> <23320e3c-40c3-12bb-0a1c-7e659a1961f2@linaro.org> From: Krzysztof Kozlowski In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220627_053945_914289_E1B5A750 X-CRM114-Status: GOOD ( 27.94 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 26/06/2022 05:28, Bjorn Andersson wrote: > On Thu 23 Jun 07:58 CDT 2022, Krzysztof Kozlowski wrote: > >> On 23/06/2022 08:48, Rajendra Nayak wrote: >>>>>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>>>> index 83e8b63f0910..adffb9c70566 100644 >>>>>> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>>>> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi >>>>>> @@ -2026,6 +2026,60 @@ llcc: system-cache-controller@1100000 { >>>>>> interrupts = ; >>>>>> }; >>>>>> >>>>>> + pmu@1436400 { >>>>>> + compatible = "qcom,sdm845-cpu-bwmon"; >>>>>> + reg = <0 0x01436400 0 0x600>; >>>>>> + >>>>>> + interrupts = ; >>>>>> + >>>>>> + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3>, >>>>>> + <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; >>>>>> + interconnect-names = "ddr", "l3c"; >>>>> >>>>> Is this the pmu/bwmon instance between the cpu and caches or the one between the caches and DDR? >>>> >>>> To my understanding this is the one between CPU and caches. >>> >>> Ok, but then because the OPP table lists the DDR bw first and Cache bw second, isn't the driver >>> ending up comparing the bw values thrown by the pmu against the DDR bw instead of the Cache BW? >> >> I double checked now and you're right. >> >>> Atleast with my testing on sc7280 I found this to mess things up and I always was ending up at >>> higher OPPs even while the system was completely idle. Comparing the values against the Cache bw >>> fixed it.(sc7280 also has a bwmon4 instance between the cpu and caches and a bwmon5 between the cache >>> and DDR) >> >> In my case it exposes different issue - under performance. Somehow the >> bwmon does not report bandwidth high enough to vote for high bandwidth. >> >> After removing the DDR interconnect and bandwidth OPP values I have for: >> sysbench --threads=8 --time=60 --memory-total-size=20T --test=memory >> --memory-block-size=4M run >> >> 1. Vanilla: 29768 MB/s >> 2. Vanilla without CPU votes: 8728 MB/s >> 3. Previous bwmon (voting too high): 32007 MB/s >> 4. Fixed bwmon 24911 MB/s >> Bwmon does not vote for maximum L3 speed: >> bwmon report 9408 MB/s (thresholds set: <9216000 15052801> >> ) >> osm l3 aggregate 14355 MBps -> 897 MHz, level 7, bw 14355 MBps >> >> Maybe that's just problem with missing governor which would vote for >> bandwidth rounding up or anticipating higher needs. >> >>>>> Depending on which one it is, shouldn;t we just be scaling either one and not both the interconnect paths? >>>> >>>> The interconnects are the same as ones used for CPU nodes, therefore if >>>> we want to scale both when scaling CPU, then we also want to scale both >>>> when seeing traffic between CPU and cache. >>> >>> Well, they were both associated with the CPU node because with no other input to decide on _when_ >>> to scale the caches and DDR, we just put a mapping table which simply mapped a CPU freq to a L3 _and_ >>> DDR freq. So with just one input (CPU freq) we decided on what should be both the L3 freq and DDR freq. >>> >>> Now with 2 pmu's, we have 2 inputs, so we can individually scale the L3 based on the cache PMU >>> counters and DDR based on the DDR PMU counters, no? >>> >>> Since you said you have plans to add the other pmu support as well (bwmon5 between the cache and DDR) >>> how else would you have the OPP table associated with that pmu instance? Would you again have both the >>> L3 and DDR scale based on the inputs from that bwmon too? >> >> Good point, thanks for sharing. I think you're right. I'll keep only the >> l3c interconnect path. >> > > If I understand correctly, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 > SLAVE_OSM_L3> relates to the L3 cache speed, which sits inside the CPU > subsystem. As such traffic hitting this cache will not show up in either > bwmon instance. > > The path <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_EBI1 3> > affects the DDR frequency. So the traffic measured by the cpu-bwmon > would be the CPU subsystems traffic that missed the L1/L2/L3 caches and > hits the memory bus towards DDR. > > > If this is the case it seems to make sense to keep the L3 scaling in the > opp-tables for the CPU and make bwmon only scale the DDR path. What do > you think? The reported data throughput by this bwmon instance is beyond the DDR OPP table bandwidth, e.g.: 16-22 GB/s, so it seems it measures still within cache controller, not the memory bus. Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel