From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933382AbdDEKLe convert rfc822-to-8bit (ORCPT ); Wed, 5 Apr 2017 06:11:34 -0400 Received: from gloria.sntech.de ([95.129.55.99]:38758 "EHLO gloria.sntech.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932586AbdDEKLb (ORCPT ); Wed, 5 Apr 2017 06:11:31 -0400 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: Elaine Zhang Cc: cl@rock-chips.com, robh+dt@kernel.org, mark.rutland@arm.com, zhengxing@rock-chips.com, andy.yan@rock-chips.com, jay.xu@rock-chips.com, matthias.bgg@gmail.com, paweljarosz3691@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, wsa@the-dreams.de, linux-i2c@vger.kernel.org, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, wxt@rock-chips.com, david.wu@rock-chips.com, linux-iio@vger.kernel.org, shawn.lin@rock-chips.com, akpm@linux-foundation.org, dianders@chromium.org, yamada.masahiro@socionext.com, catalin.marinas@arm.com, will.deacon@arm.com, afaerber@suse.de, shawnguo@kernel.org, khilman@baylibre.com, arnd@arndb.de, fabio.estevam@nxp.com, kever.yang@rock-chips.com, tony.xie@rock-chips.com, huangtao@rock-chips.com, yhx@rock-chips.com, rocky.hao@rock-chips.com Subject: Re: [PATCH v4 4/6] arm64: dts: rockchip: add core dtsi file for RK3328 SoCs Date: Wed, 05 Apr 2017 12:11:11 +0200 Message-ID: <4811905.ImQG7774i7@diego> User-Agent: KMail/5.2.3 (Linux/4.8.0-2-amd64; KDE/5.27.0; x86_64; ; ) In-Reply-To: <58E4516D.4000805@rock-chips.com> References: <1490607650-18650-1-git-send-email-cl@rock-chips.com> <6636047.jL6XHNkknt@phil> <58E4516D.4000805@rock-chips.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Elaine, Am Mittwoch, 5. April 2017, 10:07:41 CEST schrieb Elaine Zhang: > On 04/05/2017 12:04 AM, Heiko Stuebner wrote: > > Am Montag, 27. März 2017, 17:40:48 CEST schrieb cl@rock-chips.com: > >> From: Liang Chen > >> > >> This patch adds core dtsi file for Rockchip RK3328 SoCs. > >> > >> Signed-off-by: Liang Chen > > > > applied for 4.12, with the following list of changes: > > > > - reorder some properties to bring them in alphabetical order > > - dropped the status-disabled from the power-controller > > > > power-domain control is a quite essential part of the system, so if > > boards really want to disable them, they should do it in their board > > file > > Having power-domains on all the time, is also our default in all other > > devicetrees. > > > > - removed #dma-cells from spi0 -> this is not a dma controller > > - reword the cru assigned-clocks comment a bit > > - fixed sdmmc1_bus4 pins, as indicated by Shawn and after looking up the > > > > correct pins in the manual > > > > And a final question, are you sure about SCLK_PDM becoming a child of the > > APLL in your cru assigned-clocks, as the APLL will vary later on with > > cpufreq active? > > the NPLL will vary later on with cpufreq active. > > The NPLL is better than APLL, so NPLL is for clk_core,and apll is for pdm. > > please see the TRM in CRU: > 1.4 Function Description > /........./ > To maximize the flexibility, some of clocks can select divider source > from 5 PLLs. (Note: It’s > recommended to use NEW PLL instead of ARM PLL as arm clock source, > because NEW PLL is > near to ARM. And it’s jitter is better than ARM PLL). Thanks for the clarification - this way it definitly makes sense. Thanks Heiko From mboxrd@z Thu Jan 1 00:00:00 1970 From: Heiko =?ISO-8859-1?Q?St=FCbner?= Subject: Re: [PATCH v4 4/6] arm64: dts: rockchip: add core dtsi file for RK3328 SoCs Date: Wed, 05 Apr 2017 12:11:11 +0200 Message-ID: <4811905.ImQG7774i7@diego> References: <1490607650-18650-1-git-send-email-cl@rock-chips.com> <6636047.jL6XHNkknt@phil> <58E4516D.4000805@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <58E4516D.4000805@rock-chips.com> Sender: linux-kernel-owner@vger.kernel.org To: Elaine Zhang Cc: cl@rock-chips.com, robh+dt@kernel.org, mark.rutland@arm.com, zhengxing@rock-chips.com, andy.yan@rock-chips.com, jay.xu@rock-chips.com, matthias.bgg@gmail.com, paweljarosz3691@gmail.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, wsa@the-dreams.de, linux-i2c@vger.kernel.org, jic23@kernel.org, knaack.h@gmx.de, lars@metafoo.de, pmeerw@pmeerw.net, wxt@rock-chips.com, david.wu@rock-chips.com, linux-iio@vger.kernel.org, shawn.lin@rock-chips.com, akpm@linux-foundation.org, dianders@chromium.org, yamada.masahiro@socionext.com, catalin.marinas@arm.com, will.deacon@arm.com, afaerber@suse.de, shawnguo@kernel.org, khilman@baylibre.com, arnd@arndb.de, fabio.estevam@nxp.com, kever.yang@rock-chips.com List-Id: devicetree@vger.kernel.org Hi Elaine, Am Mittwoch, 5. April 2017, 10:07:41 CEST schrieb Elaine Zhang: > On 04/05/2017 12:04 AM, Heiko Stuebner wrote: > > Am Montag, 27. März 2017, 17:40:48 CEST schrieb cl@rock-chips.com: > >> From: Liang Chen > >> > >> This patch adds core dtsi file for Rockchip RK3328 SoCs. > >> > >> Signed-off-by: Liang Chen > > > > applied for 4.12, with the following list of changes: > > > > - reorder some properties to bring them in alphabetical order > > - dropped the status-disabled from the power-controller > > > > power-domain control is a quite essential part of the system, so if > > boards really want to disable them, they should do it in their board > > file > > Having power-domains on all the time, is also our default in all other > > devicetrees. > > > > - removed #dma-cells from spi0 -> this is not a dma controller > > - reword the cru assigned-clocks comment a bit > > - fixed sdmmc1_bus4 pins, as indicated by Shawn and after looking up the > > > > correct pins in the manual > > > > And a final question, are you sure about SCLK_PDM becoming a child of the > > APLL in your cru assigned-clocks, as the APLL will vary later on with > > cpufreq active? > > the NPLL will vary later on with cpufreq active. > > The NPLL is better than APLL, so NPLL is for clk_core,and apll is for pdm. > > please see the TRM in CRU: > 1.4 Function Description > /........./ > To maximize the flexibility, some of clocks can select divider source > from 5 PLLs. (Note: It’s > recommended to use NEW PLL instead of ARM PLL as arm clock source, > because NEW PLL is > near to ARM. And it’s jitter is better than ARM PLL). Thanks for the clarification - this way it definitly makes sense. Thanks Heiko From mboxrd@z Thu Jan 1 00:00:00 1970 From: heiko@sntech.de (Heiko =?ISO-8859-1?Q?St=FCbner?=) Date: Wed, 05 Apr 2017 12:11:11 +0200 Subject: [PATCH v4 4/6] arm64: dts: rockchip: add core dtsi file for RK3328 SoCs In-Reply-To: <58E4516D.4000805@rock-chips.com> References: <1490607650-18650-1-git-send-email-cl@rock-chips.com> <6636047.jL6XHNkknt@phil> <58E4516D.4000805@rock-chips.com> Message-ID: <4811905.ImQG7774i7@diego> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Elaine, Am Mittwoch, 5. April 2017, 10:07:41 CEST schrieb Elaine Zhang: > On 04/05/2017 12:04 AM, Heiko Stuebner wrote: > > Am Montag, 27. M?rz 2017, 17:40:48 CEST schrieb cl at rock-chips.com: > >> From: Liang Chen > >> > >> This patch adds core dtsi file for Rockchip RK3328 SoCs. > >> > >> Signed-off-by: Liang Chen > > > > applied for 4.12, with the following list of changes: > > > > - reorder some properties to bring them in alphabetical order > > - dropped the status-disabled from the power-controller > > > > power-domain control is a quite essential part of the system, so if > > boards really want to disable them, they should do it in their board > > file > > Having power-domains on all the time, is also our default in all other > > devicetrees. > > > > - removed #dma-cells from spi0 -> this is not a dma controller > > - reword the cru assigned-clocks comment a bit > > - fixed sdmmc1_bus4 pins, as indicated by Shawn and after looking up the > > > > correct pins in the manual > > > > And a final question, are you sure about SCLK_PDM becoming a child of the > > APLL in your cru assigned-clocks, as the APLL will vary later on with > > cpufreq active? > > the NPLL will vary later on with cpufreq active. > > The NPLL is better than APLL, so NPLL is for clk_core,and apll is for pdm. > > please see the TRM in CRU: > 1.4 Function Description > /........./ > To maximize the flexibility, some of clocks can select divider source > from 5 PLLs. (Note: It?s > recommended to use NEW PLL instead of ARM PLL as arm clock source, > because NEW PLL is > near to ARM. And it?s jitter is better than ARM PLL). Thanks for the clarification - this way it definitly makes sense. Thanks Heiko