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[174.21.70.228]) by smtp.gmail.com with ESMTPSA id k1sm4560865pfa.30.2021.06.05.14.10.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 05 Jun 2021 14:10:05 -0700 (PDT) Subject: Re: [PATCH v16 80/99] target/arm: tcg-sve: import narrow_vq and change_el functions To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org References: <20210604155312.15902-1-alex.bennee@linaro.org> <20210604155312.15902-81-alex.bennee@linaro.org> From: Richard Henderson Message-ID: <484b0d7d-69e2-9a83-d431-4887615723a1@linaro.org> Date: Sat, 5 Jun 2021 14:10:02 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <20210604155312.15902-81-alex.bennee@linaro.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.59, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Claudio Fontana , Laurent Vivier Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/4/21 8:52 AM, Alex Bennée wrote: > From: Claudio Fontana > > aarch64_sve_narrow_vq and aarch64_sve_change_el are SVE-related > functions only used for TCG, so we can put them in the > tcg-sve.c module. > > Signed-off-by: Claudio Fontana > Reviewed-by: Richard Henderson > Signed-off-by: Alex Bennée > --- > target/arm/cpu.h | 7 --- > target/arm/tcg/tcg-sve.h | 5 ++ > linux-user/syscall.c | 4 ++ > target/arm/cpu-exceptions-aa64.c | 1 + > target/arm/tcg/cpregs.c | 4 ++ > target/arm/tcg/helper-a64.c | 1 + > target/arm/tcg/helper.c | 87 -------------------------------- > target/arm/tcg/tcg-sve.c | 86 +++++++++++++++++++++++++++++++ > 8 files changed, 101 insertions(+), 94 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 8614948543..3edf8bb4ec 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1056,9 +1056,6 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, > #ifdef TARGET_AARCH64 > int aarch64_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); > int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); > -void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); > -void aarch64_sve_change_el(CPUARMState *env, int old_el, > - int new_el, bool el0_a64); > > static inline bool is_a64(CPUARMState *env) > { > @@ -1090,10 +1087,6 @@ static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr) > } > > #else > -static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { } > -static inline void aarch64_sve_change_el(CPUARMState *env, int o, > - int n, bool a) > -{ } > > #define is_a64(env) ((void)env, false) > > diff --git a/target/arm/tcg/tcg-sve.h b/target/arm/tcg/tcg-sve.h > index 4bed809b9a..5855bb4289 100644 > --- a/target/arm/tcg/tcg-sve.h > +++ b/target/arm/tcg/tcg-sve.h > @@ -21,4 +21,9 @@ uint32_t tcg_sve_disable_lens(unsigned long *sve_vq_map, > bool tcg_sve_validate_lens(unsigned long *sve_vq_map, uint32_t max_vq, > Error **errp); > > +void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); > + > +void aarch64_sve_change_el(CPUARMState *env, int old_el, > + int new_el, bool el0_a64); > + > #endif /* TCG_SVE_H */ > diff --git a/linux-user/syscall.c b/linux-user/syscall.c > index c9f812091c..db4b7b1e46 100644 > --- a/linux-user/syscall.c > +++ b/linux-user/syscall.c > @@ -134,6 +134,10 @@ > #include "fd-trans.h" > #include "tcg/tcg.h" > > +#ifdef TARGET_AARCH64 > +#include "tcg/tcg-sve.h" > +#endif /* TARGET_AARCH64 */ > + > #ifndef CLONE_IO > #define CLONE_IO 0x80000000 /* Clone io context */ > #endif > diff --git a/target/arm/cpu-exceptions-aa64.c b/target/arm/cpu-exceptions-aa64.c > index 7daaba0426..adaf3bab17 100644 > --- a/target/arm/cpu-exceptions-aa64.c > +++ b/target/arm/cpu-exceptions-aa64.c > @@ -21,6 +21,7 @@ > #include "qemu/osdep.h" > #include "qemu/log.h" > #include "cpu.h" > +#include "tcg/tcg-sve.h" > #include "internals.h" > #include "sysemu/tcg.h" Ok, sure. > > diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c > index 56d56f7f81..9d3c9ae841 100644 > --- a/target/arm/tcg/cpregs.c > +++ b/target/arm/tcg/cpregs.c > @@ -16,6 +16,10 @@ > #include "cpu-mmu.h" > #include "cpregs.h" > > +#ifdef TARGET_AARCH64 > +#include "tcg/tcg-sve.h" > +#endif /* TARGET_AARCH64 */ Don't like the ifdef here. If in the previous patch we had moved zcr to cpregs-a64.c, it certainly wouldn't be required. > diff --git a/target/arm/tcg/tcg-sve.c b/target/arm/tcg/tcg-sve.c > index 99cfde1f41..908d2c2f2c 100644 > --- a/target/arm/tcg/tcg-sve.c > +++ b/target/arm/tcg/tcg-sve.c > @@ -24,6 +24,7 @@ > #include "sysemu/tcg.h" > #include "cpu-sve.h" > #include "tcg-sve.h" > +#include "cpu-exceptions-aa64.h" Unnecessary. r~