From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 360DEC3A5A4 for ; Sun, 1 Sep 2019 15:46:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 125E921897 for ; Sun, 1 Sep 2019 15:46:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728896AbfIAPqo (ORCPT ); Sun, 1 Sep 2019 11:46:44 -0400 Received: from pio-pvt-msa1.bahnhof.se ([79.136.2.40]:56588 "EHLO pio-pvt-msa1.bahnhof.se" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728621AbfIAPqo (ORCPT ); Sun, 1 Sep 2019 11:46:44 -0400 Received: from localhost (localhost [127.0.0.1]) by pio-pvt-msa1.bahnhof.se (Postfix) with ESMTP id A180240F37 for ; Sun, 1 Sep 2019 17:46:42 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at bahnhof.se Received: from pio-pvt-msa1.bahnhof.se ([127.0.0.1]) by localhost (pio-pvt-msa1.bahnhof.se [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KKHMlAwQWNv0 for ; Sun, 1 Sep 2019 17:46:41 +0200 (CEST) Received: from localhost (h-41-252.A163.priv.bahnhof.se [46.59.41.252]) (Authenticated sender: mb547485) by pio-pvt-msa1.bahnhof.se (Postfix) with ESMTPA id A0F8240C35 for ; Sun, 1 Sep 2019 17:46:41 +0200 (CEST) Date: Sun, 1 Sep 2019 17:46:41 +0200 From: Fredrik Noring To: linux-mips@vger.kernel.org Subject: [PATCH 023/120] MIPS: R5900: Add MFSA and MTSA instructions for the special SA register Message-ID: <484e5c712f0ff87fcd525b3fc18f1483389844fa.1567326213.git.noring@nocrew.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org The shift amount (SA) register is a 64-bit special register storing the funnel shift amount. The SA is encoded an implementation-defined manner. It is therefore not meaningful for software to operate on this value. Use the MTSAB and MTSAH instructions to set a new funnel shift amount. The SA is used by the QFSRV (quadword funnel shift right variable) 256-bit multimedia instruction. MFSA copies the SA register to a 64-bit GPR[1]. The sole purpose of this instruction is to permit the shift amount to be saved during a context switch. MTSA copies a 64-bit GPR rs to the SA register[2]. Note that rs must contain a value that was originally generated by MFSA. If some other user-generated value is in rs, the shifting action performed by the funnel shifter is not defined; that is, MTSA cannot be used to by a program to set a new funnel shift amount. The sole purpose of this instruction is to permit the shift amount to be restored during a context switch. Restrictions: The three instructions statically preceding a MTSA instruction must not read or write the SA register; that is, they cannot be either of the instructions MFSA, QFSRV, or MTSAx. References: [1] "TX System RISC TX79 Core Architecture" manual, revision 2.0, Toshiba Corporation, p. B-17, https://wiki.qemu.org/File:C790.pdf [2] Ibid. p. B-20. Signed-off-by: Fredrik Noring --- arch/mips/include/asm/mipsregs.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index a3b3ee011539..d8c1ffac2824 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -2594,6 +2594,28 @@ do { \ #else +#ifdef CONFIG_CPU_R5900 +#define mfsa() \ +({ \ + unsigned long __treg; /* FIXME: __u64? */ \ + \ + __asm__ __volatile__( \ + " mfsa %0\n" \ + : "=r" (__treg)); \ + __treg; \ +}) + +#define mtsa(x) \ +do { \ + unsigned long __treg = (x);/* FIXME: __u64? */ \ + \ + __asm__ __volatile__( \ + " mtsa %0\n" \ + : \ + : "r" (__treg)); \ +} while (0) +#endif + #define rddsp(mask) \ ({ \ unsigned int __res; \ -- 2.21.0