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Received: from DM4PR12MB5040.namprd12.prod.outlook.com (2603:10b6:5:38b::19) by BL1PR12MB5380.namprd12.prod.outlook.com (2603:10b6:208:314::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4975.11; Tue, 8 Feb 2022 14:31:56 +0000 Received: from DM4PR12MB5040.namprd12.prod.outlook.com ([fe80::84cf:cad7:192:8089]) by DM4PR12MB5040.namprd12.prod.outlook.com ([fe80::84cf:cad7:192:8089%8]) with mapi id 15.20.4951.018; Tue, 8 Feb 2022 14:31:56 +0000 Message-ID: <48646543-ac47-bfc1-ee09-54c22fd5ac6c@amd.com> Date: Tue, 8 Feb 2022 15:31:49 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH 1/2] drm/amdgpu: add debugfs for reset registers list Content-Language: en-US From: "Sharma, Shashank" To: "Somalapuram, Amaranath" , =?UTF-8?Q?Christian_K=c3=b6nig?= , Somalapuram Amaranath , amd-gfx@lists.freedesktop.org References: <20220208081647.3025-1-Amaranath.Somalapuram@amd.com> <385688f4-2165-ba58-8928-5774a44044e7@amd.com> <52c555ab-ec80-bcfc-5811-270b3b23c5c8@amd.com> In-Reply-To: Content-Type: text/plain; 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I missed this comment in the last patch, and this makes me a bit confused. During the design phase, did we agree to have this whole list loaded from user ? which means that if user doesn't define the list at init, we will not send the trace_event(). Or was it kernel has a list, and user can modify if he wants to, and we will dump the values as per the register list. @Christian ? Regards Shashank On 2/8/2022 3:18 PM, Sharma, Shashank wrote: > > > On 2/8/2022 2:39 PM, Somalapuram, Amaranath wrote: >> >> >> On 2/8/2022 4:43 PM, Sharma, Shashank wrote: >>> I thought we spoke and agreed about: >>> - Not doing dynamic memory allocation during a reset call, >> as there is a redesign debugfs call will happen during the application >> initialization and not during reset. >>> - Not doing string operations, but just dumping register values by >>> index. >> I think your referring to the second patch which happens during reset >> and no string operation in second patch. > > Pls see my comment in the end. > >>> NACK ! >>> >>> - Shashank >>> >>> Amar, >>> Apart from the long comment,there are a few more bugs in the patch, >>> which I have mentioned here inline. Please check them out. >>> >>> - Shashank >>> >>> On 2/8/2022 9:18 AM, Christian König wrote: >>>> Am 08.02.22 um 09:16 schrieb Somalapuram Amaranath: >>>>> List of register to be populated for dump collection during the GPU >>>>> reset. >>>>> >>>>> Signed-off-by: Somalapuram Amaranath >>>>> --- >>>>>   drivers/gpu/drm/amd/amdgpu/amdgpu.h         |  3 ++ >>>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 60 >>>>> +++++++++++++++++++++ >>>>>   2 files changed, 63 insertions(+) >>>>> >>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>>>> index b85b67a88a3d..78fa46f959c5 100644 >>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h >>>>> @@ -1097,6 +1097,9 @@ struct amdgpu_device { >>>>>       struct amdgpu_reset_control     *reset_cntl; >>>>>       uint32_t ip_versions[HW_ID_MAX][HWIP_MAX_INSTANCE]; >>>>> + >>>>> +    /* reset dump register */ >>>>> +    long            reset_dump_reg_list[128]; >>>> >>>> I don't have time for a full review, but using long here certainly >>>> makes no sense. >>>> >>>> long is either 32bit or 64bit depending on the CPU architecture. >>>> >>>> Regards, >>>> Christian. >>>> >> will change uint32_t. >>>>>   }; >>>>>   static inline struct amdgpu_device *drm_to_adev(struct drm_device >>>>> *ddev) >>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c >>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c >>>>> index 164d6a9e9fbb..dad268e8a81a 100644 >>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c >>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c >>>>> @@ -1609,6 +1609,64 @@ DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL, >>>>>   DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL, >>>>>               amdgpu_debugfs_sclk_set, "%llu\n"); >>>>> +static ssize_t amdgpu_reset_dump_register_list_read(struct file *f, >>>>> +                char __user *buf, size_t size, loff_t *pos) >>>>> +{ >>>>> +    struct amdgpu_device *adev = (struct amdgpu_device >>>>> *)file_inode(f)->i_private; >>>>> +    char *reg_offset; >>>>> +    int i, r, len; >>>>> + >>>>> +    reg_offset = kmalloc(2048, GFP_KERNEL); > > We also want to understand how does the value 2048 came into picture, > probably a macro which calculates the size preprocessing time will work > better. > > #define #define N_REGS_DUMP_GPU_RESET 10 > #define BUFFER_SZ(N_REGS_DUMP_GPU_RESET * (sizeof uint64_t) + 1) > > This first macro can be used later for the loop count for registers as > well. > >>>>> +    memset(reg_offset,  0, 2048); >>>>> +    for (i = 0; adev->reset_dump_reg_list[i] != 0; i++) >>> >>> This loop termination condition is incorrect, why are we running the >>> loop until adev->reset_dump_reg_list[i] != 0 ? >>> >>> What if I have 10 registers to dump, but my 4th register value is 0 ? >>> It will break the loop at 4 and we will not get all values. >>> >> agreed, i try to avoid one more variable in adev > > Not by the cost of logic of course :). > > Now you can run this loop here. > > for (i = 0; i < N_REGS...; i++) { >     register_value_copy_here; > } > >>>>> +        sprintf(reg_offset + strlen(reg_offset), "0x%lx ", >>>>> adev->reset_dump_reg_list[i]); >>>>> + > >>>>> +    sprintf(reg_offset + strlen(reg_offset), "\n"); >>>>> +    len = strlen(reg_offset); >>>>> + >>>>> +    if (*pos >=  len) >>>>> +        return 0; >>>>> + >>>>> +    r = copy_to_user(buf, reg_offset, len); >>>>> +    *pos += len - r; >>>>> +    kfree(reg_offset); >>> >>> Also, why are we doing a dynamic memory allocation for reg_offest ? >>> We can simply use adev->reset_dump_reg_list[i] isnt't it ? >>> >>> simply >>> for (i=0; i>>     copy_to_user(buf, adev->reg_list[i], sizeof(uint64_t)); >>> } >>> >>> Or without even a loop, simply: >>> copy_to_user(buf, &adev->reg_list, num_regs * sizeof(uint64_t)); >>> >>> - Shashank >> >> it will not be in user readable format for debugfs, (if non readable >> is acceptable I will change this) >> > > We are just adding 0x in front of the reg value, so honestly I don't see > a huge improvement in the user readability, but if you still want to do > the dynamic allocation of memory, add the register offset or name as > well, I mean then it should read like: > > 0x1234 = 0xABCD > 0x1238 = 0xFFFF > > - Shashank > >>> + >>>>> >>>>> +    return len - r; >>>>> +} >>>>> + >>>>> +static ssize_t amdgpu_reset_dump_register_list_write(struct file >>>>> *f, const char __user *buf, >>>>> +        size_t size, loff_t *pos) >>>>> +{ >>>>> +    struct amdgpu_device *adev = (struct amdgpu_device >>>>> *)file_inode(f)->i_private; >>>>> +    char *reg_offset, *reg; >>>>> +    int ret, i = 0; >>>>> + >>>>> +    reg_offset = kmalloc(size, GFP_KERNEL); >>>>> +    memset(reg_offset,  0, size); >>>>> +    ret = copy_from_user(reg_offset, buf, size); >>>>> + >>> >>> We are not allowing user to write into the list, so this whole >>> function can just be a NOOP. >>> >>> - Shashank >> User only update the list of reg offsets on init, there is no >> predefined reg offset from kernel code. >>> >>>>> +    if (ret) >>>>> +        return -EFAULT; >>>>> + >>>>> +    while ((reg = strsep(®_offset, " ")) != NULL) { >>>>> +        ret  = kstrtol(reg, 16, &adev->reset_dump_reg_list[i]); >>>>> +        if (ret) >>>>> +            return -EINVAL; >>>>> +        i++; >>>>> +    } >>>>> + >>>>> +    kfree(reg_offset); >>>>> + >>>>> +    return size; >>>>> +} >>>>> + >>>>> +static const struct file_operations >>>>> amdgpu_reset_dump_register_list = { >>>>> +    .owner = THIS_MODULE, >>>>> +    .read = amdgpu_reset_dump_register_list_read, >>>>> +    .write = amdgpu_reset_dump_register_list_write, >>>>> +    .llseek = default_llseek >>>>> +}; >>>>> + >>>>>   int amdgpu_debugfs_init(struct amdgpu_device *adev) >>>>>   { >>>>>       struct dentry *root = adev_to_drm(adev)->primary->debugfs_root; >>>>> @@ -1672,6 +1730,8 @@ int amdgpu_debugfs_init(struct amdgpu_device >>>>> *adev) >>>>>                   &amdgpu_debugfs_test_ib_fops); >>>>>       debugfs_create_file("amdgpu_vm_info", 0444, root, adev, >>>>>                   &amdgpu_debugfs_vm_info_fops); >>>>> +    debugfs_create_file("amdgpu_reset_dump_register_list", 0644, >>>>> root, adev, >>>>> +                &amdgpu_reset_dump_register_list); >>>>>       adev->debugfs_vbios_blob.data = adev->bios; >>>>>       adev->debugfs_vbios_blob.size = adev->bios_size; >>>>