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[109.252.154.132]) by smtp.googlemail.com with ESMTPSA id g24-20020a2e9cd8000000b002b590f2d808sm220504ljj.9.2023.06.22.04.32.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Jun 2023 04:32:28 -0700 (PDT) Message-ID: <4925a344-03a4-6afb-881c-edf0b9930a4c@gmail.com> Date: Thu, 22 Jun 2023 14:32:27 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.2 Subject: Re: [PATCH v4 65/68] clk: tegra: super: Switch to determine_rate Content-Language: en-US To: Thierry Reding , Stephen Boyd Cc: Maxime Ripard , Michael Turquette , linux-clk@vger.kernel.org, Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , linux-tegra@vger.kernel.org References: <20221018-clk-range-checks-fixes-v4-0-971d5077e7d2@cerno.tech> <20221018-clk-range-checks-fixes-v4-65-971d5077e7d2@cerno.tech> <700c0c62-defd-01c1-3b1d-8a760dfa194f@gmail.com> From: Dmitry Osipenko In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org 21.06.2023 18:35, Thierry Reding пишет: > On Tue, Jun 20, 2023 at 12:09:09PM -0700, Stephen Boyd wrote: >> Quoting Maxime Ripard (2023-06-19 00:26:19) >>> On Mon, Jun 19, 2023 at 02:38:59AM +0300, Dmitry Osipenko wrote: >>>> 05.05.2023 14:26, Maxime Ripard пишет: >>>>> >>>>> diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c >>>>> index 3f3a7a203c5f..7ec47942720c 100644 >>>>> --- a/drivers/clk/tegra/clk-super.c >>>>> +++ b/drivers/clk/tegra/clk-super.c >>>>> @@ -142,15 +142,22 @@ static const struct clk_ops tegra_clk_super_mux_ops = { >>>>> .restore_context = clk_super_mux_restore_context, >>>>> }; >>>>> >>>>> -static long clk_super_round_rate(struct clk_hw *hw, unsigned long rate, >>>>> - unsigned long *parent_rate) >>>>> +static int clk_super_determine_rate(struct clk_hw *hw, >>>>> + struct clk_rate_request *req) >>>>> { >>>>> struct tegra_clk_super_mux *super = to_clk_super_mux(hw); >>>>> struct clk_hw *div_hw = &super->frac_div.hw; >>>>> + unsigned long rate; >>>>> >>>>> __clk_hw_set_clk(div_hw, hw); >>>>> >>>>> - return super->div_ops->round_rate(div_hw, rate, parent_rate); >>>>> + rate = super->div_ops->round_rate(div_hw, req->rate, >>>>> + &req->best_parent_rate); >>>>> + if (rate < 0) >> >> There's the report that this condition is never possible. Maybe the >> previous code was relying on an error value sometimes. Can we add >> determine_rate to the div_ops and simplify this code? I asked on the >> list for that earlier. > > I was able to reproduce this on a Tegra30 Beaver, but the problem is > more straightforward than this. The crash I was seeing during boot was > because cclk_super_determine_rate() was still calling the round_rate() > callback from tegra_clk_super_ops, which this patch removed (and added > determine_rate() instead). > > The following fixes the problem for me. It's basically converting the > round_rate() call to an equivalent determine_rate() call. > > Dmitry, can you verify that this fixes the issue that you were seeing? > > Thierry > > --- >8 --- > diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c > index 68d7bcd5fc8a..8a2bb4ae4fd2 100644 > --- a/drivers/clk/tegra/clk-tegra-super-cclk.c > +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c > @@ -86,9 +86,16 @@ static int cclk_super_determine_rate(struct clk_hw *hw, > if (rate <= pllp_rate) { > if (super->flags & TEGRA20_SUPER_CLK) > rate = pllp_rate; > - else > - rate = tegra_clk_super_ops.round_rate(hw, rate, > - &pllp_rate); > + else { > + struct clk_rate_request parent = { > + .rate = req->rate, > + .best_parent_rate = pllp_rate, > + }; > + > + tegra_clk_super_ops.determine_rate(hw, &parent); > + pllp_rate = parent.best_parent_rate; > + rate = parent.rate; > + } > > req->best_parent_rate = pllp_rate; > req->best_parent_hw = pllp_hw; > --- >8 --- Thank you for the fix, it works! Feel free to add my t-b :)