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From: Marcel Apfelbaum <marcel@redhat.com>
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Date: Fri, 29 Sep 2017 15:37:00 +0300
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Subject: Re: [Qemu-devel] [PATCH] PCI: PCIe access should always be little
 endian
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To: Matt Redfearn <matt.redfearn@imgtec.com>, "Michael S . Tsirkin" <mst@redhat.com>
Cc: qemu-devel@nongnu.org, Yongbok Kim <Yongbok.Kim@imgtec.com>
List-ID: <qemu-devel.nongnu.org>

On 27/09/2017 11:27, Matt Redfearn wrote:
> ping?
>=20

Hi Matt,

I think Michael is in PTO, he'll pick up
the patch as soon he is back.

Thanks,
Marcel

>=20
> On 16/08/17 11:25, Marcel Apfelbaum wrote:
>> On 15/08/2017 17:44, Matt Redfearn wrote:
>>> PCIe busses are always little endian, so set the endianness of the
>>> memory region to little endian rather than native such that operation=
s
>>> work as expected on big endian targets.
>>>
>>> Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
>>
>>
>> Hi Matt,
>> Thanks for the patch.
>>
>>> ---
>>>
>>> =C2=A0 hw/pci/pcie_host.c | 2 +-
>>> =C2=A0 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c
>>> index dcebf57ed45e..553db56778b6 100644
>>> --- a/hw/pci/pcie_host.c
>>> +++ b/hw/pci/pcie_host.c
>>> @@ -81,7 +81,7 @@ static uint64_t pcie_mmcfg_data_read(void *opaque,
>>> =C2=A0 static const MemoryRegionOps pcie_mmcfg_ops =3D {
>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .read =3D pcie_mmcfg_data_read,
>>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 .write =3D pcie_mmcfg_data_write,
>>> -=C2=A0=C2=A0=C2=A0 .endianness =3D DEVICE_NATIVE_ENDIAN,
>>> +=C2=A0=C2=A0=C2=A0 .endianness =3D DEVICE_LITTLE_ENDIAN,
>>> =C2=A0 };
>>> =C2=A0=C2=A0=C2=A0 static void pcie_host_init(Object *obj)
>>>
>>
>>
>> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com>
>>
>> Thanks,
>> Marcel
>=20