From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A86E6C43470 for ; Mon, 17 May 2021 15:09:26 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0DFDB6128A for ; Mon, 17 May 2021 15:09:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0DFDB6128A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:57706 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lies1-0001Ud-3g for qemu-devel@archiver.kernel.org; Mon, 17 May 2021 11:09:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38942) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lieqc-0008HU-7M; Mon, 17 May 2021 11:07:58 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:2466) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lieqV-0007Tx-64; Mon, 17 May 2021 11:07:57 -0400 Received: from dggems705-chm.china.huawei.com (unknown [172.30.72.60]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FkMq262jYzQpKS; Mon, 17 May 2021 23:04:14 +0800 (CST) Received: from dggpemm500023.china.huawei.com (7.185.36.83) by dggems705-chm.china.huawei.com (10.3.19.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.2; Mon, 17 May 2021 23:07:42 +0800 Received: from [10.174.187.128] (10.174.187.128) by dggpemm500023.china.huawei.com (7.185.36.83) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2176.2; Mon, 17 May 2021 23:07:42 +0800 Subject: Re: [RFC PATCH v3 1/4] vl.c: Add -smp, clusters=* command line support for ARM cpu To: Andrew Jones References: <20210516103228.37792-1-wangyanan55@huawei.com> <20210516103228.37792-2-wangyanan55@huawei.com> <20210517090709.u5fjdmarrpeb345y@gator.home> From: "wangyanan (Y)" Message-ID: <49f25604-90cc-a187-2261-b2745fec7102@huawei.com> Date: Mon, 17 May 2021 23:07:41 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:78.0) Gecko/20100101 Thunderbird/78.4.0 MIME-Version: 1.0 In-Reply-To: <20210517090709.u5fjdmarrpeb345y@gator.home> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Content-Language: en-US X-Originating-IP: [10.174.187.128] X-ClientProxiedBy: dggeme702-chm.china.huawei.com (10.1.199.98) To dggpemm500023.china.huawei.com (7.185.36.83) X-CFilter-Loop: Reflected Received-SPF: pass client-ip=45.249.212.191; envelope-from=wangyanan55@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Barry Song , Peter Maydell , "Michael S . Tsirkin" , wanghaibin.wang@huawei.com, zhukeqian1@huawei.com, qemu-devel@nongnu.org, yangyicong@huawei.com, Shannon Zhao , qemu-arm@nongnu.org, prime.zeng@hisilicon.com, Paolo Bonzini , yuzenghui@huawei.com, Igor Mammedov , =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2021/5/17 17:07, Andrew Jones wrote: > On Sun, May 16, 2021 at 06:32:25PM +0800, Yanan Wang wrote: >> In implementations of ARM architecture, at most there could be a >> cpu hierarchy like "sockets/dies/clusters/cores/threads" defined. >> For example, ARM64 server chip Kunpeng 920 totally has 2 sockets, >> 2 NUMA nodes (also means cpu dies) in each socket, 6 clusters in >> each NUMA node, 4 cores in each cluster, and doesn't support SMT. >> Clusters within the same NUMA share a L3 cache and cores within >> the same cluster share a L2 cache. >> >> The cache affinity of ARM cluster has been proved to improve the >> kernel scheduling performance and a patchset has been posted, in >> which a general sched_domain for clusters was added and a cluster >> level was added in the arch-neutral cpu topology struct like below. >> >> struct cpu_topology { >> int thread_id; >> int core_id; >> int cluster_id; >> int package_id; >> int llc_id; >> cpumask_t thread_sibling; >> cpumask_t core_sibling; >> cpumask_t cluster_sibling; >> cpumask_t llc_sibling; >> } >> >> In virtuallization, exposing the cluster level topology to guest >> kernel may also improve the scheduling performance. So let's add >> the -smp, clusters=* command line support for ARM cpu, then users >> will be able to define a four-level cpu hierarchy for machines >> and it will be sockets/clusters/cores/threads. >> >> Because we only support clusters for ARM cpu currently, a new member >> "smp_clusters" is only added to the VirtMachineState structure. >> >> Signed-off-by: Yanan Wang >> --- >> include/hw/arm/virt.h | 1 + >> qemu-options.hx | 26 +++++++++++++++----------- >> softmmu/vl.c | 3 +++ >> 3 files changed, 19 insertions(+), 11 deletions(-) >> >> diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h >> index f546dd2023..74fff9667b 100644 >> --- a/include/hw/arm/virt.h >> +++ b/include/hw/arm/virt.h >> @@ -156,6 +156,7 @@ struct VirtMachineState { >> char *pciehb_nodename; >> const int *irqmap; >> int fdt_size; >> + unsigned smp_clusters; >> uint32_t clock_phandle; >> uint32_t gic_phandle; >> uint32_t msi_phandle; >> diff --git a/qemu-options.hx b/qemu-options.hx >> index bd97086c21..245eb415a6 100644 >> --- a/qemu-options.hx >> +++ b/qemu-options.hx >> @@ -184,25 +184,29 @@ SRST >> ERST >> >> DEF("smp", HAS_ARG, QEMU_OPTION_smp, >> - "-smp [cpus=]n[,maxcpus=cpus][,cores=cores][,threads=threads][,dies=dies][,sockets=sockets]\n" >> + "-smp [cpus=]n[,maxcpus=cpus][,cores=cores][,threads=threads][,clusters=clusters][,dies=dies][,sockets=sockets]\n" >> " set the number of CPUs to 'n' [default=1]\n" >> " maxcpus= maximum number of total cpus, including\n" >> " offline CPUs for hotplug, etc\n" >> - " cores= number of CPU cores on one socket (for PC, it's on one die)\n" >> + " cores= number of CPU cores on one socket\n" >> + " (it's on one die for PC, and on one cluster for ARM)\n" >> " threads= number of threads on one CPU core\n" >> + " clusters= number of CPU clusters on one socket (for ARM only)\n" >> " dies= number of CPU dies on one socket (for PC only)\n" >> " sockets= number of discrete sockets in the system\n", >> QEMU_ARCH_ALL) >> SRST >> -``-smp [cpus=]n[,cores=cores][,threads=threads][,dies=dies][,sockets=sockets][,maxcpus=maxcpus]`` >> - Simulate an SMP system with n CPUs. On the PC target, up to 255 CPUs >> - are supported. On Sparc32 target, Linux limits the number of usable >> - CPUs to 4. For the PC target, the number of cores per die, the >> - number of threads per cores, the number of dies per packages and the >> - total number of sockets can be specified. Missing values will be >> - computed. If any on the three values is given, the total number of >> - CPUs n can be omitted. maxcpus specifies the maximum number of >> - hotpluggable CPUs. >> +``-smp [cpus=]n[,cores=cores][,threads=threads][,clusters=clusters][,dies=dies][,sockets=sockets][,maxcpus=maxcpus]`` >> + Simulate an SMP system with n CPUs. On the PC target, up to 255 >> + CPUs are supported. On the Sparc32 target, Linux limits the number >> + of usable CPUs to 4. For the PC target, the number of threads per >> + core, the number of cores per die, the number of dies per package >> + and the total number of sockets can be specified. For the ARM target, >> + the number of threads per core, the number of cores per cluster, the >> + number of clusters per socket and the total number of sockets can be >> + specified. And missing values will be computed. If any of the five > ^ Why did you add this 'And'? My fault.. I will drop it. >> + values is given, the total number of CPUs n can be omitted. > The last two sentences are not valid for Arm, which requires most of its > parameters to be given. Yes, indeed. I think I should state more *clearly* about these two sentences. Will rearrange the Doc in v4. Thanks, Yanan >> Maxcpus >> + specifies the maximum number of hotpluggable CPUs. >> >> For the ARM target, at least one of cpus or maxcpus must be provided. >> Threads will default to 1 if not provided. Sockets and cores must be >> diff --git a/softmmu/vl.c b/softmmu/vl.c >> index 307944aef3..69a5c73ef7 100644 >> --- a/softmmu/vl.c >> +++ b/softmmu/vl.c >> @@ -719,6 +719,9 @@ static QemuOptsList qemu_smp_opts = { >> }, { >> .name = "dies", >> .type = QEMU_OPT_NUMBER, >> + }, { >> + .name = "clusters", >> + .type = QEMU_OPT_NUMBER, >> }, { >> .name = "cores", >> .type = QEMU_OPT_NUMBER, >> -- >> 2.19.1 >> > Thanks, > drew > > .