From: kevin.morfitt at fearnside-systems.co.uk <kevin.morfitt@fearnside-systems.co.uk>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH-ARM] Add support for Embest SBC2440-II Board 5/7
Date: Thu, 25 Jun 2009 01:36:24 +0100 [thread overview]
Message-ID: <4A42C688.30001@fearnside-systems.co.uk> (raw)
Patches 5 to 7, replace "[PATCH-ARM 2/2] Add support for
the Embest SBC2440-II Board 2/2" submitted on 19/06/2009.
This patch adds support for the s3c2440 cpu, excluding the NAND driver
which is in patch 6/7.
This patch assume the following patches have already been applied:
- [PATCH-ARM] Bug-fix in drivers mtd nand Makefile, sent 18/06/2009
- [PATCH-ARM] CONFIG_SYS_HZ fix for ARM920T S3C24X0 Boards, sent
21/06/2009
The patch was tested by running MAKEALL for all ARM9 targets and
checking that no new warnings or errors were introduced.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk>
---
common/serial.c | 4 +-
cpu/arm920t/s3c24x0/Makefile | 2 +
cpu/arm920t/s3c24x0/arch_pre_lowlevel_init.S | 81 +++++++++++++
cpu/arm920t/s3c24x0/speed.c | 41 +++++--
cpu/arm920t/s3c24x0/timer.c | 20 +---
cpu/arm920t/s3c24x0/usb.c | 17 +--
cpu/arm920t/s3c24x0/usb_ohci.c | 11 +--
cpu/arm920t/start.S | 39 +------
drivers/i2c/s3c24x0_i2c.c | 18 ++--
drivers/mtd/nand/s3c2410_nand.c | 2 +-
drivers/rtc/s3c24x0_rtc.c | 7 +-
drivers/serial/serial_s3c24x0.c | 6 +-
drivers/usb/host/ohci-hcd.c | 3 +-
include/common.h | 5 +-
include/configs/VCMA9.h | 4 +-
include/configs/sbc2410x.h | 4 +-
include/configs/smdk2400.h | 4 +-
include/configs/smdk2410.h | 4 +-
include/configs/trab.h | 4 +-
include/s3c2410.h | 25 ++++
include/s3c2440.h | 162 ++++++++++++++++++++++++++
include/s3c24x0.h | 94 ++++++++++++++-
include/s3c24x0_cpu.h | 29 +++++
23 files changed, 468 insertions(+), 118 deletions(-)
create mode 100644 cpu/arm920t/s3c24x0/arch_pre_lowlevel_init.S
create mode 100644 include/s3c2440.h
create mode 100644 include/s3c24x0_cpu.h
diff --git a/common/serial.c b/common/serial.c
index dd80e7c..6548b8b 100644
--- a/common/serial.c
+++ b/common/serial.c
@@ -58,7 +58,7 @@ struct serial_device *__default_serial_console (void)
#else
return &serial0_device;
#endif
-#elif defined(CONFIG_S3C2410)
+#elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
#if defined(CONFIG_SERIAL1)
return &s3c24xx_serial0_device;
#elif defined(CONFIG_SERIAL2)
@@ -133,7 +133,7 @@ void serial_initialize (void)
#if defined (CONFIG_STUART)
serial_register(&serial_stuart_device);
#endif
-#if defined(CONFIG_S3C2410)
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
serial_register(&s3c24xx_serial0_device);
serial_register(&s3c24xx_serial1_device);
serial_register(&s3c24xx_serial2_device);
diff --git a/cpu/arm920t/s3c24x0/Makefile b/cpu/arm920t/s3c24x0/Makefile
index 5d2be2c..f030515 100644
--- a/cpu/arm920t/s3c24x0/Makefile
+++ b/cpu/arm920t/s3c24x0/Makefile
@@ -25,6 +25,8 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).a
+SOBJS += arch_pre_lowlevel_init.o
+
COBJS += speed.o
COBJS += timer.o
COBJS += usb.o
diff --git a/cpu/arm920t/s3c24x0/arch_pre_lowlevel_init.S b/cpu/arm920t/s3c24x0/arch_pre_lowlevel_init.S
new file mode 100644
index 0000000..13467cf
--- /dev/null
+++ b/cpu/arm920t/s3c24x0/arch_pre_lowlevel_init.S
@@ -0,0 +1,81 @@
+/*
+ * (C) Copyright 2009
+ * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+#ifdef CONFIG_S3C24X0
+
+/* Register addresses. */
+# ifdef CONFIG_S3C2400
+ #define pWTCON 0x15300000
+ #define INTMSK 0x14400008
+ #define CLKDIVN 0x14800014
+#else
+ #define pWTCON 0x53000000
+ #define INTMSK 0x4A000008
+ #define INTSUBMSK 0x4A00001C
+ #define CLKDIVN 0x4C000014
+#endif
+
+/* Configuration values. */
+#ifdef CONFIG_S3C2440
+ #define INTSMASK 0xffff
+ #define CLKDIVVAL 0x5
+#else
+ #define INTSMASK 0x3ff
+ #define CLKDIVVAL 0x3
+#endif
+
+.globl arch_pre_lowlevel_init
+arch_pre_lowlevel_init:
+
+ /* turn off the watchdog */
+ ldr r0, =pWTCON
+ mov r1, #0x0
+ str r1, [r0]
+
+ /*
+ * mask all IRQs by setting all bits in the INTMR - default
+ */
+ mov r1, #0xffffffff
+ ldr r0, =INTMSK
+ str r1, [r0]
+# if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
+ ldr r1, =INTSMASK
+ ldr r0, =INTSUBMSK
+ str r1, [r0]
+# endif
+
+ /* FCLK:HCLK:PCLK = 1:2:4 */
+ /* default FCLK is 120 MHz ! */
+ ldr r0, =CLKDIVN
+ mov r1, #CLKDIVVAL
+ str r1, [r0]
+
+#ifdef CONFIG_S3C2440
+ /* Set asynchronous bus mode */
+ mrc p15, 0, r1, c1, c0, 0 /* read ctrl register */
+ orr r1, r1, #0xc0000000 /* Asynchronous */
+ mcr p15, 0, r1, c1, c0, 0 /* write ctrl register */
+#endif /* CONFIG_S3C2440 */
+
+ mov pc, lr
+
+#endif /* CONFIG_S3C24X0 */
diff --git a/cpu/arm920t/s3c24x0/speed.c b/cpu/arm920t/s3c24x0/speed.c
index bb86335..95c4407 100644
--- a/cpu/arm920t/s3c24x0/speed.c
+++ b/cpu/arm920t/s3c24x0/speed.c
@@ -30,15 +30,10 @@
*/
#include <common.h>
-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+#ifdef CONFIG_S3C24X0
#include <asm/io.h>
-
-#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
-#endif
+#include <s3c24x0_cpu.h>
#define MPLL 0
#define UPLL 1
@@ -69,6 +64,11 @@ static ulong get_PLLCLK(int pllreg)
p = ((r & 0x003F0) >> 4) + 2;
s = r & 0x3;
+#ifdef CONFIG_S3C2440
+ if (pllreg == MPLL)
+ return (2 * CONFIG_SYS_CLK_FREQ * m) / (p << s);
+ else
+#endif
return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
}
@@ -83,7 +83,23 @@ ulong get_HCLK(void)
{
struct s3c24x0_clock_power *clk_power = S3C24X0_GetBase_CLOCK_POWER();
+#ifdef CONFIG_S3C2440
+ switch (clk_power->CLKDIVN & 0x6) {
+ default:
+ case 0:
+ return get_FCLK();
+ case 2:
+ return get_FCLK() / 2;
+ case 4:
+ return (readl(&clk_power->CAMDIVN) & (1 << 9)) ?
+ get_FCLK() / 8 : get_FCLK() / 4;
+ case 6:
+ return (readl(&clk_power->CAMDIVN) & (1 << 8)) ?
+ get_FCLK() / 6 : get_FCLK() / 3;
+ }
+#else
return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
+#endif
}
/* return PCLK frequency */
@@ -97,9 +113,14 @@ ulong get_PCLK(void)
/* return UCLK frequency */
ulong get_UCLK(void)
{
+#ifdef CONFIG_S3C2440
+ struct s3c24x0_clock_power *clk_power = S3C24X0_GetBase_CLOCK_POWER();
+
+ return (readl(&clk_power->CLKDIVN) & (1 << 3)) ?
+ get_PLLCLK(UPLL) / 2 : get_PLLCLK(UPLL);
+#else
return get_PLLCLK(UPLL);
+#endif
}
-#endif /* defined(CONFIG_S3C2400) ||
- defined (CONFIG_S3C2410) ||
- defined (CONFIG_TRAB) */
+#endif /* CONFIG_S3C24X0 */
diff --git a/cpu/arm920t/s3c24x0/timer.c b/cpu/arm920t/s3c24x0/timer.c
index 0aa7947..c7575f5 100644
--- a/cpu/arm920t/s3c24x0/timer.c
+++ b/cpu/arm920t/s3c24x0/timer.c
@@ -30,17 +30,10 @@
*/
#include <common.h>
-#if defined(CONFIG_S3C2400) || \
- defined(CONFIG_S3C2410) || \
- defined(CONFIG_TRAB)
+#ifdef CONFIG_S3C24X0
#include <asm/io.h>
-
-#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
-#endif
+#include <s3c24x0_cpu.h>
static unsigned long get_timer_raw(void);
int timer_load_val = 0;
@@ -192,8 +185,8 @@ ulong get_tbclk(void)
#if defined(CONFIG_SMDK2400) || defined(CONFIG_TRAB)
tbclk = timer_load_val * 100;
-#elif defined(CONFIG_SBC2410X) || \
- defined(CONFIG_SMDK2410) || \
+#elif defined(CONFIG_SBC2410X) || \
+ defined(CONFIG_SMDK2410) || \
defined(CONFIG_VCMA9)
tbclk = CONFIG_SYS_HZ;
#else
@@ -239,7 +232,4 @@ void s3c2410_irq(void)
}
#endif /* USE_IRQ */
-#endif /* defined(CONFIG_S3C2400) ||
- defined (CONFIG_S3C2410) ||
- defined (CONFIG_TRAB) */
-
+#endif /* CONFIG_S3C24X0 */
diff --git a/cpu/arm920t/s3c24x0/usb.c b/cpu/arm920t/s3c24x0/usb.c
index 1f495ff..fa6e084 100644
--- a/cpu/arm920t/s3c24x0/usb.c
+++ b/cpu/arm920t/s3c24x0/usb.c
@@ -23,15 +23,11 @@
#include <common.h>
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-# if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
-
-#if defined(CONFIG_S3C2400)
-# include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-# include <s3c2410.h>
-#endif
+#if defined(CONFIG_USB_OHCI_NEW) && \
+ defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
+ defined(CONFIG_S3C24X0)
+#include <s3c24x0_cpu.h>
#include <asm/io.h>
int usb_cpu_init(void)
@@ -70,5 +66,6 @@ int usb_cpu_init_fail(void)
return 0;
}
-# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
-#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
+#endif /* defined(CONFIG_USB_OHCI_NEW) && \
+ defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
+ defined(CONFIG_S3C24X0) */
diff --git a/cpu/arm920t/s3c24x0/usb_ohci.c b/cpu/arm920t/s3c24x0/usb_ohci.c
index fe7b533..22615c2 100644
--- a/cpu/arm920t/s3c24x0/usb_ohci.c
+++ b/cpu/arm920t/s3c24x0/usb_ohci.c
@@ -36,14 +36,9 @@
#include <common.h>
/* #include <pci.h> no PCI on the S3C24X0 */
-#ifdef CONFIG_USB_OHCI
-
-#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
-#endif
+#if defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0)
+#include <s3c24x0_cpu.h>
#include <asm/io.h>
#include <malloc.h>
#include <usb.h>
@@ -1750,4 +1745,4 @@ int usb_lowlevel_stop(void)
return 0;
}
-#endif /* CONFIG_USB_OHCI */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */
diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index c19df61..ab615d5 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -132,42 +132,9 @@ copyex:
bne copyex
#endif
-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410)
- /* turn off the watchdog */
-
-# if defined(CONFIG_S3C2400)
-# define pWTCON 0x15300000
-# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
-# define CLKDIVN 0x14800014 /* clock divisor register */
-#else
-# define pWTCON 0x53000000
-# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
-# define INTSUBMSK 0x4A00001C
-# define CLKDIVN 0x4C000014 /* clock divisor register */
-# endif
-
- ldr r0, =pWTCON
- mov r1, #0x0
- str r1, [r0]
-
- /*
- * mask all IRQs by setting all bits in the INTMR - default
- */
- mov r1, #0xffffffff
- ldr r0, =INTMSK
- str r1, [r0]
-# if defined(CONFIG_S3C2410)
- ldr r1, =0x3ff
- ldr r0, =INTSUBMSK
- str r1, [r0]
-# endif
-
- /* FCLK:HCLK:PCLK = 1:2:4 */
- /* default FCLK is 120 MHz ! */
- ldr r0, =CLKDIVN
- mov r1, #3
- str r1, [r0]
-#endif /* CONFIG_S3C2400 || CONFIG_S3C2410 */
+#ifdef CONFIG_DO_ARCH_PRE_LOWLEVEL_INIT
+ bl arch_pre_lowlevel_init
+#endif
/*
* we do sys-critical inits only at reboot,
diff --git a/drivers/i2c/s3c24x0_i2c.c b/drivers/i2c/s3c24x0_i2c.c
index a21f67a..fd56ca7 100644
--- a/drivers/i2c/s3c24x0_i2c.c
+++ b/drivers/i2c/s3c24x0_i2c.c
@@ -27,12 +27,9 @@
*/
#include <common.h>
-#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
-#endif
+#ifdef CONFIG_S3C24X0
+#include <s3c24x0_cpu.h>
#include <asm/io.h>
#include <i2c.h>
@@ -61,7 +58,7 @@ static int GetI2CSDA(void)
{
struct s3c24x0_gpio *gpio = S3C24X0_GetBase_GPIO();
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
return (readl(&gpio->GPEDAT) & 0x8000) >> 15;
#endif
#ifdef CONFIG_S3C2400
@@ -80,7 +77,7 @@ static void SetI2CSCL(int x)
{
struct s3c24x0_gpio *gpio = S3C24X0_GetBase_GPIO();
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
writel((readl(&gpio->GPEDAT) & ~0x4000) | (x & 1) << 14, &gpio->GPEDAT);
#endif
#ifdef CONFIG_S3C2400
@@ -132,7 +129,7 @@ void i2c_init(int speed, int slaveadd)
}
if ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
ulong old_gpecon = readl(&gpio->GPECON);
#endif
#ifdef CONFIG_S3C2400
@@ -141,7 +138,7 @@ void i2c_init(int speed, int slaveadd)
/* bus still busy probably by (most) previously interrupted
transfer */
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
writel((readl(&gpio->GPECON) & ~0xF0000000) | 0x10000000,
&gpio->GPECON);
@@ -167,7 +164,7 @@ void i2c_init(int speed, int slaveadd)
udelay(1000);
/* restore pin functions */
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
writel(old_gpecon, &gpio->GPECON);
#endif
#ifdef CONFIG_S3C2400
@@ -445,3 +442,4 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
len) != 0);
}
#endif /* CONFIG_HARD_I2C */
+#endif /* CONFIG_S3C24X0 */
diff --git a/drivers/mtd/nand/s3c2410_nand.c b/drivers/mtd/nand/s3c2410_nand.c
index 1dfe59e..5157941 100644
--- a/drivers/mtd/nand/s3c2410_nand.c
+++ b/drivers/mtd/nand/s3c2410_nand.c
@@ -21,7 +21,7 @@
#include <common.h>
#include <nand.h>
-#include <s3c2410.h>
+#include <s3c24x0_cpu.h>
#include <asm/io.h>
#define S3C2410_NFCONF_EN (1<<15)
diff --git a/drivers/rtc/s3c24x0_rtc.c b/drivers/rtc/s3c24x0_rtc.c
index 9476115..7afbb2b 100644
--- a/drivers/rtc/s3c24x0_rtc.c
+++ b/drivers/rtc/s3c24x0_rtc.c
@@ -30,12 +30,7 @@
#if (defined(CONFIG_CMD_DATE))
-#if defined(CONFIG_S3C2400)
-#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
-#endif
-
+#include <s3c24x0_cpu.h>
#include <rtc.h>
#include <asm/io.h>
diff --git a/drivers/serial/serial_s3c24x0.c b/drivers/serial/serial_s3c24x0.c
index ff1ec57..059d7b4 100644
--- a/drivers/serial/serial_s3c24x0.c
+++ b/drivers/serial/serial_s3c24x0.c
@@ -19,11 +19,7 @@
*/
#include <common.h>
-#if defined(CONFIG_S3C2400) || defined(CONFIG_TRAB)
-#include <s3c2400.h>
-#elif defined(CONFIG_S3C2410)
-#include <s3c2410.h>
-#endif
+#include <s3c24x0_cpu.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index 67d478f..b03a600 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -65,8 +65,7 @@
#endif
#if defined(CONFIG_ARM920T) || \
- defined(CONFIG_S3C2400) || \
- defined(CONFIG_S3C2410) || \
+ defined(CONFIG_S3C24X0) || \
defined(CONFIG_S3C6400) || \
defined(CONFIG_440EP) || \
defined(CONFIG_PCI_OHCI) || \
diff --git a/include/common.h b/include/common.h
index ff4f821..193bec4 100644
--- a/include/common.h
+++ b/include/common.h
@@ -491,8 +491,9 @@ int prt_mpc8220_clks (void);
ulong get_OPB_freq (void);
ulong get_PCI_freq (void);
#endif
-#if defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) || \
- defined(CONFIG_LH7A40X) || defined(CONFIG_S3C6400)
+#if defined(CONFIG_S3C24X0) || \
+ defined(CONFIG_LH7A40X) || \
+ defined(CONFIG_S3C6400)
void s3c2410_irq(void);
#define ARM920_IRQ_CALLBACK s3c2410_irq
ulong get_FCLK (void);
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h
index de3092d..70d775f 100644
--- a/include/configs/VCMA9.h
+++ b/include/configs/VCMA9.h
@@ -34,8 +34,10 @@
* (easy to change)
*/
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */
+#define CONFIG_DO_ARCH_PRE_LOWLEVEL_INIT
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */
diff --git a/include/configs/sbc2410x.h b/include/configs/sbc2410x.h
index e8afa50..ca36b48 100644
--- a/include/configs/sbc2410x.h
+++ b/include/configs/sbc2410x.h
@@ -44,8 +44,10 @@
* (easy to change)
*/
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
+#define CONFIG_DO_ARCH_PRE_LOWLEVEL_INIT
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */
diff --git a/include/configs/smdk2400.h b/include/configs/smdk2400.h
index 22b88ae..ba4ed82 100644
--- a/include/configs/smdk2400.h
+++ b/include/configs/smdk2400.h
@@ -35,8 +35,10 @@
* (easy to change)
*/
#define CONFIG_ARM920T 1 /* This is an ARM920T core */
-#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */
#define CONFIG_SMDK2400 1 /* on an SAMSUNG SMDK2400 Board */
+#define CONFIG_DO_ARCH_PRE_LOWLEVEL_INIT
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000 /* SMDK2400 has 12 MHz input clock */
diff --git a/include/configs/smdk2410.h b/include/configs/smdk2410.h
index f45d94b..dbd37b4 100644
--- a/include/configs/smdk2410.h
+++ b/include/configs/smdk2410.h
@@ -34,8 +34,10 @@
* (easy to change)
*/
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
-#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */
#define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */
+#define CONFIG_DO_ARCH_PRE_LOWLEVEL_INIT
/* input clock of PLL */
#define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */
diff --git a/include/configs/trab.h b/include/configs/trab.h
index b3f23ae..64fe750 100644
--- a/include/configs/trab.h
+++ b/include/configs/trab.h
@@ -41,9 +41,11 @@
* (easy to change)
*/
#define CONFIG_ARM920T 1 /* This is an arm920t CPU */
-#define CONFIG_S3C2400 1 /* in a SAMSUNG S3C2400 SoC */
+#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */
+#define CONFIG_S3C2400 1 /* specifically a SAMSUNG S3C2400 SoC */
#define CONFIG_TRAB 1 /* on a TRAB Board */
#undef CONFIG_TRAB_50MHZ /* run the CPU at 50 MHz */
+#define CONFIG_DO_ARCH_PRE_LOWLEVEL_INIT
/* automatic software updates (see board/trab/auto_update.c) */
#define CONFIG_AUTO_UPDATE 1
diff --git a/include/s3c2410.h b/include/s3c2410.h
index 763418e..ab6f961 100644
--- a/include/s3c2410.h
+++ b/include/s3c2410.h
@@ -142,4 +142,29 @@ static inline struct s3c2410_sdi *S3C2410_GetBase_SDI(void)
return (struct s3c2410_sdi *)S3C2410_SDI_BASE;
}
+/* Define the registers and bits to use to operate the NAND flash controller. */
+
+/* The NAND control register, */
+#define S3C24X0_NAND_CTRL_REG NFCONF
+/* NAND Enable/disable bit. */
+#define S3C24X0_NAND_EN_BIT (1 << 15)
+/* NAND CE enable/disable bit, */
+#define S3C24X0_NAND_nFCE_BIT (1 << 11)
+/* NAND init ECC bit. */
+#define S3C24X0_NAND_INITECC_BIT (1 << 12)
+
+/* The NAND timimg register. */
+#define S3C24X0_NAND_TIMING_REG NFCONF
+/* NAND TACLS field. */
+#define S3C24X0_NAND_TACLS_BITS(x) ((x) << 8)
+/* NAND TWRPH0 field. */
+#define S3C24X0_NAND_TWRPH0_BITS(x) ((x) << 4)
+/* NAND TWRPH1 field. */
+#define S3C24X0_NAND_TWRPH1_BITS(x) ((x) << 0)
+
+/* The NAND ECC register. */
+#define S3C24X0_NAND_ECC_REG NFECC
+/* NAND INIT ECC bit. */
+#define S3C24X0_NAND_INITECC_BIT (1 << 12)
+
#endif /*__S3C2410_H__*/
diff --git a/include/s3c2440.h b/include/s3c2440.h
new file mode 100644
index 0000000..73b835e
--- /dev/null
+++ b/include/s3c2440.h
@@ -0,0 +1,162 @@
+/*
+ * (C) Copyright 2003
+ * David M?ller ELSOFT AG Switzerland. d.mueller at elsoft.ch
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Modified for the s3c2440 cpu by
+ * (C) Copyright 2009
+ * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/************************************************
+ * NAME : s3c2440.h
+ * Version : 24.10.2008
+ *
+ * Based on S3C2440X User's manual Rev 1.3
+ ************************************************/
+
+#ifndef __S3C2440_H__
+#define __S3C2440_H__
+
+#define S3C24X0_UART_CHANNELS 3
+#define S3C24X0_SPI_CHANNELS 2
+
+enum s3c24x0_uarts_nr {
+ S3C24X0_UART0,
+ S3C24X0_UART1,
+ S3C24X0_UART2
+};
+
+/* S3C2440 device base addresses */
+#define S3C24X0_MEMCTL_BASE 0x48000000
+#define S3C24X0_USB_HOST_BASE 0x49000000
+#define S3C24X0_INTERRUPT_BASE 0x4A000000
+#define S3C24X0_DMA_BASE 0x4B000000
+#define S3C24X0_CLOCK_POWER_BASE 0x4C000000
+#define S3C24X0_LCD_BASE 0x4D000000
+#define S3C2440_NAND_BASE 0x4E000000
+#define S3C2440_CAM_BASE 0x4F000000
+#define S3C24X0_UART_BASE 0x50000000
+#define S3C24X0_TIMER_BASE 0x51000000
+#define S3C24X0_USB_DEVICE_BASE 0x52000140
+#define S3C24X0_WATCHDOG_BASE 0x53000000
+#define S3C24X0_I2C_BASE 0x54000000
+#define S3C24X0_I2S_BASE 0x55000000
+#define S3C24X0_GPIO_BASE 0x56000000
+#define S3C24X0_RTC_BASE 0x57000000
+#define S3C2440_ADC_BASE 0x58000000
+#define S3C24X0_SPI_BASE 0x59000000
+#define S3C2440_SDI_BASE 0x5A000000
+#define S3C2440_AC97_BASE 0x5B000000
+
+/* include common stuff */
+#include <s3c24x0.h>
+
+static inline struct s3c24x0_memctl *S3C24X0_GetBase_MEMCTL(void)
+{
+ return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
+}
+static inline struct s3c24x0_usb_host *S3C24X0_GetBase_USB_HOST(void)
+{
+ return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
+}
+static inline struct s3c24x0_interrupt *S3C24X0_GetBase_INTERRUPT(void)
+{
+ return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
+}
+static inline struct s3c24x0_dmas *S3C24X0_GetBase_DMAS(void)
+{
+ return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
+}
+static inline struct s3c24x0_clock_power *S3C24X0_GetBase_CLOCK_POWER(void)
+{
+ return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
+}
+static inline struct s3c24x0_lcd *S3C24X0_GetBase_LCD(void)
+{
+ return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
+}
+static inline struct s3c2410_nand *S3C2410_GetBase_NAND(void)
+{
+ return (struct s3c2410_nand *)S3C2440_NAND_BASE;
+}
+static inline struct s3c24x0_uart *S3C24X0_GetBase_UART(enum s3c24x0_uarts_nr n)
+{
+ return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
+}
+static inline struct s3c24x0_timers *S3C24X0_GetBase_TIMERS(void)
+{
+ return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
+}
+static inline struct s3c24x0_usb_device *S3C24X0_GetBase_USB_DEVICE(void)
+{
+ return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
+}
+static inline struct s3c24x0_watchdog *S3C24X0_GetBase_WATCHDOG(void)
+{
+ return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
+}
+static inline struct s3c24x0_i2c *S3C24X0_GetBase_I2C(void)
+{
+ return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
+}
+static inline struct s3c24x0_i2s *S3C24X0_GetBase_I2S(void)
+{
+ return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
+}
+static inline struct s3c24x0_gpio *S3C24X0_GetBase_GPIO(void)
+{
+ return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
+}
+static inline struct s3c24x0_rtc *S3C24X0_GetBase_RTC(void)
+{
+ return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
+}
+static inline struct s3c24x0_spi *S3C24X0_GetBase_SPI(void)
+{
+ return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
+}
+
+/* Define the registers and bits to use to operate the NAND flash controller. */
+
+/* The NAND control register, */
+#define S3C24X0_NAND_CTRL_REG NFCONT
+/* NAND Enable/disable bit. */
+#define S3C24X0_NAND_EN_BIT (1 << 0)
+/* NAND CE enable/disable bit, */
+#define S3C24X0_NAND_nFCE_BIT (1 << 1)
+/* NAND init ECC bit. */
+#define S3C24X0_NAND_INITECC_BIT (1 << 4)
+
+/* The NAND timimg register. */
+#define S3C24X0_NAND_TIMING_REG NFCONF
+/* NAND TACLS field. */
+#define S3C24X0_NAND_TACLS_BITS(x) ((x) << 12)
+/* NAND TWRPH0 field. */
+#define S3C24X0_NAND_TWRPH0_BITS(x) ((x) << 8)
+/* NAND TWRPH1 field. */
+#define S3C24X0_NAND_TWRPH1_BITS(x) ((x) << 4)
+
+/* The NAND ECC register. */
+#define S3C24X0_NAND_ECC_REG NFMECC0
+/* NAND INIT ECC bit. */
+#define S3C24X0_NAND_INITECC_BIT (1 << 4)
+
+#endif /*__S3C2440_H__*/
diff --git a/include/s3c24x0.h b/include/s3c24x0.h
index b34c880..b0c8c02 100644
--- a/include/s3c24x0.h
+++ b/include/s3c24x0.h
@@ -82,7 +82,7 @@ struct s3c24x0_interrupt {
S3C24X0_REG32 PRIORITY;
S3C24X0_REG32 INTPND;
S3C24X0_REG32 INTOFFSET;
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
S3C24X0_REG32 SUBSRCPND;
S3C24X0_REG32 INTSUBMSK;
#endif
@@ -92,11 +92,11 @@ struct s3c24x0_interrupt {
/* DMAS (see manual chapter 8) */
struct s3c24x0_dma {
S3C24X0_REG32 DISRC;
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
S3C24X0_REG32 DISRCC;
#endif
S3C24X0_REG32 DIDST;
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
S3C24X0_REG32 DIDSTC;
#endif
S3C24X0_REG32 DCON;
@@ -107,7 +107,7 @@ struct s3c24x0_dma {
#ifdef CONFIG_S3C2400
S3C24X0_REG32 res[1];
#endif
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
S3C24X0_REG32 res[7];
#endif
};
@@ -126,6 +126,9 @@ struct s3c24x0_clock_power {
S3C24X0_REG32 CLKCON;
S3C24X0_REG32 CLKSLOW;
S3C24X0_REG32 CLKDIVN;
+#ifdef CONFIG_S3C2440
+ S3C24X0_REG32 CAMDIVN;
+#endif
};
@@ -145,7 +148,7 @@ struct s3c24x0_lcd {
S3C24X0_REG32 res[8];
S3C24X0_REG32 DITHMODE;
S3C24X0_REG32 TPAL;
-#ifdef CONFIG_S3C2410
+#if defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440)
S3C24X0_REG32 LCDINTPND;
S3C24X0_REG32 LCDSRCPND;
S3C24X0_REG32 LCDINTMSK;
@@ -154,14 +157,32 @@ struct s3c24x0_lcd {
};
-/* NAND FLASH (see S3C2410 manual chapter 6) */
+/* NAND FLASH (see S3C2410/S3C2440 manual chapter 6) */
struct s3c2410_nand {
S3C24X0_REG32 NFCONF;
+#ifdef CONFIG_S3C2440
+ S3C24X0_REG32 NFCONT;
+#endif
S3C24X0_REG32 NFCMD;
S3C24X0_REG32 NFADDR;
S3C24X0_REG32 NFDATA;
+#ifdef CONFIG_S3C2440
+ S3C24X0_REG32 NFMECCD0;
+ S3C24X0_REG32 NFMECCD1;
+ S3C24X0_REG32 NFSECCD;
+#endif
S3C24X0_REG32 NFSTAT;
+#ifndef CONFIG_S3C2440
S3C24X0_REG32 NFECC;
+#else
+ S3C24X0_REG32 NFESTAT0;
+ S3C24X0_REG32 NFESTAT1;
+ S3C24X0_REG32 NFMECC0;
+ S3C24X0_REG32 NFMECC1;
+ S3C24X0_REG32 NFSECC;
+ S3C24X0_REG32 NFSBLOCK;
+ S3C24X0_REG32 NFEBLOCK;
+#endif
};
@@ -335,6 +356,9 @@ struct s3c24x0_i2c {
S3C24X0_REG32 IICSTAT;
S3C24X0_REG32 IICADD;
S3C24X0_REG32 IICDS;
+#ifdef CONFIG_S3C2440
+ S3C24X0_REG32 IICLC;
+#endif
};
@@ -451,6 +475,64 @@ struct s3c24x0_gpio {
S3C24X0_REG32 GSTATUS3;
S3C24X0_REG32 GSTATUS4;
#endif
+#ifdef CONFIG_S3C2440
+ S3C24X0_REG32 GPACON;
+ S3C24X0_REG32 GPADAT;
+ S3C24X0_REG32 res1[2];
+ S3C24X0_REG32 GPBCON;
+ S3C24X0_REG32 GPBDAT;
+ S3C24X0_REG32 GPBUP;
+ S3C24X0_REG32 res2;
+ S3C24X0_REG32 GPCCON;
+ S3C24X0_REG32 GPCDAT;
+ S3C24X0_REG32 GPCUP;
+ S3C24X0_REG32 res3;
+ S3C24X0_REG32 GPDCON;
+ S3C24X0_REG32 GPDDAT;
+ S3C24X0_REG32 GPDUP;
+ S3C24X0_REG32 res4;
+ S3C24X0_REG32 GPECON;
+ S3C24X0_REG32 GPEDAT;
+ S3C24X0_REG32 GPEUP;
+ S3C24X0_REG32 res5;
+ S3C24X0_REG32 GPFCON;
+ S3C24X0_REG32 GPFDAT;
+ S3C24X0_REG32 GPFUP;
+ S3C24X0_REG32 res6;
+ S3C24X0_REG32 GPGCON;
+ S3C24X0_REG32 GPGDAT;
+ S3C24X0_REG32 GPGUP;
+ S3C24X0_REG32 res7;
+ S3C24X0_REG32 GPHCON;
+ S3C24X0_REG32 GPHDAT;
+ S3C24X0_REG32 GPHUP;
+ S3C24X0_REG32 res8;
+
+ S3C24X0_REG32 MISCCR;
+ S3C24X0_REG32 DCLKCON;
+ S3C24X0_REG32 EXTINT0;
+ S3C24X0_REG32 EXTINT1;
+ S3C24X0_REG32 EXTINT2;
+ S3C24X0_REG32 EINTFLT0;
+ S3C24X0_REG32 EINTFLT1;
+ S3C24X0_REG32 EINTFLT2;
+ S3C24X0_REG32 EINTFLT3;
+ S3C24X0_REG32 EINTMASK;
+ S3C24X0_REG32 EINTPEND;
+ S3C24X0_REG32 GSTATUS0;
+ S3C24X0_REG32 GSTATUS1;
+ S3C24X0_REG32 GSTATUS2;
+ S3C24X0_REG32 GSTATUS3;
+ S3C24X0_REG32 GSTATUS4;
+ S3C24X0_REG32 res9;
+
+ S3C24X0_REG32 DSC0;
+ S3C24X0_REG32 DSC1;
+ S3C24X0_REG32 MSLCON;
+ S3C24X0_REG32 GPJCON;
+ S3C24X0_REG32 GPJDAT;
+ S3C24X0_REG32 GPJUP;
+#endif
};
diff --git a/include/s3c24x0_cpu.h b/include/s3c24x0_cpu.h
new file mode 100644
index 0000000..cade11b
--- /dev/null
+++ b/include/s3c24x0_cpu.h
@@ -0,0 +1,29 @@
+/*
+ * (C) Copyright 2009
+ * Kevin Morfitt, Fearnside Systems Ltd, <kevin.morfitt@fearnside-systems.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifdef CONFIG_S3C2400
+ #include <s3c2400.h>
+#elif defined CONFIG_S3C2410
+ #include <s3c2410.h>
+#elif defined CONFIG_S3C2440
+ #include <s3c2440.h>
+#else
+ #error Please define the s3c24x0 cpu type
+#endif
--
1.6.1.2
next prev reply other threads:[~2009-06-25 0:36 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-06-25 0:35 [U-Boot] [PATCH-ARM, MTD] Add support for Embest SBC2440-II Board 4/7 kevin.morfitt at fearnside-systems.co.uk
2009-06-25 0:36 ` kevin.morfitt at fearnside-systems.co.uk [this message]
2009-07-08 20:54 ` [U-Boot] [PATCH-ARM] Add support for Embest SBC2440-II Board 5/7 Jean-Christophe PLAGNIOL-VILLARD
2009-07-09 18:40 ` kevin.morfitt at fearnside-systems.co.uk
2009-07-09 20:31 ` Jean-Christophe PLAGNIOL-VILLARD
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