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From: Tom <Tom.Rix@windriver.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 5/9 V3] convert common files to new SoC access
Date: Sat, 30 Jan 2010 19:20:00 -0600	[thread overview]
Message-ID: <4B64DAC0.3090404@windriver.com> (raw)
In-Reply-To: <4B5AD783.7080904@scharsoft.de>

Jens Scharsig wrote:
> * convert common files in cpu/../at91 and a lot of drivers to use
>   c stucture SoC access
> * add's a warning to all files, which need update to new SoC access 
> 
> Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
> ---
>  cpu/arm926ejs/at91/at91cap9_devices.c       |    4 +
>  cpu/arm926ejs/at91/at91sam9261_devices.c    |    4 +
>  cpu/arm926ejs/at91/at91sam9263_devices.c    |   33 ++++++--
>  cpu/arm926ejs/at91/at91sam9m10g45_devices.c |    4 +
>  cpu/arm926ejs/at91/at91sam9rl_devices.c     |    4 +
>  cpu/arm926ejs/at91/clock.c                  |   51 +++++++------
>  cpu/arm926ejs/at91/cpu.c                    |    4 +
>  cpu/arm926ejs/at91/led.c                    |    7 ++
>  cpu/arm926ejs/at91/lowlevel_init.S          |  110 +++++++++++++++------------
>  cpu/arm926ejs/at91/reset.c                  |    8 +-
>  cpu/arm926ejs/at91/timer.c                  |   17 +++--
>  drivers/i2c/soft_i2c.c                      |   11 ++-
>  drivers/serial/at91rm9200_usart.c           |    8 ++
>  drivers/serial/atmel_usart.c                |    4 +
>  drivers/spi/atmel_dataflash_spi.c           |    4 +
>  drivers/usb/host/ohci-at91.c                |    5 +
>  drivers/video/bus_vcxk.c                    |   22 +++++-
>  include/i2c.h                               |    5 +
>  18 files changed, 209 insertions(+), 96 deletions(-)
> 
> diff --git a/cpu/arm926ejs/at91/at91cap9_devices.c b/cpu/arm926ejs/at91/at91cap9_devices.c
> index c41e139..0f8086d 100644
> --- a/cpu/arm926ejs/at91/at91cap9_devices.c
> +++ b/cpu/arm926ejs/at91/at91cap9_devices.c
> @@ -27,6 +27,10 @@
>   */
>  
>  #include <common.h>
> +#ifndef CONFIG_AT91_LEGACY

This should be
#ifdef CONFIG_AT91_LEGACY
The additions you made to the board configs should take care of this.
Perhaps add an
#ifndef CONFIG_AT91_LEGACY
#error "Error this is legacy code"
Fix globally

> +#define CONFIG_AT91_LEGACY
> +#warning Please update to use C structur SoC access !

'structure'
Fix globally

> +#endif
>  #include <asm/arch/at91_common.h>
>  #include <asm/arch/at91_pmc.h>
>  #include <asm/arch/gpio.h>
> diff --git a/cpu/arm926ejs/at91/at91sam9261_devices.c b/cpu/arm926ejs/at91/at91sam9261_devices.c
> index 9112ccb..172845a 100644
> --- a/cpu/arm926ejs/at91/at91sam9261_devices.c
> +++ b/cpu/arm926ejs/at91/at91sam9261_devices.c
> @@ -23,6 +23,10 @@
>   */
>  
>  #include <common.h>
> +#ifndef CONFIG_AT91_LEGACY
> +#define CONFIG_AT91_LEGACY
> +#warning Please update to use C structur SoC access !
> +#endif
>  #include <asm/arch/at91_common.h>
>  #include <asm/arch/at91_pmc.h>
>  #include <asm/arch/gpio.h>
> diff --git a/cpu/arm926ejs/at91/at91sam9263_devices.c b/cpu/arm926ejs/at91/at91sam9263_devices.c
> index eb56ebf..05a5ab5 100644
> --- a/cpu/arm926ejs/at91/at91sam9263_devices.c
> +++ b/cpu/arm926ejs/at91/at91sam9263_devices.c
> @@ -27,37 +27,46 @@
>   */
>  
>  #include <common.h>
> +#include <asm/arch/hardware.h>
> +#include <asm/arch/io.h>
>  #include <asm/arch/at91_common.h>
>  #include <asm/arch/at91_pmc.h>
> -#include <asm/arch/gpio.h>
> -#include <asm/arch/io.h>
> +#include <asm/arch/at91_pio.h>
>  
>  void at91_serial0_hw_init(void)
>  {
> +	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
> +
>  	at91_set_a_periph(AT91_PORTPIN(A, 26), 1);		/* TXD0 */
>  	at91_set_a_periph(AT91_PORTPIN(A, 27), 0);		/* RXD0 */
> -	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
> +	writel(1 << AT91SAM9263_ID_US0, &pmc->pcer);
>  }
>  
>  void at91_serial1_hw_init(void)
>  {
> +	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
> +
>  	at91_set_a_periph(AT91_PORTPIN(D, 0), 1);		/* TXD1 */
>  	at91_set_a_periph(AT91_PORTPIN(D, 1), 0);		/* RXD1 */
> -	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1);
> +	writel(1 << AT91SAM9263_ID_US1, &pmc->pcer);
>  }
>  
>  void at91_serial2_hw_init(void)
>  {
> +	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
> +
>  	at91_set_a_periph(AT91_PORTPIN(D, 2), 1);		/* TXD2 */
>  	at91_set_a_periph(AT91_PORTPIN(D, 3), 0);		/* RXD2 */
> -	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2);
> +	writel(1 << AT91SAM9263_ID_US2, &pmc->pcer);
>  }
>  
>  void at91_serial3_hw_init(void)
>  {
> +	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
> +
>  	at91_set_a_periph(AT91_PORTPIN(C, 30), 0);		/* DRXD */
>  	at91_set_a_periph(AT91_PORTPIN(C, 31), 1);		/* DTXD */
> -	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
> +	writel(1 << AT91_ID_SYS, &pmc->pcer);
>  }
>  
>  void at91_serial_hw_init(void)
> @@ -82,12 +91,14 @@ void at91_serial_hw_init(void)
>  #ifdef CONFIG_HAS_DATAFLASH
>  void at91_spi0_hw_init(unsigned long cs_mask)
>  {
> +	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
> +
>  	at91_set_b_periph(AT91_PORTPIN(A, 0), 0);	/* SPI0_MISO */
>  	at91_set_b_periph(AT91_PORTPIN(A, 1), 0);	/* SPI0_MOSI */
>  	at91_set_b_periph(AT91_PORTPIN(A, 2), 0);	/* SPI0_SPCK */
>  
>  	/* Enable clock */
> -	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0);
> +	writel(1 << AT91SAM9263_ID_SPI0, &pmc->pcer);
>  
>  	if (cs_mask & (1 << 0)) {
>  		at91_set_b_periph(AT91_PORTPIN(A, 5), 1);
> @@ -117,12 +128,14 @@ void at91_spi0_hw_init(unsigned long cs_mask)
>  
>  void at91_spi1_hw_init(unsigned long cs_mask)
>  {
> +	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
> +
>  	at91_set_a_periph(AT91_PORTPIN(B, 12), 0);	/* SPI1_MISO */
>  	at91_set_a_periph(AT91_PORTPIN(B, 13), 0);	/* SPI1_MOSI */
>  	at91_set_a_periph(AT91_PORTPIN(B, 14), 0);	/* SPI1_SPCK */
>  
>  	/* Enable clock */
> -	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI1);
> +	writel(1 << AT91SAM9263_ID_SPI1, &pmc->pcer);
>  
>  	if (cs_mask & (1 << 0)) {
>  		at91_set_a_periph(AT91_PORTPIN(B, 15), 1);
> @@ -190,10 +203,12 @@ void at91_uhp_hw_init(void)
>  #ifdef CONFIG_AT91_CAN
>  void at91_can_hw_init(void)
>  {
> +	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
> +
>  	at91_set_a_periph(AT91_PORTPIN(A, 13), 0);	/* CAN_TX */
>  	at91_set_a_periph(AT91_PORTPIN(A, 14), 1);	/* CAN_RX */
>  
>  	/* Enable clock */
> -	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_CAN);
> +	writel(1 << AT91SAM9263_ID_CAN, &pmc->pcer);
>  }
>  #endif
> diff --git a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
> index c3a2102..55b9b5a 100644
> --- a/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
> +++ b/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
> @@ -23,6 +23,10 @@
>   */
>  
>  #include <common.h>
> +#ifndef CONFIG_AT91_LEGACY
> +#define CONFIG_AT91_LEGACY
> +#warning Please update to use C structur SoC access !
> +#endif
>  #include <asm/arch/at91_common.h>
>  #include <asm/arch/at91_pmc.h>
>  #include <asm/arch/gpio.h>
> diff --git a/cpu/arm926ejs/at91/at91sam9rl_devices.c b/cpu/arm926ejs/at91/at91sam9rl_devices.c
> index 9c5624a..946bdc5 100644
> --- a/cpu/arm926ejs/at91/at91sam9rl_devices.c
> +++ b/cpu/arm926ejs/at91/at91sam9rl_devices.c
> @@ -23,6 +23,10 @@
>   */
>  
>  #include <common.h>
> +#ifndef CONFIG_AT91_LEGACY
> +#define CONFIG_AT91_LEGACY
> +#warning Please update to use C structur SoC access !
> +#endif
>  #include <asm/arch/at91_common.h>
>  #include <asm/arch/at91_pmc.h>
>  #include <asm/arch/gpio.h>
> diff --git a/cpu/arm926ejs/at91/clock.c b/cpu/arm926ejs/at91/clock.c
> index 574f488..7e03907 100644
> --- a/cpu/arm926ejs/at91/clock.c
> +++ b/cpu/arm926ejs/at91/clock.c
> @@ -13,9 +13,9 @@
>  
>  #include <config.h>
>  #include <asm/arch/hardware.h>
> +#include <asm/arch/io.h>
>  #include <asm/arch/at91_pmc.h>
>  #include <asm/arch/clk.h>
> -#include <asm/arch/io.h>
>  
>  static unsigned long cpu_clk_rate_hz;
>  static unsigned long main_clk_rate_hz;
> @@ -57,14 +57,14 @@ u32 get_pllb_init(void)
>  static unsigned long at91_css_to_rate(unsigned long css)
>  {
>  	switch (css) {
> -		case AT91_PMC_CSS_SLOW:
> -			return AT91_SLOW_CLOCK;
> -		case AT91_PMC_CSS_MAIN:
> -			return main_clk_rate_hz;
> -		case AT91_PMC_CSS_PLLA:
> -			return plla_rate_hz;
> -		case AT91_PMC_CSS_PLLB:
> -			return pllb_rate_hz;
> +	case AT91_PMC_MCKR_CSS_SLOW:
> +		return AT91_SLOW_CLOCK;
> +	case AT91_PMC_MCKR_CSS_MAIN:
> +		return main_clk_rate_hz;
> +	case AT91_PMC_MCKR_CSS_PLLA:
> +		return plla_rate_hz;
> +	case AT91_PMC_MCKR_CSS_PLLB:
> +		return pllb_rate_hz;

Please submit ws fixes seperately

>  	}
>  
>  	return 0;
> @@ -146,6 +146,7 @@ static u32 at91_pll_rate(u32 freq, u32 reg)
>  int at91_clock_init(unsigned long main_clock)
>  {
>  	unsigned freq, mckr;
> +	at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
>  #ifndef AT91_MAIN_CLOCK
>  	unsigned tmp;
>  	/*
> @@ -164,7 +165,7 @@ int at91_clock_init(unsigned long main_clock)
>  	main_clk_rate_hz = main_clock;
>  
>  	/* report if PLLA is more than mildly overclocked */
> -	plla_rate_hz = at91_pll_rate(main_clock, at91_sys_read(AT91_CKGR_PLLAR));
> +	plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
>  
>  #ifdef CONFIG_USB_ATMEL
>  	/*
> @@ -174,7 +175,7 @@ int at91_clock_init(unsigned long main_clock)
>  	 * REVISIT:  assumes MCK doesn't derive from PLLB!
>  	 */
>  	at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
> -			     AT91_PMC_USB96M;
> +			     AT91_PMC_PLLBR_USBDIV_2;

The name of this define should not have changed
This is reoccurring problem in this patchset.
Revert globally


>  	pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init);
>  #endif
>  
> @@ -182,28 +183,32 @@ int at91_clock_init(unsigned long main_clock)
>  	 * MCK and CPU derive from one of those primary clocks.
>  	 * For now, assume this parentage won't change.
>  	 */
> -	mckr = at91_sys_read(AT91_PMC_MCKR);
> +	mckr = readl(&pmc->mckr);
>  #if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
>  	/* plla divisor by 2 */
>  	plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
>  #endif
> -	freq = mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_CSS);
> +	mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);

Similar.
The name of the define should not have changed
Revert the name changes
Revert globally

> +	freq = mck_rate_hz;
>  
> -	freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));			/* prescale */
> +	freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2));	/* prescale */
>  #if defined(CONFIG_AT91RM9200)
> -	mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));	/* mdiv */
> +	/* mdiv */
> +	mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
>  #elif defined(CONFIG_AT91SAM9G20)
> -	mck_rate_hz = (mckr & AT91_PMC_MDIV) ?
> -		freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;		/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
> -	if (mckr & AT91_PMC_PDIV)
> -		freq /= 2;						/* processor clock division */
> +	/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
> +	mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
> +		freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
> +	if (mckr & AT91_PMC_MCKR_MDIV_MASK)
> +		freq /= 2;			/* processor clock division */
>  #elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
> -	mck_rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
> -		freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));	/* mdiv */
> +	mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == AT91SAM9_PMC_MDIV_3
> +		? freq / 3
> +		: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
>  #else
> -	mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));	/* mdiv */
> +	mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
>  #endif
>  	cpu_clk_rate_hz = freq;
>  
> -		return 0;
> +	return 0;
>  }
> diff --git a/cpu/arm926ejs/at91/cpu.c b/cpu/arm926ejs/at91/cpu.c
> index f2f7b62..993b299 100644
> --- a/cpu/arm926ejs/at91/cpu.c
> +++ b/cpu/arm926ejs/at91/cpu.c
> @@ -22,6 +22,10 @@
>   */
>  
>  #include <common.h>
> +#ifdef CONFIG_AT91_LEGACY
> +#warning Your board is using legacy SoC access. Please update!
> +#endif
> +
>  #include <asm/arch/hardware.h>
>  #include <asm/arch/at91_pmc.h>
>  #include <asm/arch/clk.h>
> diff --git a/cpu/arm926ejs/at91/led.c b/cpu/arm926ejs/at91/led.c
> index be68f59..0a0bb57 100644
> --- a/cpu/arm926ejs/at91/led.c
> +++ b/cpu/arm926ejs/at91/led.c
> @@ -23,7 +23,14 @@
>   */
>  
>  #include <common.h>
> +/*
> +#ifndef CONFIG_AT91_LEGACY
> +#define CONFIG_AT91_LEGACY
> +#warning Please update to use C structur SoC access !
> +#endif
> +*/
>  #include <asm/arch/at91_pmc.h>
> +#include <asm/arch/at91_pio.h>
>  #include <asm/arch/gpio.h>
>  #include <asm/arch/io.h>
>  
> diff --git a/cpu/arm926ejs/at91/lowlevel_init.S b/cpu/arm926ejs/at91/lowlevel_init.S
> index f11ebc6..869b581 100644
> --- a/cpu/arm926ejs/at91/lowlevel_init.S
> +++ b/cpu/arm926ejs/at91/lowlevel_init.S
> @@ -27,15 +27,20 @@
>   */
>  
>  #include <config.h>
> -#include <version.h>
>  #include <asm/arch/hardware.h>
>  #include <asm/arch/at91_pmc.h>
> -#include <asm/arch/at91_pio.h>
> -#include <asm/arch/at91_rstc.h>
>  #include <asm/arch/at91_wdt.h>
> -#include <asm/arch/at91sam9_matrix.h>
> +#include <asm/arch/at91_pio.h>
> +#include <asm/arch/at91_matrix.h>
>  #include <asm/arch/at91sam9_sdramc.h>
>  #include <asm/arch/at91sam9_smc.h>
> +#include <asm/arch/at91_rstc.h>
> +#ifdef CONFIG_AT91_LEGACY
> +#include <asm/arch/at91sam9_matrix.h>
> +#endif
> +#ifndef CONFIG_SYS_MATRIX_EBICSA_VAL
> +#define CONFIG_SYS_MATRIX_EBICSA_VAL CONFIG_SYS_MATRIX_EBI0CSA_VAL
> +#endif
>  
>  _TEXT_BASE:
>  	.word	TEXT_BASE
> @@ -75,7 +80,7 @@ POS1:
>   * - Check if the PLL is already initialized
>   * ----------------------------------------------------------------------------
>   */
> -	ldr	r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
> +	ldr	r1, =(AT91_ASM_PMC_MCKR)

This looks ok

>  	ldr	r0, [r1]
>  	and	r0, r0, #3
>  	cmp	r0, #0
> @@ -85,18 +90,18 @@ POS1:
>   * - Enable the Main Oscillator
>   * ---------------------------------------------------------------------------
>   */
> -	ldr	r1, =(AT91_BASE_SYS + AT91_CKGR_MOR)
> -	ldr	r2, =(AT91_BASE_SYS + AT91_PMC_SR)
> +	ldr	r1, =(AT91_ASM_PMC_MOR)
> +	ldr	r2, =(AT91_ASM_PMC_SR)
>  	/* Main oscillator Enable register PMC_MOR: */
>  	ldr	r0, =CONFIG_SYS_MOR_VAL
>  	str	r0, [r1]
>  
>  	/* Reading the PMC Status to detect when the Main Oscillator is enabled */
> -	mov	r4, #AT91_PMC_MOSCS
> +	mov	r4, #AT91_PMC_IxR_MOSCS

This #define should not have changed name

>  MOSCS_Loop:
>  	ldr	r3, [r2]
>  	and	r3, r4, r3
> -	cmp	r3, #AT91_PMC_MOSCS
> +	cmp	r3, #AT91_PMC_IxR_MOSCS

This #define should not have changed name
You get the idea..

>  	bne	MOSCS_Loop
>  
>  /* ----------------------------------------------------------------------------
> @@ -105,56 +110,71 @@ MOSCS_Loop:
>   * Setup PLLA
>   * ----------------------------------------------------------------------------
>   */
> -	ldr	r1, =(AT91_BASE_SYS + AT91_CKGR_PLLAR)
> +	ldr	r1, =(AT91_ASM_PMC_PLLAR)
>  	ldr	r0, =CONFIG_SYS_PLLAR_VAL
>  	str	r0, [r1]
>  
>  	/* Reading the PMC Status register to detect when the PLLA is locked */
> -	mov	r4, #AT91_PMC_LOCKA
> +	mov	r4, #AT91_PMC_IxR_LOCKA
>  MOSCS_Loop1:
>  	ldr	r3, [r2]
>  	and	r3, r4, r3
> -	cmp	r3, #AT91_PMC_LOCKA
> +	cmp	r3, #AT91_PMC_IxR_LOCKA
>  	bne	MOSCS_Loop1
>  

This is new
and not a simple structure change.
This should go into its own patch

> +#ifdef CONFIG_SYS_PLLBR_VAL
> +	ldr	r1, =(AT91_ASM_PMC_PLLBR)
> +	ldr	r0, =CONFIG_SYS_PLLBR_VAL
> +	str	r0, [r1]
> +
> +	/* Reading the PMC Status register to detect when the PLLB is locked */
> +	mov	r4, #AT91_PMC_IxR_LOCKB
> +PLLB_Loop:
> +	ldr	r3, [r2]
> +	and	r3, r4, r3
> +	cmp	r3, #AT91_PMC_IxR_LOCKB
> +	bne	PLLB_Loop
> +#endif
> +
>  /* ----------------------------------------------------------------------------
>   * PMC Init Step 3.
>   * ----------------------------------------------------------------------------
>   * - Switch on the Main Oscillator
>   * ----------------------------------------------------------------------------
>   */
> -	ldr	r1, =(AT91_BASE_SYS + AT91_PMC_MCKR)
> +	ldr	r1, =(AT91_ASM_PMC_MCKR)
>  
>  	/* -Master Clock Controller register PMC_MCKR */
>  	ldr	r0, =CONFIG_SYS_MCKR1_VAL
>  	str	r0, [r1]
>  
>  	/* Reading the PMC Status to detect when the Master clock is ready */
> -	mov	r4, #AT91_PMC_MCKRDY
> +	mov	r4, #AT91_PMC_IxR_MCKRDY
>  MCKRDY_Loop:
>  	ldr	r3, [r2]
>  	and	r3, r4, r3
> -	cmp	r3, #AT91_PMC_MCKRDY
> +	cmp	r3, #AT91_PMC_IxR_MCKRDY
>  	bne	MCKRDY_Loop
>  
>  	ldr	r0, =CONFIG_SYS_MCKR2_VAL
>  	str	r0, [r1]
>  
>  	/* Reading the PMC Status to detect when the Master clock is ready */
> -	mov	r4, #AT91_PMC_MCKRDY
> +	mov	r4, #AT91_PMC_IxR_MCKRDY
>  MCKRDY_Loop1:
>  	ldr	r3, [r2]
>  	and	r3, r4, r3
> -	cmp	r3, #AT91_PMC_MCKRDY
> +	cmp	r3, #AT91_PMC_IxR_MCKRDY
>  	bne	MCKRDY_Loop1
> -
>  PLL_setup_end:
>  
>  /* ----------------------------------------------------------------------------
>   * - memory control configuration 2
>   * ----------------------------------------------------------------------------
>   */
> -	ldr	r0, =(AT91_BASE_SYS + AT91_SDRAMC_TR)
> +
> +	ldr	r0, =(AT91_ASM_SDRAMC_TR)
> +
ws
remove extra

Tom

  reply	other threads:[~2010-01-31  1:20 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-01-23 11:03 [U-Boot] [PATCH 5/9 V3] convert common files to new SoC access Jens Scharsig
2010-01-31  1:20 ` Tom [this message]
2010-01-31 16:15   ` Jens Scharsig
2010-02-03 21:46 ` [U-Boot] [PATCH 5/9 V4] " Jens Scharsig
2010-02-10 11:25   ` Daniel Gorsulowski
2010-02-11  7:38     ` Daniel Gorsulowski
2010-02-11  7:52   ` Daniel Gorsulowski
2010-02-11  9:11     ` Daniel Gorsulowski
2010-02-14 11:25     ` Jens Scharsig

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