[U-Boot] [PATCH] Add support for Indefia Nimbus Cloud Board

[Semih Hazar <semih.hazar@indefia.com>]

Nimbus Cloud is an AVR32 based single board computer with
256MiB NAND, 64MiB SDRAM, battery backed RTC, LCD/touch
screen support, VGA Output, Ethernet and offers seamless
integration with Indefia's Zigbee transceivers.

---
 CREDITS                                 |    4 +
 MAINTAINERS                             |    4 +
 MAKEALL                                 |    1 +
 Makefile                                |    3 +
 board/indefia/nimbuscloud/Makefile      |   40 +++++++
 board/indefia/nimbuscloud/config.mk     |    3 +
 board/indefia/nimbuscloud/nimbuscloud.c |  165 +++++++++++++++++++++++++++
 board/indefia/nimbuscloud/nimbuscloud.h |    8 ++
 board/indefia/nimbuscloud/u-boot.lds    |   72 ++++++++++++
 include/configs/nimbuscloud.h           |  184 +++++++++++++++++++++++++++++++
 10 files changed, 484 insertions(+), 0 deletions(-)

diff --git a/CREDITS b/CREDITS
index 2471029..69a9dde 100644
--- a/CREDITS
+++ b/CREDITS
@@ -196,6 +196,10 @@ N: Anne-Sophie Harnois
 E: Anne-Sophie.Harnois at nextream.fr
 D: Port to Walnut405 board
 
+N: Semih Hazar
+E: semih.hazar at indefia.com
+D: Nimbus Cloud board support
+
 N: Andreas Heppel
 E: aheppel at sysgo.de
 D: CPU Support for MPC 75x; board support for Eltec BAB750 [obsolete!]
diff --git a/MAINTAINERS b/MAINTAINERS
index e8ba4bc..9202137 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -881,6 +881,10 @@ Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
 
 	FAVR-32-EZKIT		AT32AP7000
 
+Semih Hazar <semih.hazar@indefia.com>
+
+	NIMBUSCLOUD		AT32AP7000
+
 Mark Jackson <mpfj@mimc.co.uk>
 
 	MIMC200			AT32AP7000
diff --git a/MAKEALL b/MAKEALL
index 15e93cf..6ee30ec 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -866,6 +866,7 @@ LIST_avr32="		\
 	favr-32-ezkit	\
 	hammerhead	\
 	mimc200		\
+	nimbuscloud	\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 69b963f..8c4e453 100644
--- a/Makefile
+++ b/Makefile
@@ -3593,6 +3593,9 @@ hammerhead_config	:	unconfig
 mimc200_config		:	unconfig
 	@$(MKCONFIG) $(@:_config=) avr32 at32ap mimc200 mimc at32ap700x
 
+nimbuscloud_config	:	unconfig
+	 @$(MKCONFIG) $(@:_config=) avr32 at32ap nimbuscloud indefia at32ap700x
+
 #========================================================================
 # SH3 (SuperH)
 #========================================================================
diff --git a/board/indefia/nimbuscloud/Makefile b/board/indefia/nimbuscloud/Makefile
new file mode 100644
index 0000000..43a9c68
--- /dev/null
+++ b/board/indefia/nimbuscloud/Makefile
@@ -0,0 +1,40 @@
+#
+# Copyright (C) 2008-2009 Indefia
+#
+# See file CREDITS for list of people who contributed to this project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	:= $(obj)lib$(BOARD).a
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/indefia/nimbuscloud/config.mk b/board/indefia/nimbuscloud/config.mk
new file mode 100644
index 0000000..9a794e5
--- /dev/null
+++ b/board/indefia/nimbuscloud/config.mk
@@ -0,0 +1,3 @@
+TEXT_BASE		= 0x00000000
+PLATFORM_RELFLAGS	+= -ffunction-sections -fdata-sections
+PLATFORM_LDFLAGS	+= --gc-sections
diff --git a/board/indefia/nimbuscloud/nimbuscloud.c b/board/indefia/nimbuscloud/nimbuscloud.c
new file mode 100644
index 0000000..e869a97
--- /dev/null
+++ b/board/indefia/nimbuscloud/nimbuscloud.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (C) 2008-2009 Indefia
+ *
+ * Based on atngw100.c (c) Atmel Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+
+#include <asm/io.h>
+#include <asm/sdram.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/portmux.h>
+#include <netdev.h>
+#include <net.h>
+
+#include "nimbuscloud.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct sdram_config sdram_config = {
+	.data_bits	= SDRAM_DATA_32BIT,
+	.row_bits	= 13,
+	.col_bits	= 9,
+	.bank_bits	= 2,
+	.cas		= 3,
+	.twr		= 2,
+	.trc		= 7,
+	.trp		= 2,
+	.trcd		= 2,
+	.tras		= 5,
+	.txsr		= 5,
+	/* 7.81 us */
+	.refresh_period	= (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
+};
+
+static u8 read_configsw(void) {
+	u8 configsw = 0;
+
+	if ( ! gpio_get_value(GPIO_PIN_PB(13)) )
+		configsw |= 1;
+	if ( ! gpio_get_value(GPIO_PIN_PB(14)) )
+		configsw |= 2;
+	if ( ! gpio_get_value(GPIO_PIN_PB(15)) )
+		configsw |= 4;
+	if ( ! gpio_get_value(GPIO_PIN_PB(16)) )
+		configsw |= 8;
+
+	return configsw;
+}
+
+
+int board_early_init_f(void)
+{
+	/* Enable SDRAM in the EBI mux */
+	hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
+
+	portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
+	portmux_enable_usart1(PORTMUX_DRIVE_MIN);
+
+	/* Enable GPIO on config swicthes */
+	portmux_select_gpio(
+		PORTMUX_PORT_B, 
+		(1 << 13) | (1 << 14) | (1 << 15) | (1 << 16),
+		PORTMUX_DIR_INPUT | PORTMUX_PULL_UP);
+
+#if defined(CONFIG_MACB)
+	portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
+#endif
+#if defined(CONFIG_MMC)
+	portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
+#endif
+
+	if ( (read_configsw() & 1) == 1 ) {
+		gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+	}
+
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	unsigned long expected_size;
+	unsigned long actual_size;
+	void *sdram_base;
+
+	sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
+
+	expected_size = sdram_init(sdram_base, &sdram_config);
+	actual_size = get_ram_size(sdram_base, expected_size);
+
+	unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
+
+	if (expected_size != actual_size)
+		printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+				actual_size >> 20, expected_size >> 20);
+
+	return actual_size;
+}
+
+int misc_init_r(void)
+{
+	char buf[3];
+	u8 configsw;
+
+	configsw = read_configsw();
+
+	if ( (configsw & 1) == 1 ) {
+		setenv("bootdelay", "0");
+	}
+
+	sprintf(buf, "%d", configsw);
+	setenv("configsw", buf);
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	gd->bd->bi_phy_id[0] = 0x01;
+	return 0;
+}
+
+#ifdef CONFIG_CMD_NET
+
+int board_eth_init(bd_t *bi)
+{
+	u16 val;
+
+	macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]);
+
+	/* PHY is in power down state initially.
+	   Exit power-down state, write 1 to MICR (0x11)
+	*/
+	macb_miiphy_write("macb0", 1, 0x11, 0x01);
+
+	/* Configure LEDs, read and modify PHYCR (0x19)
+	   Left: link, right: activity
+	*/
+	macb_miiphy_read("macb0", 1, 0x19, &val);
+	val |= 1<<5;
+	macb_miiphy_write("macb0", 1, 0x19, val);
+
+	return 0;
+}
+#endif
+
diff --git a/board/indefia/nimbuscloud/nimbuscloud.h b/board/indefia/nimbuscloud/nimbuscloud.h
new file mode 100644
index 0000000..f6a0571
--- /dev/null
+++ b/board/indefia/nimbuscloud/nimbuscloud.h
@@ -0,0 +1,8 @@
+
+#ifdef CONFIG_CMD_NET
+
+extern int macb_miiphy_read(char *devname, u8 phy_adr, u8 reg, u16 *value);
+extern int macb_miiphy_write(char *devname, u8 phy_adr, u8 reg, u16 value);
+
+#endif
+
diff --git a/board/indefia/nimbuscloud/u-boot.lds b/board/indefia/nimbuscloud/u-boot.lds
new file mode 100644
index 0000000..a7243f2
--- /dev/null
+++ b/board/indefia/nimbuscloud/u-boot.lds
@@ -0,0 +1,72 @@
+/* -*- Fundamental -*-
+ *
+ * Copyright (C) 2005-2006 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32")
+OUTPUT_ARCH(avr32)
+ENTRY(_start)
+
+SECTIONS
+{
+	. = 0;
+	_text = .;
+	.text : {
+		*(.exception.text)
+		*(.text)
+		*(.text.*)
+	}
+	_etext = .;
+
+	.rodata : {
+		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+	}
+
+	. = ALIGN(8);
+	_data = .;
+	.data : {
+		*(.data)
+		*(.data.*)
+	}
+
+	. = ALIGN(4);
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : {
+		KEEP(*(.u_boot_cmd))
+	}
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	_got = .;
+	.got : {
+		*(.got)
+	}
+	_egot = .;
+
+	. = ALIGN(8);
+	_edata = .;
+
+	.bss : {
+		*(.bss)
+		*(.bss.*)
+	}
+	. = ALIGN(8);
+	_end = .;
+} 
diff --git a/include/configs/nimbuscloud.h b/include/configs/nimbuscloud.h
new file mode 100644
index 0000000..8a53725
--- /dev/null
+++ b/include/configs/nimbuscloud.h
@@ -0,0 +1,184 @@
+/*
+ * Copyright (C) 2008-2009 Indefia
+ *
+ * Configuration settings for Indefia Nimbus Cloud
+ *
+ * Based on atngw100.h (c) Atmel Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <asm/arch/memory-map.h>
+
+#define CONFIG_AVR32			1
+#define CONFIG_AT32AP			1
+#define CONFIG_AT32AP7000		1
+#define CONFIG_NIMBUSCLOUD		1
+
+#define CONFIG_SYS_HZ				1000
+
+/*
+ * Set up the PLL to run at 180 MHz, the CPU to run at the PLL
+ * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
+ * and the PBA bus to run at 1/4 the PLL frequency.
+ */
+#define CONFIG_PLL				1
+#define CONFIG_SYS_POWER_MANAGER		1
+#define CONFIG_SYS_OSC0_HZ			25000000
+#define CONFIG_SYS_PLL0_DIV			5
+#define CONFIG_SYS_PLL0_MUL			36
+#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES		16
+#define CONFIG_SYS_CLKDIV_CPU			0
+#define CONFIG_SYS_CLKDIV_HSB			1
+#define CONFIG_SYS_CLKDIV_PBA			2
+#define CONFIG_SYS_CLKDIV_PBB			1
+
+/*
+ * The PLLOPT register controls the PLL like this:
+ *   icp = PLLOPT<2>
+ *   ivco = PLLOPT<1:0>
+ *
+ * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
+ */
+#define CONFIG_SYS_PLL0_OPT			0x05
+
+#define CONFIG_USART1			1
+
+/* User serviceable stuff */
+
+#define CONFIG_DOS_PARTITION		1
+#define CONFIG_CMDLINE_TAG		1
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+
+#define CONFIG_STACKSIZE		(2048)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0 root=/dev/mtdblock4 rootfstype=jffs2 fbmem=1200k"
+#define CONFIG_BOOTCOMMAND						\
+	"cp.b 0x20000 0x90400000 0x180000; bootm 0x90400000"
+
+/*
+ * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
+ * data on the serial line may interrupt the boot sequence.
+ */
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_AUTOBOOT			1
+#define CONFIG_AUTOBOOT_KEYED		1
+#define CONFIG_AUTOBOOT_PROMPT		\
+	"Press SPACE to abort autoboot in %d seconds\n", bootdelay
+#define CONFIG_AUTOBOOT_DELAY_STR	"d"
+#define CONFIG_AUTOBOOT_STOP_STR	" "
+
+#define CONFIG_OVERWRITE_ETHADDR_ONCE	1
+#define CONFIG_NET_MULTI		1
+
+/*
+ * BOOTP/DHCP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ASKENV
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+/* #define CONFIG_CMD_JFFS2 */
+#define CONFIG_CMD_MMC
+/* #define CONFIG_CMD_SF */
+
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_SOURCE
+#undef CONFIG_CMD_XIMG
+
+#define CONFIG_ATMEL_USART		1
+#define CONFIG_MACB			1
+#define CONFIG_PORTMUX_PIO		1
+#define CONFIG_SYS_NR_PIOS		5
+#define CONFIG_SYS_HSDRAMC		1
+#define CONFIG_MMC			1
+#define CONFIG_ATMEL_MCI		1
+
+#define CONFIG_SYS_DCACHE_LINESZ	32
+#define CONFIG_SYS_ICACHE_LINESZ	32
+
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
+
+#define CONFIG_SYS_FLASH_PROTECTION     1
+
+#define CONFIG_SYS_FLASH_BASE		0xa0000000
+#define CONFIG_SYS_FLASH_SIZE		0x200000
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	39
+
+#define CONFIG_SYS_MONITOR_BASE		0x00000000
+
+#define CONFIG_SYS_INTRAM_BASE		INTERNAL_SRAM_BASE
+#define CONFIG_SYS_INTRAM_SIZE		INTERNAL_SRAM_SIZE
+#define CONFIG_SYS_SDRAM_BASE		EBI_SDRAM_BASE
+
+#define CONFIG_ENV_IS_IN_FLASH		1
+#define CONFIG_ENV_SIZE			65536
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + \
+		CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + \
+		CONFIG_SYS_INTRAM_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN		(256*1024)
+#define CONFIG_SYS_DMA_ALLOC_LEN	(16384)
+
+/* Allow 4MB for the kernel run-time image */
+#define CONFIG_SYS_LOAD_ADDR		(EBI_SDRAM_BASE + 0x00400000)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(16 * 1024)
+
+/* Other configuration settings that shouldn't have to change all that often */
+#define CONFIG_SYS_PROMPT		"U-Boot> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+		sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
+
+#define CONFIG_SYS_MEMTEST_START	EBI_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x1f00000)
+
+#define CONFIG_SYS_BAUDRATE_TABLE 	{ 115200, 38400, 19200, 9600, 2400 }
+
+#define CONFIG_CMD_MII			1
+#define CONFIG_MISC_INIT_R		1
+#define CONFIG_SILENT_CONSOLE		1
+#define CONFIG_DISABLE_CONSOLE		1
+#define CONFIG_SYS_DEVICE_NULLDEV	1
+
+
+#endif /* __CONFIG_H */
+