cross-compiling Linux for PowerPC e200 core?

cross-compiling Linux for PowerPC e200 core?

[Németh Márton]

[-- Attachment #1: Type: text/plain, Size: 2574 bytes --]

Hi,

I'm trying to cross-compile Linux 2.6.33 for Freescale MPC5554 [1][2]. This
microcontroller is based on the e200z6 core. I could build the cross-development
tools, but I could miss something because I get an error message when building
Linux for PowerPC e200 core. Here are the steps I used:

$ tar xjvRf binutils-2.20.tar.bz2
$ mkdir binutils-build
$ cd binutils-build
$ ../binutils-2.20/configure --target=powerpc-linux-gnuspe --prefix=/home/nmarci/usr/local
$ make
$ make install
$ cd ..
$ export PATH=$PATH:/home/nmarci/usr/local/binutils/bin
$ tar xjvRf gcc-core-4.4.2.tar.bz2
$ mkdir gcc-build
$ cd gcc-build
$ ../gcc-4.4.2/configure --target=powerpc-linux-gnuspe --prefix=/home/nmarci/usr/local --disable-shared --disable-threads --enable-languages=c
$ make all-gcc
$ make install-gcc
$ cd ..
$ tar xjvRf linux-2.6.33.tar.bz2
$ ln -s linux-2.6.33 linux
$ cd linux
$ make ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnuspe- menuconfig
$ make ARCH=powerpc CROSS_COMPILE=powerpc-linux-gnuspe- vmlinux
  HOSTCC  scripts/basic/fixdep
  HOSTCC  scripts/basic/docproc
  HOSTCC  scripts/basic/hash
  HOSTCC  scripts/kconfig/conf.o
  HOSTCC  scripts/kconfig/kxgettext.o
  HOSTCC  scripts/kconfig/zconf.tab.o
  HOSTLD  scripts/kconfig/conf
scripts/kconfig/conf -s arch/powerpc/Kconfig
  CHK     include/linux/version.h
  CHK     include/generated/utsrelease.h
  CC      kernel/bounds.s
  GEN     include/generated/bounds.h
  CC      arch/powerpc/kernel/asm-offsets.s
  GEN     include/generated/asm-offsets.h
  CALL    scripts/checksyscalls.sh
<stdin>:1523:2: warning: #warning syscall recvmmsg not implemented
  HOSTCC  scripts/dtc/checks.o
  HOSTCC  scripts/dtc/data.o
  HOSTCC  scripts/dtc/dtc-lexer.lex.o
  HOSTCC  scripts/dtc/dtc-parser.tab.o
  HOSTCC  scripts/dtc/dtc.o
  HOSTCC  scripts/dtc/flattree.o
  HOSTCC  scripts/dtc/fstree.o
  HOSTCC  scripts/dtc/livetree.o
  HOSTCC  scripts/dtc/srcpos.o
  HOSTCC  scripts/dtc/treesource.o
  HOSTLD  scripts/dtc/dtc
  CC      scripts/mod/empty.o
Assembler messages:
Error: invalid switch -me200
Error: unrecognized option -me200
make[2]: *** [scripts/mod/empty.o] Error 2
make[1]: *** [scripts/mod] Error 2
make: *** [scripts] Error 2

I attach the kernel .config I used. I guess the assembler I built misses the support
for e200 core. How can enable it?

References:
[1] Freescale MPC5554
    http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC5554

[2] MPC5553/MPC5554 Microcontroller Reference Manual
    http://www.freescale.com/files/32bit/doc/ref_manual/MPC5553_MPC5554_RM.pdf

Regards,

	Márton Németh

[-- Attachment #2: .config --]
[-- Type: text/plain, Size: 15460 bytes --]

#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.33
# Sun Mar  7 07:40:17 2010
#
# CONFIG_PPC64 is not set

#
# Processor support
#
# CONFIG_PPC_BOOK3S_32 is not set
# CONFIG_PPC_85xx is not set
# CONFIG_PPC_8xx is not set
# CONFIG_40x is not set
# CONFIG_44x is not set
CONFIG_E200=y
CONFIG_BOOKE=y
CONFIG_FSL_BOOKE=y
CONFIG_SPE=y
CONFIG_PPC_MMU_NOHASH=y
CONFIG_PPC_MMU_NOHASH_32=y
CONFIG_PPC_BOOK3E_MMU=y
# CONFIG_PPC_MM_SLICES is not set
# CONFIG_SMP is not set
CONFIG_NOT_COHERENT_CACHE=y
CONFIG_PPC32=y
CONFIG_WORD_SIZE=32
# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
CONFIG_MMU=y
CONFIG_GENERIC_CMOS_UPDATE=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_TIME_VSYSCALL=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_GENERIC_HARDIRQS=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
# CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK is not set
CONFIG_IRQ_PER_CPU=y
CONFIG_NR_IRQS=512
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_RWSEM_XCHGADD_ALGORITHM=y
CONFIG_ARCH_HAS_ILOG2_U32=y
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_FIND_NEXT_BIT=y
# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
CONFIG_PPC=y
CONFIG_EARLY_PRINTK=y
CONFIG_GENERIC_NVRAM=y
CONFIG_SCHED_OMIT_FRAME_POINTER=y
CONFIG_ARCH_MAY_HAVE_PC_FDC=y
CONFIG_PPC_OF=y
CONFIG_OF=y
# CONFIG_PPC_UDBG_16550 is not set
# CONFIG_GENERIC_TBSYNC is not set
CONFIG_AUDIT_ARCH=y
CONFIG_GENERIC_BUG=y
CONFIG_DTC=y
# CONFIG_DEFAULT_UIMAGE is not set
CONFIG_ARCH_HIBERNATION_POSSIBLE=y
# CONFIG_PPC_DCR_NATIVE is not set
# CONFIG_PPC_DCR_MMIO is not set
CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
CONFIG_CONSTRUCTORS=y

#
# General setup
#
# CONFIG_EXPERIMENTAL is not set
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
# CONFIG_SWAP is not set
# CONFIG_SYSVIPC is not set
# CONFIG_BSD_PROCESS_ACCT is not set

#
# RCU Subsystem
#
CONFIG_TREE_RCU=y
# CONFIG_TREE_PREEMPT_RCU is not set
# CONFIG_TINY_RCU is not set
# CONFIG_RCU_TRACE is not set
CONFIG_RCU_FANOUT=32
# CONFIG_RCU_FANOUT_EXACT is not set
# CONFIG_TREE_RCU_TRACE is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=17
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
CONFIG_ANON_INODES=y
# CONFIG_EMBEDDED is not set
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_HAVE_PERF_EVENTS=y

#
# Kernel Performance Events And Counters
#
# CONFIG_PERF_EVENTS is not set
# CONFIG_PERF_COUNTERS is not set
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_PCI_QUIRKS=y
CONFIG_SLUB_DEBUG=y
CONFIG_COMPAT_BRK=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
CONFIG_HAVE_IOREMAP_PROT=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_ARCH_TRACEHOOK=y
CONFIG_HAVE_DMA_ATTRS=y
CONFIG_HAVE_DMA_API_DEBUG=y

#
# GCOV-based kernel profiling
#
# CONFIG_SLOW_WORK is not set
# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
CONFIG_BASE_SMALL=0
# CONFIG_MODULES is not set
CONFIG_BLOCK=y
CONFIG_LBDAF=y
CONFIG_BLK_DEV_BSG=y
# CONFIG_BLK_DEV_INTEGRITY is not set

#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
# CONFIG_INLINE_SPIN_TRYLOCK is not set
# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK is not set
# CONFIG_INLINE_SPIN_LOCK_BH is not set
# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
CONFIG_INLINE_SPIN_UNLOCK=y
# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_READ_TRYLOCK is not set
# CONFIG_INLINE_READ_LOCK is not set
# CONFIG_INLINE_READ_LOCK_BH is not set
# CONFIG_INLINE_READ_LOCK_IRQ is not set
# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
CONFIG_INLINE_READ_UNLOCK=y
# CONFIG_INLINE_READ_UNLOCK_BH is not set
CONFIG_INLINE_READ_UNLOCK_IRQ=y
# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
# CONFIG_INLINE_WRITE_TRYLOCK is not set
# CONFIG_INLINE_WRITE_LOCK is not set
# CONFIG_INLINE_WRITE_LOCK_BH is not set
# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
CONFIG_INLINE_WRITE_UNLOCK=y
# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
# CONFIG_MUTEX_SPIN_ON_OWNER is not set
# CONFIG_FREEZER is not set

#
# Platform support
#
# CONFIG_PPC_CELL is not set
# CONFIG_PPC_CELL_NATIVE is not set
# CONFIG_PQ2ADS is not set
# CONFIG_IPIC is not set
# CONFIG_MPIC is not set
# CONFIG_MPIC_WEIRD is not set
# CONFIG_PPC_I8259 is not set
# CONFIG_PPC_RTAS is not set
# CONFIG_MMIO_NVRAM is not set
# CONFIG_PPC_MPC106 is not set
# CONFIG_PPC_970_NAP is not set
# CONFIG_PPC_INDIRECT_IO is not set
# CONFIG_GENERIC_IOMAP is not set
# CONFIG_CPU_FREQ is not set
# CONFIG_FSL_ULI1575 is not set
# CONFIG_SIMPLE_GPIO is not set

#
# Kernel options
#
# CONFIG_HIGHMEM is not set
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
# CONFIG_HZ_100 is not set
CONFIG_HZ_250=y
# CONFIG_HZ_300 is not set
# CONFIG_HZ_1000 is not set
CONFIG_HZ=250
# CONFIG_SCHED_HRTICK is not set
CONFIG_PREEMPT_NONE=y
# CONFIG_PREEMPT_VOLUNTARY is not set
# CONFIG_PREEMPT is not set
CONFIG_BINFMT_ELF=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_HAVE_AOUT is not set
# CONFIG_BINFMT_MISC is not set
# CONFIG_MATH_EMULATION is not set
# CONFIG_IOMMU_HELPER is not set
# CONFIG_SWIOTLB is not set
CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
CONFIG_ARCH_HAS_WALK_MEMORY=y
CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
CONFIG_SPARSE_IRQ=y
CONFIG_MAX_ACTIVE_REGIONS=32
CONFIG_ARCH_FLATMEM_ENABLE=y
CONFIG_ARCH_POPULATES_NODE_MAP=y
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
CONFIG_MIGRATION=y
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
# CONFIG_KSM is not set
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
CONFIG_PPC_4K_PAGES=y
# CONFIG_PPC_16K_PAGES is not set
# CONFIG_PPC_64K_PAGES is not set
# CONFIG_PPC_256K_PAGES is not set
CONFIG_FORCE_MAX_ZONEORDER=11
# CONFIG_PROC_DEVICETREE is not set
# CONFIG_CMDLINE_BOOL is not set
CONFIG_EXTRA_TARGETS=""
# CONFIG_PM is not set
CONFIG_SECCOMP=y
CONFIG_ISA_DMA_API=y

#
# Bus options
#
CONFIG_ZONE_DMA=y
# CONFIG_PPC_INDIRECT_PCI is not set
CONFIG_PCI=y
CONFIG_PCI_DOMAINS=y
CONFIG_PCI_SYSCALL=y
# CONFIG_PCIEPORTBUS is not set
CONFIG_ARCH_SUPPORTS_MSI=y
# CONFIG_PCI_MSI is not set
CONFIG_PCI_LEGACY=y
# CONFIG_PCI_STUB is not set
# CONFIG_PCI_IOV is not set
# CONFIG_PCCARD is not set
# CONFIG_HOTPLUG_PCI is not set
# CONFIG_HAS_RAPIDIO is not set

#
# Advanced setup
#
# CONFIG_ADVANCED_OPTIONS is not set

#
# Default settings for advanced configuration options are used
#
CONFIG_LOWMEM_SIZE=0x30000000
CONFIG_LOWMEM_CAM_NUM=3
CONFIG_PAGE_OFFSET=0xc0000000
CONFIG_KERNEL_START=0xc0000000
CONFIG_PHYSICAL_START=0x00000000
CONFIG_PHYSICAL_ALIGN=0x04000000
CONFIG_TASK_SIZE=0xc0000000
CONFIG_CONSISTENT_SIZE=0x00200000
# CONFIG_NET is not set

#
# Device Drivers
#

#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=y
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_MTD is not set
CONFIG_OF_DEVICE=y
# CONFIG_PARPORT is not set
CONFIG_BLK_DEV=y
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_CPQ_DA is not set
# CONFIG_BLK_CPQ_CISS_DA is not set
# CONFIG_BLK_DEV_DAC960 is not set
# CONFIG_BLK_DEV_COW_COMMON is not set
# CONFIG_BLK_DEV_LOOP is not set

#
# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
#
# CONFIG_BLK_DEV_SX8 is not set
# CONFIG_BLK_DEV_RAM is not set
# CONFIG_CDROM_PKTCDVD is not set
# CONFIG_BLK_DEV_HD is not set
# CONFIG_MISC_DEVICES is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set

#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
# CONFIG_FUSION is not set

#
# IEEE 1394 (FireWire) support
#

#
# You can enable one or both FireWire driver stacks.
#

#
# The newer stack is recommended.
#
# CONFIG_FIREWIRE is not set
# CONFIG_IEEE1394 is not set
# CONFIG_I2O is not set
# CONFIG_MACINTOSH_DRIVERS is not set
# CONFIG_PHONE is not set

#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set

#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set

#
# Input Device Drivers
#
CONFIG_INPUT_KEYBOARD=y
CONFIG_KEYBOARD_ATKBD=y
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_XTKBD is not set
CONFIG_INPUT_MOUSE=y
CONFIG_MOUSE_PS2=y
CONFIG_MOUSE_PS2_ALPS=y
CONFIG_MOUSE_PS2_LOGIPS2PP=y
CONFIG_MOUSE_PS2_SYNAPTICS=y
CONFIG_MOUSE_PS2_TRACKPOINT=y
# CONFIG_MOUSE_PS2_ELANTECH is not set
# CONFIG_MOUSE_PS2_SENTELIC is not set
# CONFIG_MOUSE_PS2_TOUCHKIT is not set
# CONFIG_MOUSE_SERIAL is not set
# CONFIG_MOUSE_VSXXXAA is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set

#
# Hardware I/O ports
#
CONFIG_SERIO=y
CONFIG_SERIO_I8042=y
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_PCIPS2 is not set
CONFIG_SERIO_LIBPS2=y
# CONFIG_SERIO_RAW is not set
# CONFIG_SERIO_XILINX_XPS_PS2 is not set
# CONFIG_SERIO_ALTERA_PS2 is not set
# CONFIG_GAMEPORT is not set

#
# Character devices
#
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
CONFIG_DEVKMEM=y
# CONFIG_SERIAL_NONSTANDARD is not set

#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set

#
# Non-8250 serial port support
#
# CONFIG_SERIAL_UARTLITE is not set
# CONFIG_SERIAL_JSM is not set
# CONFIG_SERIAL_GRLIB_GAISLER_APBUART is not set
CONFIG_UNIX98_PTYS=y
# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
# CONFIG_GEN_RTC is not set
# CONFIG_R3964 is not set
# CONFIG_APPLICOM is not set
# CONFIG_RAW_DRIVER is not set
CONFIG_DEVPORT=y
# CONFIG_I2C is not set
# CONFIG_SPI is not set

#
# PPS support
#
CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
# CONFIG_GPIOLIB is not set
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
# CONFIG_WATCHDOG is not set
CONFIG_SSB_POSSIBLE=y

#
# Sonics Silicon Backplane
#
# CONFIG_SSB is not set

#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_REGULATOR is not set
# CONFIG_MEDIA_SUPPORT is not set

#
# Graphics support
#
# CONFIG_AGP is not set
CONFIG_VGA_ARB=y
# CONFIG_DRM is not set
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set

#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set

#
# Console display driver support
#
CONFIG_VGA_CONSOLE=y
# CONFIG_VGACON_SOFT_SCROLLBACK is not set
CONFIG_DUMMY_CONSOLE=y
# CONFIG_SOUND is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
# CONFIG_NEW_LEDS is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_INFINIBAND is not set
# CONFIG_EDAC is not set
# CONFIG_RTC_CLASS is not set
# CONFIG_DMADEVICES is not set
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set

#
# TI VLYNQ
#
# CONFIG_STAGING is not set

#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
CONFIG_FILE_LOCKING=y
# CONFIG_FSNOTIFY is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY is not set
# CONFIG_INOTIFY_USER is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set

#
# Caches
#

#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set

#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set

#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
# CONFIG_PROC_KCORE is not set
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
# CONFIG_MISC_FILESYSTEMS is not set

#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_NLS is not set
# CONFIG_BINARY_PRINTF is not set

#
# Library routines
#
CONFIG_GENERIC_FIND_LAST_BIT=y
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
# CONFIG_CRC32 is not set
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y
CONFIG_HAVE_LMB=y
CONFIG_GENERIC_ATOMIC64=y

#
# Kernel hacking
#
CONFIG_PRINTK_TIME=y
CONFIG_ENABLE_WARN_DEPRECATED=y
CONFIG_ENABLE_MUST_CHECK=y
CONFIG_FRAME_WARN=1024
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_STRIP_ASM_SYMS is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_RCU_CPU_STALL_DETECTOR=y
# CONFIG_LATENCYTOP is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
CONFIG_HAVE_FUNCTION_TRACER=y
CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
CONFIG_TRACING_SUPPORT=y
# CONFIG_FTRACE is not set
# CONFIG_DMA_API_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_PPC_DISABLE_WERROR is not set
CONFIG_PPC_WERROR=y
CONFIG_PRINT_STACK_DEPTH=64
# CONFIG_IRQSTACKS is not set
# CONFIG_PPC_EARLY_DEBUG is not set

#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
# CONFIG_DEFAULT_SECURITY_SELINUX is not set
# CONFIG_DEFAULT_SECURITY_SMACK is not set
# CONFIG_DEFAULT_SECURITY_TOMOYO is not set
CONFIG_DEFAULT_SECURITY_DAC=y
CONFIG_DEFAULT_SECURITY=""
# CONFIG_CRYPTO is not set
# CONFIG_PPC_CLOCK is not set
# CONFIG_VIRTUALIZATION is not set

Re: cross-compiling Linux for PowerPC e200 core?

[Grant Likely]

2010/3/6 N=E9meth M=E1rton <nm127@freemail.hu>:
> Hi,
>
> I'm trying to cross-compile Linux 2.6.33 for Freescale MPC5554 [1][2]. Th=
is
> microcontroller is based on the e200z6 core. I could build the cross-deve=
lopment
> tools, but I could miss something because I get an error message when bui=
lding
> Linux for PowerPC e200 core. Here are the steps I used:

I doubt you'll have much luck with the mpc5554.  Linux doesn't include
any support for the MPC5554, and I don't think anybody is working on
it.  Any of the mpc5554 systems I've see don't have enough ram to run
Linux well.

g.

Re: cross-compiling Linux for PowerPC e200 core?

[Segher Boessenkool]

> Assembler messages:
> Error: invalid switch -me200
> Error: unrecognized option -me200

No version of mainline binutils supports this.

This kernel code was added in 2005, in 33d9e9b, by FSL; perhaps
they have a fork of binutils that supports it, maybe they forgot
to submit the changes upstream?


Segher

Re: cross-compiling Linux for PowerPC e200 core?

[Németh Márton]

Grant Likely wrote:
> 2010/3/6 Németh Márton <nm127@freemail.hu>:
>> Hi,
>>
>> I'm trying to cross-compile Linux 2.6.33 for Freescale MPC5554 [1][2]. This
>> microcontroller is based on the e200z6 core. I could build the cross-development
>> tools, but I could miss something because I get an error message when building
>> Linux for PowerPC e200 core. Here are the steps I used:
> 
> I doubt you'll have much luck with the mpc5554.  Linux doesn't include
> any support for the MPC5554, and I don't think anybody is working on
> it.  Any of the mpc5554 systems I've see don't have enough ram to run
> Linux well.

I'm ready to work a bit more than just compiling the kernel and run it on MPC5554.
On my target system there is a possibility to use external RAM connected to the
External Bus Interface, so I don't see this would be a problem in my case.

However, I have not much experience running Linux on PowerPC environment. Could
you suggest a PowerPC port which would be a good starting point to make support
for MPC5554?

As far as I could find out I'll need to create a device tree as documented in
the linux/Documentation/powerpc/booting-without-of.txt file.

Regards,

	Márton Németh

Re: cross-compiling Linux for PowerPC e200 core?

[Németh Márton]

Hi,
Segher Boessenkool wrote:
>> Assembler messages:
>> Error: invalid switch -me200
>> Error: unrecognized option -me200
> 
> No version of mainline binutils supports this.
> 
> This kernel code was added in 2005, in 33d9e9b, by FSL; perhaps
> they have a fork of binutils that supports it, maybe they forgot
> to submit the changes upstream?

I'm a bit new on the topic, could you please describe what FSL means?

I'm also having problems finding the commit 33d9e9b in the git repository
at http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git .

Regards,

	Márton Németh

Re: cross-compiling Linux for PowerPC e200 core?

[Grant Likely]

2010/3/8 N=E9meth M=E1rton <nm127@freemail.hu>:
> Grant Likely wrote:
>> 2010/3/6 N=E9meth M=E1rton <nm127@freemail.hu>:
>>> Hi,
>>>
>>> I'm trying to cross-compile Linux 2.6.33 for Freescale MPC5554 [1][2]. =
This
>>> microcontroller is based on the e200z6 core. I could build the cross-de=
velopment
>>> tools, but I could miss something because I get an error message when b=
uilding
>>> Linux for PowerPC e200 core. Here are the steps I used:
>>
>> I doubt you'll have much luck with the mpc5554. =A0Linux doesn't include
>> any support for the MPC5554, and I don't think anybody is working on
>> it. =A0Any of the mpc5554 systems I've see don't have enough ram to run
>> Linux well.
>
> I'm ready to work a bit more than just compiling the kernel and run it on=
 MPC5554.
> On my target system there is a possibility to use external RAM connected =
to the
> External Bus Interface, so I don't see this would be a problem in my case=
.
>
> However, I have not much experience running Linux on PowerPC environment.=
 Could
> you suggest a PowerPC port which would be a good starting point to make s=
upport
> for MPC5554?

I'd use the MPC5200 board support as a starting point
(arch/powerpc/platforms/52xx).  Create yourself a new directory for
this platform (arch/powerpc/platforms/55xx)

> As far as I could find out I'll need to create a device tree as documente=
d in
> the linux/Documentation/powerpc/booting-without-of.txt file.

Yes, you'll need to create a device tree file for the board.  Again,
start from an existing 5200 .dts file.  You won't need very much in it
to get started.  I'd be happy to help you get the structure right.

g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: cross-compiling Linux for PowerPC e200 core?

[Segher Boessenkool]

>>> Assembler messages:
>>> Error: invalid switch -me200
>>> Error: unrecognized option -me200
>>
>> No version of mainline binutils supports this.
>>
>> This kernel code was added in 2005, in 33d9e9b, by FSL; perhaps
>> they have a fork of binutils that supports it, maybe they forgot
>> to submit the changes upstream?
>
> I'm a bit new on the topic, could you please describe what FSL means?

Freescale

> I'm also having problems finding the commit 33d9e9b in the git repository
> at http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git .

http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=33d9e9b

There is no obvious way to get there via clicking afaics, the "commit"
search box doesn't work at least.  Hrm.


Segher

Re: cross-compiling Linux for PowerPC e200 core?

[Németh Márton]

Hi,
Grant Likely wrote:
> 2010/3/8 Németh Márton <nm127@freemail.hu>:
>> Grant Likely wrote:
>>> 2010/3/6 Németh Márton <nm127@freemail.hu>:
>>>> Hi,
>>>>
>>>> I'm trying to cross-compile Linux 2.6.33 for Freescale MPC5554 [1][2]. This
>>>> microcontroller is based on the e200z6 core. I could build the cross-development
>>>> tools, but I could miss something because I get an error message when building
>>>> Linux for PowerPC e200 core. Here are the steps I used:
>>> I doubt you'll have much luck with the mpc5554.  Linux doesn't include
>>> any support for the MPC5554, and I don't think anybody is working on
>>> it.  Any of the mpc5554 systems I've see don't have enough ram to run
>>> Linux well.
>> I'm ready to work a bit more than just compiling the kernel and run it on MPC5554.
>> On my target system there is a possibility to use external RAM connected to the
>> External Bus Interface, so I don't see this would be a problem in my case.
>>
>> However, I have not much experience running Linux on PowerPC environment. Could
>> you suggest a PowerPC port which would be a good starting point to make support
>> for MPC5554?
> 
> I'd use the MPC5200 board support as a starting point
> (arch/powerpc/platforms/52xx).  Create yourself a new directory for
> this platform (arch/powerpc/platforms/55xx)
> 
>> As far as I could find out I'll need to create a device tree as documented in
>> the linux/Documentation/powerpc/booting-without-of.txt file.
> 
> Yes, you'll need to create a device tree file for the board.  Again,
> start from an existing 5200 .dts file.  You won't need very much in it
> to get started.  I'd be happy to help you get the structure right.

I tried to create a first draft of the deveice tree for MPC5554. It is
compilable with dtc. I based this .dts file on Figure 1-1 on page 1-3 and
Table 1-2 on page 1-21 of http://www.freescale.com/files/32bit/doc/ref_manual/MPC5553_MPC5554_RM.pdf .

I'm not sure about the following points:
1. Where should be the on-chip FLASH described? This memory is read-only from
   view of software and can be used to store read-only data or execute code directly
   from there.

2. Should the co-processor (eTPU in this case) also listed in section "cpus"
   or not? This co-processor is not able to run code like the e200z6.

3. There are three on-chip buses on MPC5554:
   - Crossbar Switch (XBAR)
   - Peripheral Bridge A (PBRIDGE_A)
   - Peripheral Bridge B (PBRIDGE_B)
   I used PBRIDGE_A and PRIDGE_B to create two /soc<SOCname> entries. Is this possible?

4. There are modules which have multiple instances at different base addresses. These
   are DSPI, SCI and FlexCAN. I used the same name for them but with different addresses.
   Is this correct?

Regards,

	Márton Németh
---
From: Márton Németh <nm127@freemail.hu>

Add device tree for Freescale MPC5554.

Signed-off-by: Márton Németh <nm127@freemail.hu>
---
diff -uprN linux-2.6.33.orig/arch/powerpc/boot/dts/mpc5554.dts linux/arch/powerpc/boot/dts/mpc5554.dts
--- linux-2.6.33.orig/arch/powerpc/boot/dts/mpc5554.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux/arch/powerpc/boot/dts/mpc5554.dts	2010-03-09 07:40:46.000000000 +0100
@@ -0,0 +1,197 @@
+/*
+ * Freescale MPC5554 Device Tree Source
+ *
+ * Based on MPC5553/5554 Microcontroller Reference Manual, Rev. 4.0, 04/2007
+ * http://www.freescale.com/files/32bit/doc/ref_manual/MPC5553_MPC5554_RM.pdf
+ *
+ * Copyright 2010 Márton Németh
+ * Márton Németh <nm127@freemail.hu>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "MPC5554";
+	compatible = "MPC5554";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,5554@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;	// L1, 32KiB
+			i-cache-size = <0x8000>;	// L1, 32KiB
+			timebase-frequency = <0>;	// from bootloader
+			bus-frequency = <0>;		// from bootloader
+			clock-frequency = <0>;		// from bootloader
+		};
+	};
+
+	flash {	// read-only FLASH
+		device_type = "memory";
+		reg = <0x00000000 0x200000>;	// 2MiB internal FLASH
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x40000000 0x10000>;	// 32KiB internal SRAM
+	};
+
+	soc5554BridgeA@c0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc5554-bridgea";
+		ranges = <0 0xc0000000 0x20000000>;
+		reg = <0xc0000000 0x20000000>;
+		bus-frequency = <0>;		// from bootloader
+		system-frequency = <0>;		// from bootloader
+
+		bridgea@3f00000 {
+			compatible = "fsl,mpc5554-bridgea";
+			reg = <0x03f00000 0x4000>;
+		};
+
+		fmpll@3f80000 {		// Frequency Modulated PLL
+			compatible = "fsl,mpc5554-fmpll";
+			reg = <0x03f80000 0x4000>;
+		};
+
+		flashconfig@3f88000 {	// Flash Configuration
+			compatible = "fsl,mpc5554-flashconfig";
+			reg = <0x03f88000 0x4000>;
+		};
+
+		siu@3f89000 {		// System Integration Unit
+			compatible = "fsl,mpc5554-siu";
+			reg = <0x03f90000 0x4000>;
+		};
+
+		emios@3fa0000 {		// Modular Timer System
+			compatible = "fsl,mpc5554-emios";
+			reg = <0x03fa0000 0x4000>;
+		};
+
+		etpu@3fc0000 {		// Enhanced Time Processing Unit
+			compatible = "fsl,mpc5554-etpu";
+			reg = <0x03fc0000 0x4000>;
+		};
+
+		etpudata@3fc8000 {	// eTPU Shared Data Memory (Parameter RAM)
+			compatible = "fsl,mpc5554-etpudata";
+			reg = <0x03fc8000 0x4000>;
+		};
+
+		etpudata@3fcc000 {	// eTPU Shared Data Memory (Parameter RAM) mirror
+			compatible = "fsl,mpc5554-etpudata";
+			reg = <0x03fcc000 0x4000>;
+		};
+
+		etpucode@3fd0000 {		// eTPU Shared Code RAM
+			compatible = "fsl,mpc5554-etpucode";
+			reg = <0x03fd0000 0x4000>;
+		};
+	};
+
+	soc5554BridgeB@e0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc5554-bridgeb";
+		ranges = <0 0xe0000000 0x20000000>;
+		reg = <0xe0000000 0x20000000>;
+		bus-frequency = <0>;		// from bootloader
+		system-frequency = <0>;		// from bootloader
+
+		bridgeb@1ff00000 {
+			compatible = "fsl,mpc5554-bridgeb";
+			reg = <0x1ff00000 0x4000>;
+		};
+
+		xbar@1ff04000 {		// System Bus Crossbar Switch (XBAR)
+			compatible = "fsl,mpc5554-xbar";
+			reg = <0x1ff04000 0x4000>;
+		};
+
+		ecsm@1ff40000 {		// Error Correction Status Module (ECSM)
+			compatible = "fsl,mpc5554-ecsm";
+			reg = <0x1ff40000 0x4000>;
+		};
+
+		edma@1ff44000 {		// Enhanced DMA Controller (eDMA)
+			compatible = "fsl,mpc5554-edma";
+			reg = <0x1ff44000 0x4000>;
+		};
+
+		intc@1ff48000 {		// Interrupt Controller (INTC)
+			compatible = "fsl,mpc5554-intc";
+			reg = <0x1ff48000 0x4000>;
+		};
+
+		eqadc@1ff80000 {	// Enhanced Queued Analog-to-Digital Converter (eQADC)
+			compatible = "fsl,mpc5554-eqacd";
+			reg = <0x1ff80000 0x4000>;
+		};
+
+		dspi@1ff90000 {		// Deserial Serial Peripheral Interface (DSPI_A)
+			compatible = "fsl,mpc5554-dspi";
+			reg = <0x1ff90000 0x4000>;
+		};
+
+		dspi@1ff94000 {		// Deserial Serial Peripheral Interface (DSPI_B)
+			compatible = "fsl,mpc5554-dspi";
+			reg = <0x1ff94000 0x4000>;
+		};
+
+		dspi@1ff98000 {		// Deserial Serial Peripheral Interface (DSPI_C)
+			compatible = "fsl,mpc5554-dspi";
+			reg = <0x1ff98000 0x4000>;
+		};
+
+		dspi@1ff9c000 {		// Deserial Serial Peripheral Interface (DSPI_D)
+			compatible = "fsl,mpc5554-dspi";
+			reg = <0x1ff9c000 0x4000>;
+		};
+
+		sci@1ffb0000 {		// Serial Communications Interface (SCI_A)
+			compatible = "fsl,mpc5554-sci";
+			reg = <0x1ffb0000 0x4000>;
+		};
+
+		sci@1ffb4000 {		// Serial Communications Interface (SCI_A)
+			compatible = "fsl,mpc5554-sci";
+			reg = <0x1ffb4000 0x4000>;
+		};
+
+		can@1ffc0000 {		// Controller Area Network (FlexCAN_A)
+			compatible = "fsl,mpc5554-flexcan";
+			reg = <0x1ffc0000 0x4000>;
+		};
+
+		can@1ffc4000 {		// Controller Area Network (FlexCAN_B)
+			compatible = "fsl,mpc5554-flexcan";
+			reg = <0x1ffc4000 0x4000>;
+		};
+
+		can@1ffc8000 {		// Controller Area Network (FlexCAN_C)
+			compatible = "fsl,mpc5554-flexcan";
+			reg = <0x1ffc8000 0x4000>;
+		};
+
+		bam@1fffc000 {		// Boot Assist Module (BAM)
+			compatible = "fsl,mpc5554-bam";
+			reg = <0x1fffc000 0x4000>;
+		};
+
+	};
+
+};

Re: cross-compiling Linux for PowerPC e200 core?

[Grant Likely]

2010/3/9 N=E9meth M=E1rton <nm127@freemail.hu>:
> Hi,
> Grant Likely wrote:
>> 2010/3/8 N=E9meth M=E1rton <nm127@freemail.hu>:
>>> Grant Likely wrote:
>>>> 2010/3/6 N=E9meth M=E1rton <nm127@freemail.hu>:
>>>>> Hi,
>>>>>
>>>>> I'm trying to cross-compile Linux 2.6.33 for Freescale MPC5554 [1][2]=
. This
>>>>> microcontroller is based on the e200z6 core. I could build the cross-=
development
>>>>> tools, but I could miss something because I get an error message when=
 building
>>>>> Linux for PowerPC e200 core. Here are the steps I used:
>>>> I doubt you'll have much luck with the mpc5554. =A0Linux doesn't inclu=
de
>>>> any support for the MPC5554, and I don't think anybody is working on
>>>> it. =A0Any of the mpc5554 systems I've see don't have enough ram to ru=
n
>>>> Linux well.
>>> I'm ready to work a bit more than just compiling the kernel and run it =
on MPC5554.
>>> On my target system there is a possibility to use external RAM connecte=
d to the
>>> External Bus Interface, so I don't see this would be a problem in my ca=
se.
>>>
>>> However, I have not much experience running Linux on PowerPC environmen=
t. Could
>>> you suggest a PowerPC port which would be a good starting point to make=
 support
>>> for MPC5554?
>>
>> I'd use the MPC5200 board support as a starting point
>> (arch/powerpc/platforms/52xx). =A0Create yourself a new directory for
>> this platform (arch/powerpc/platforms/55xx)
>>
>>> As far as I could find out I'll need to create a device tree as documen=
ted in
>>> the linux/Documentation/powerpc/booting-without-of.txt file.
>>
>> Yes, you'll need to create a device tree file for the board. =A0Again,
>> start from an existing 5200 .dts file. =A0You won't need very much in it
>> to get started. =A0I'd be happy to help you get the structure right.
>
> I tried to create a first draft of the deveice tree for MPC5554. It is
> compilable with dtc. I based this .dts file on Figure 1-1 on page 1-3 and
> Table 1-2 on page 1-21 of http://www.freescale.com/files/32bit/doc/ref_ma=
nual/MPC5553_MPC5554_RM.pdf .
>
> I'm not sure about the following points:
> 1. Where should be the on-chip FLASH described? This memory is read-only =
from
> =A0 view of software and can be used to store read-only data or execute c=
ode directly
> =A0 from there.

Hang it off the xbar node.  Name it flash@<address>, and use
'compatible =3D "fsl,mpc5554-flash";'

>
> 2. Should the co-processor (eTPU in this case) also listed in section "cp=
us"
> =A0 or not? This co-processor is not able to run code like the e200z6.

No, this is a device.  Hang it off the peripheral bridge a node.

> 3. There are three on-chip buses on MPC5554:
> =A0 - Crossbar Switch (XBAR)
> =A0 - Peripheral Bridge A (PBRIDGE_A)
> =A0 - Peripheral Bridge B (PBRIDGE_B)
> =A0 I used PBRIDGE_A and PRIDGE_B to create two /soc<SOCname> entries. Is=
 this possible?

the soc5200 naming was poorly chosen when the 5200 device tree was
written.  Use something like this:

xbar@<control-regs-base-address> {
        compatible =3D "fsl,mpc5554-xbar";
        #address-cells =3D <1>;
        #size-cells =3D <1>;
        ranges =3D <[put the translation ranges in here]>;
        reg =3D <address and size of xbar control registers>;

        bridge@<bridgea-base-address> {
                compatible =3D "fsl,mpc5554-pbridge-a";
                #address-cells =3D <1>;
                #size-cells =3D <1>;
                ranges =3D <[put the translation ranges in here]>;
                reg =3D <address and size of bridge control registers>;
                [... child device nodes ...]
        };
        bridge@<bridgea-base-address> {
                compatible =3D "fsl,mpc5554-pbridge-b";
                #address-cells =3D <1>;
                #size-cells =3D <1>;
                ranges =3D <[put the translation ranges in here]>;
                reg =3D <address and size of bridge control registers>;
                [... child device nodes ...]
        };
};

The idea is to use generic names for the node names, and identify
exactly what the device is by using the "compatible" property.  Also,
the aim is to build up a tree describing the interconnection of device
from the perspective of the OS on the CPU.  ie.  the full physical
address space is represented by the root node of the tree, and
everything else hangs off that.

> 4. There are modules which have multiple instances at different base addr=
esses. These
> =A0 are DSPI, SCI and FlexCAN. I used the same name for them but with dif=
ferent addresses.
> =A0 Is this correct?

yes.

> +/ {
> + =A0 =A0 =A0 model =3D "MPC5554";
> + =A0 =A0 =A0 compatible =3D "MPC5554";

Use the board name here in the form "<manufacturer>,<board>", not the SoC n=
ame.

> + =A0 =A0 =A0 #address-cells =3D <1>;
> + =A0 =A0 =A0 #size-cells =3D <1>;
> +
> + =A0 =A0 =A0 cpus {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 #address-cells =3D <1>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 #size-cells =3D <0>;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 PowerPC,5554@0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 device_type =3D "cpu";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 d-cache-line-size =3D <32>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 i-cache-line-size =3D <32>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 d-cache-size =3D <0x8000>; =
=A0 =A0 =A0 =A0// L1, 32KiB
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 i-cache-size =3D <0x8000>; =
=A0 =A0 =A0 =A0// L1, 32KiB
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 timebase-frequency =3D <0>;=
 =A0 =A0 =A0 // from bootloader
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 bus-frequency =3D <0>; =A0 =
=A0 =A0 =A0 =A0 =A0// from bootloader
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 clock-frequency =3D <0>; =
=A0 =A0 =A0 =A0 =A0// from bootloader
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> + =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 flash { // read-only FLASH

flash@0

> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 device_type =3D "memory";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x00000000 0x200000>; =A0 =A0// 2M=
iB internal FLASH
> + =A0 =A0 =A0 };

remove device_type from this node.  Only a few special nodes should
have device_type.  Make the flash node a child of the xbar node.

> +
> + =A0 =A0 =A0 memory {

memory@400000000

> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 device_type =3D "memory";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x40000000 0x10000>; =A0 =A0 // 32=
KiB internal SRAM
> + =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 soc5554BridgeA@c0000000 {

bridge@c0000000

Make this node a child of the xbar node.

> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 #address-cells =3D <1>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 #size-cells =3D <1>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554-bridgea";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 ranges =3D <0 0xc0000000 0x20000000>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0xc0000000 0x20000000>;

The reg property here should only cover the bridge's control register.
 Not the whole range of the bridge.

> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 bus-frequency =3D <0>; =A0 =A0 =A0 =A0 =A0 =
=A0// from bootloader
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 system-frequency =3D <0>; =A0 =A0 =A0 =A0 /=
/ from bootloader
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 bridgea@3f00000 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-bridgea";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x03f00000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 fmpll@3f80000 { =A0 =A0 =A0 =A0 // Frequenc=
y Modulated PLL
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-fmpll";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x03f80000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 flashconfig@3f88000 { =A0 // Flash Configur=
ation
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-flashconfig";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x03f88000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 siu@3f89000 { =A0 =A0 =A0 =A0 =A0 // System=
 Integration Unit
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-siu";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x03f90000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 emios@3fa0000 { =A0 =A0 =A0 =A0 // Modular =
Timer System
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-emios";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x03fa0000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 etpu@3fc0000 { =A0 =A0 =A0 =A0 =A0// Enhanc=
ed Time Processing Unit
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-etpu";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x03fc0000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 etpudata@3fc8000 { =A0 =A0 =A0// eTPU Share=
d Data Memory (Parameter RAM)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-etpudata";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x03fc8000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 etpudata@3fcc000 { =A0 =A0 =A0// eTPU Share=
d Data Memory (Parameter RAM) mirror
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-etpudata";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x03fcc000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 etpucode@3fd0000 { =A0 =A0 =A0 =A0 =A0 =A0 =
=A0// eTPU Shared Code RAM
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-etpucode";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x03fd0000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> + =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 soc5554BridgeB@e0000000 {

bridge@e0000000

> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 #address-cells =3D <1>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 #size-cells =3D <1>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554-bridgeb";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 ranges =3D <0 0xe0000000 0x20000000>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0xe0000000 0x20000000>;

ditto on comment from bridge a

> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 bus-frequency =3D <0>; =A0 =A0 =A0 =A0 =A0 =
=A0// from bootloader
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 system-frequency =3D <0>; =A0 =A0 =A0 =A0 /=
/ from bootloader
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 bridgeb@1ff00000 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-bridgeb";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1ff00000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 xbar@1ff04000 { =A0 =A0 =A0 =A0 // System B=
us Crossbar Switch (XBAR)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-xbar";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1ff04000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };

The block diagram seems to suggest that the xbar should be the root of
the tree, and the peripheral bridges should be children of it.

> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 ecsm@1ff40000 { =A0 =A0 =A0 =A0 // Error Co=
rrection Status Module (ECSM)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-ecsm";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1ff40000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 edma@1ff44000 { =A0 =A0 =A0 =A0 // Enhanced=
 DMA Controller (eDMA)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-edma";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1ff44000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 intc@1ff48000 { =A0 =A0 =A0 =A0 // Interrup=
t Controller (INTC)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-intc";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1ff48000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 eqadc@1ff80000 { =A0 =A0 =A0 =A0// Enhanced=
 Queued Analog-to-Digital Converter (eQADC)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-eqacd";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1ff80000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 dspi@1ff90000 { =A0 =A0 =A0 =A0 // Deserial=
 Serial Peripheral Interface (DSPI_A)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-dspi";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1ff90000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 dspi@1ff94000 { =A0 =A0 =A0 =A0 // Deserial=
 Serial Peripheral Interface (DSPI_B)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-dspi";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1ff94000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 dspi@1ff98000 { =A0 =A0 =A0 =A0 // Deserial=
 Serial Peripheral Interface (DSPI_C)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-dspi";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1ff98000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 dspi@1ff9c000 { =A0 =A0 =A0 =A0 // Deserial=
 Serial Peripheral Interface (DSPI_D)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-dspi";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1ff9c000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 sci@1ffb0000 { =A0 =A0 =A0 =A0 =A0// Serial=
 Communications Interface (SCI_A)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-sci";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1ffb0000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 sci@1ffb4000 { =A0 =A0 =A0 =A0 =A0// Serial=
 Communications Interface (SCI_A)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-sci";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1ffb4000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 can@1ffc0000 { =A0 =A0 =A0 =A0 =A0// Contro=
ller Area Network (FlexCAN_A)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-flexcan";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1ffc0000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 can@1ffc4000 { =A0 =A0 =A0 =A0 =A0// Contro=
ller Area Network (FlexCAN_B)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-flexcan";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1ffc4000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 can@1ffc8000 { =A0 =A0 =A0 =A0 =A0// Contro=
ller Area Network (FlexCAN_C)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-flexcan";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1ffc8000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 bam@1fffc000 { =A0 =A0 =A0 =A0 =A0// Boot A=
ssist Module (BAM)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-bam";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x1fffc000 0x4000>=
;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 };
> +
> +};
>
>



--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: cross-compiling Linux for PowerPC e200 core?

[Detlev Zundel]

Hi Segher,

> http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=33d9e9b
>
> There is no obvious way to get there via clicking afaics, the "commit"
> search box doesn't work at least.  Hrm.

It works, but not like one would expect, i.e. check out the help:

http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=search_help

Last I checked the gitweb code, there was no easy way other than what
you did by manipulating the URL directly.

Cheers
  Detlev

--
DENX Software Engineering GmbH,      MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,  Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu@denx.de

Re: Freescale MPC5554 device tree (was: cross-compiling Linux for PowerPC e200 core?)

[Németh Márton]

Grant Likely wrote:
> 2010/3/9 Németh Márton <nm127@freemail.hu>:
>> Hi,
>> Grant Likely wrote:
>>> 2010/3/8 Németh Márton <nm127@freemail.hu>:
[snip]
>>>> As far as I could find out I'll need to create a device tree as documented in
>>>> the linux/Documentation/powerpc/booting-without-of.txt file.
>>> Yes, you'll need to create a device tree file for the board.  Again,
>>> start from an existing 5200 .dts file.  You won't need very much in it
>>> to get started.  I'd be happy to help you get the structure right.
>> I tried to create a first draft of the deveice tree for MPC5554. It is
>> compilable with dtc. I based this .dts file on Figure 1-1 on page 1-3 and
>> Table 1-2 on page 1-21 of http://www.freescale.com/files/32bit/doc/ref_manual/MPC5553_MPC5554_RM.pdf .
>>
>> I'm not sure about the following points:
>> 1. Where should be the on-chip FLASH described? This memory is read-only from
>>   view of software and can be used to store read-only data or execute code directly
>>   from there.
> 
> Hang it off the xbar node.  Name it flash@<address>, and use
> 'compatible = "fsl,mpc5554-flash";'
> 
>> 2. Should the co-processor (eTPU in this case) also listed in section "cpus"
>>   or not? This co-processor is not able to run code like the e200z6.
> 
> No, this is a device.  Hang it off the peripheral bridge a node.
> 
>> 3. There are three on-chip buses on MPC5554:
>>   - Crossbar Switch (XBAR)
>>   - Peripheral Bridge A (PBRIDGE_A)
>>   - Peripheral Bridge B (PBRIDGE_B)
>>   I used PBRIDGE_A and PRIDGE_B to create two /soc<SOCname> entries. Is this possible?
> 
> the soc5200 naming was poorly chosen when the 5200 device tree was
> written.  Use something like this:
> 
> xbar@<control-regs-base-address> {
>         compatible = "fsl,mpc5554-xbar";
>         #address-cells = <1>;
>         #size-cells = <1>;
>         ranges = <[put the translation ranges in here]>;
>         reg = <address and size of xbar control registers>;
> 
>         bridge@<bridgea-base-address> {
>                 compatible = "fsl,mpc5554-pbridge-a";
>                 #address-cells = <1>;
>                 #size-cells = <1>;
>                 ranges = <[put the translation ranges in here]>;
>                 reg = <address and size of bridge control registers>;
>                 [... child device nodes ...]
>         };
>         bridge@<bridgea-base-address> {
>                 compatible = "fsl,mpc5554-pbridge-b";
>                 #address-cells = <1>;
>                 #size-cells = <1>;
>                 ranges = <[put the translation ranges in here]>;
>                 reg = <address and size of bridge control registers>;
>                 [... child device nodes ...]
>         };
> };
> 
> The idea is to use generic names for the node names, and identify
> exactly what the device is by using the "compatible" property.  Also,
> the aim is to build up a tree describing the interconnection of device
> from the perspective of the OS on the CPU.  ie.  the full physical
> address space is represented by the root node of the tree, and
> everything else hangs off that.
> 
>> 4. There are modules which have multiple instances at different base addresses. These
>>   are DSPI, SCI and FlexCAN. I used the same name for them but with different addresses.
>>   Is this correct?
> 
> yes.
[snip]

Here is the next draft version of the Freescale MPC5554 device tree.

I'm not quite sure whether the memory@40000000 should go under xbar or stay
directly under the root node.

The second problem I faced with was that XBAR covers the whole address range.
However, if I specify "ranges = <0 0x00000000 0x100000000>;" then I get an
error message because of the too big length value:

| DTC: dts->dts  on file "/usr/src/linux/arch/powerpc/boot/dts/mpc5554.dts"
| /usr/src/linux/arch/powerpc/boot/dts/mpc5554.dts:51 literal out of range
| FATAL ERROR: Syntax error parsing input tree

I tried to solve this problem by assuming that leaving out the "ranges = ..."
means the whole range. Is this correct?

Regards,

	Márton Németh
---
From: Márton Németh <nm127@freemail.hu>

Add device tree for Freescale MPC5554.

Signed-off-by: Márton Németh <nm127@freemail.hu>
---
diff -uprN linux-2.6.33.orig/arch/powerpc/boot/dts/mpc5554.dts linux/arch/powerpc/boot/dts/mpc5554.dts
--- linux-2.6.33.orig/arch/powerpc/boot/dts/mpc5554.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux/arch/powerpc/boot/dts/mpc5554.dts	2010-03-11 07:01:29.000000000 +0100
@@ -0,0 +1,188 @@
+/*
+ * Freescale MPC5554 Device Tree Source
+ *
+ * Based on MPC5553/5554 Microcontroller Reference Manual, Rev. 4.0, 04/2007
+ * http://www.freescale.com/files/32bit/doc/ref_manual/MPC5553_MPC5554_RM.pdf
+ *
+ * Copyright 2010 Márton Németh
+ * Márton Németh <nm127@freemail.hu>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "MPC5554";
+	compatible = "fsl,MPC5554EVB";		// Freescale MPC5554 Evaluation Board
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		PowerPC,5554@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;	// L1, 32KiB
+			i-cache-size = <0x8000>;	// L1, 32KiB
+			timebase-frequency = <0>;	// from bootloader
+			bus-frequency = <0>;		// from bootloader
+			clock-frequency = <0>;		// from bootloader
+		};
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000>;	// 32KiB internal SRAM
+	};
+
+	xbar@1ff04000 {		// System Bus Crossbar Switch (XBAR)
+		compatible = "fsl,mpc5554-xbar";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		// The full memory range is covered by XBAR
+//		ranges = <0 0x00000000 0x100000000>;
+		reg = <0xfff04000 0x4000>;
+
+		flash@00000000 {	// read-only FLASH
+			compatible = "fsl,mpc5554-flash";
+			reg = <0x00000000 0x200000>;	// 2MiB internal FLASH
+		};
+
+		bridge@c0000000 {
+			compatible = "fsl,mpc5554-pbridge-a";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0xc0000000 0x20000000>;
+			reg = <0xc3f00000 0x4000>;
+
+			fmpll@3f80000 {		// Frequency Modulated PLL
+				compatible = "fsl,mpc5554-fmpll";
+				reg = <0x03f80000 0x4000>;
+			};
+
+			flashconfig@3f88000 {	// Flash Configuration
+				compatible = "fsl,mpc5554-flashconfig";
+				reg = <0x03f88000 0x4000>;
+			};
+
+			siu@3f89000 {		// System Integration Unit
+				compatible = "fsl,mpc5554-siu";
+				reg = <0x03f90000 0x4000>;
+			};
+
+			emios@3fa0000 {		// Modular Timer System
+				compatible = "fsl,mpc5554-emios";
+				reg = <0x03fa0000 0x4000>;
+			};
+
+			etpu@3fc0000 {		// Enhanced Time Processing Unit
+				compatible = "fsl,mpc5554-etpu";
+				reg = <0x03fc0000 0x4000>;
+			};
+
+			etpudata@3fc8000 {	// eTPU Shared Data Memory (Parameter RAM)
+				compatible = "fsl,mpc5554-etpudata";
+				reg = <0x03fc8000 0x4000>;
+			};
+
+			etpudata@3fcc000 {	// eTPU Shared Data Memory (Parameter RAM) mirror
+				compatible = "fsl,mpc5554-etpudata";
+				reg = <0x03fcc000 0x4000>;
+			};
+
+			etpucode@3fd0000 {		// eTPU Shared Code RAM
+				compatible = "fsl,mpc5554-etpucode";
+				reg = <0x03fd0000 0x4000>;
+			};
+		};
+
+		bridge@e0000000 {
+			compatible = "fsl,mpc5554-pbridge-b";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0xe0000000 0x20000000>;
+			reg = <0xfff00000 0x4000>;
+
+			ecsm@1ff40000 {		// Error Correction Status Module (ECSM)
+				compatible = "fsl,mpc5554-ecsm";
+				reg = <0x1ff40000 0x4000>;
+			};
+
+			edma@1ff44000 {		// Enhanced DMA Controller (eDMA)
+				compatible = "fsl,mpc5554-edma";
+				reg = <0x1ff44000 0x4000>;
+			};
+
+			intc@1ff48000 {		// Interrupt Controller (INTC)
+				compatible = "fsl,mpc5554-intc";
+				reg = <0x1ff48000 0x4000>;
+			};
+
+			eqadc@1ff80000 {	// Enhanced Queued Analog-to-Digital Converter (eQADC)
+				compatible = "fsl,mpc5554-eqacd";
+				reg = <0x1ff80000 0x4000>;
+			};
+
+			dspi@1ff90000 {		// Deserial Serial Peripheral Interface (DSPI_A)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0x1ff90000 0x4000>;
+			};
+
+			dspi@1ff94000 {		// Deserial Serial Peripheral Interface (DSPI_B)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0x1ff94000 0x4000>;
+			};
+
+			dspi@1ff98000 {		// Deserial Serial Peripheral Interface (DSPI_C)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0x1ff98000 0x4000>;
+			};
+
+			dspi@1ff9c000 {		// Deserial Serial Peripheral Interface (DSPI_D)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0x1ff9c000 0x4000>;
+			};
+
+			sci@1ffb0000 {		// Serial Communications Interface (SCI_A)
+				compatible = "fsl,mpc5554-sci";
+				reg = <0x1ffb0000 0x4000>;
+			};
+
+			sci@1ffb4000 {		// Serial Communications Interface (SCI_A)
+				compatible = "fsl,mpc5554-sci";
+				reg = <0x1ffb4000 0x4000>;
+			};
+
+			can@1ffc0000 {		// Controller Area Network (FlexCAN_A)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0x1ffc0000 0x4000>;
+			};
+
+			can@1ffc4000 {		// Controller Area Network (FlexCAN_B)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0x1ffc4000 0x4000>;
+			};
+
+			can@1ffc8000 {		// Controller Area Network (FlexCAN_C)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0x1ffc8000 0x4000>;
+			};
+
+			bam@1fffc000 {		// Boot Assist Module (BAM)
+				compatible = "fsl,mpc5554-bam";
+				reg = <0x1fffc000 0x4000>;
+			};
+
+		};
+
+	};
+
+};

Re: Freescale MPC5554 device tree (was: cross-compiling Linux for PowerPC e200 core?)

[David Gibson]

On Thu, Mar 11, 2010 at 07:11:56AM +0100, Németh Márton wrote:
[snip]
> +/dts-v1/;
> +
> +/ {
> +	model = "MPC5554";
> +	compatible = "fsl,MPC5554EVB";		// Freescale MPC5554 Evaluation Board
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		PowerPC,5554@0 {

Modern best practice is to have the cpu nodes named just "cpu@XXX",
and put the PowerPC,NNNN into the compatible property.

> +			device_type = "cpu";
> +			reg = <0>;
> +			d-cache-line-size = <32>;
> +			i-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;	// L1, 32KiB
> +			i-cache-size = <0x8000>;	// L1, 32KiB
> +			timebase-frequency = <0>;	// from bootloader
> +			bus-frequency = <0>;		// from bootloader
> +			clock-frequency = <0>;		// from bootloader
> +		};
> +	};
> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		reg = <0x40000000 0x10000>;	// 32KiB internal SRAM
> +	};
> +
> +	xbar@1ff04000 {		// System Bus Crossbar Switch (XBAR)
> +		compatible = "fsl,mpc5554-xbar";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		// The full memory range is covered by XBAR
> +//		ranges = <0 0x00000000 0x100000000>;

If you want all addresses to be translated by the bus you need an
empty ranges property, not *no* ranges property.  No ranges property
indicates that addresses cannot be directly translated across the
bridge, which is not, I think, what you intend.

> +		reg = <0xfff04000 0x4000>;

The unit address '@1ff04000' does not match your reg property 0xfff04000.

> +
> +		flash@00000000 {	// read-only FLASH

Unit addresses are not 0 padded, so this should be just 'flash@0'.

> +			compatible = "fsl,mpc5554-flash";
> +			reg = <0x00000000 0x200000>;	// 2MiB internal FLASH
> +		};
> +
> +		bridge@c0000000 {
> +			compatible = "fsl,mpc5554-pbridge-a";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0xc0000000 0x20000000>;
> +			reg = <0xc3f00000 0x4000>;

The unit address is based on 'reg' (if present) not ranges, so it
should be bridge@c3f00000.  Likewise for the other bridge below.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: Freescale MPC5554 device tree (was: cross-compiling Linux for PowerPC e200 core?)

[Németh Márton]

Hi,

thank you for the comments, I reworked the Freescale MPC5554 device tree
accordingly. I'm listening for comments on this draft.

Regards,

	Márton Németh

---
From: Márton Németh <nm127@freemail.hu>

Add device tree for Freescale MPC5554.

Signed-off-by: Márton Németh <nm127@freemail.hu>
---
diff -uprN linux-2.6.33.orig/arch/powerpc/boot/dts/mpc5554.dts linux/arch/powerpc/boot/dts/mpc5554.dts
--- linux-2.6.33.orig/arch/powerpc/boot/dts/mpc5554.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux/arch/powerpc/boot/dts/mpc5554.dts	2010-03-12 07:22:37.000000000 +0100
@@ -0,0 +1,189 @@
+/*
+ * Freescale MPC5554 Device Tree Source
+ *
+ * Based on MPC5553/5554 Microcontroller Reference Manual, Rev. 4.0, 04/2007
+ * http://www.freescale.com/files/32bit/doc/ref_manual/MPC5553_MPC5554_RM.pdf
+ *
+ * Copyright 2010 Márton Németh
+ * Márton Németh <nm127@freemail.hu>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "MPC5554";
+	compatible = "fsl,MPC5554EVB";		// Freescale MPC5554 Evaluation Board
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "PowerPC,5554";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;	// L1, 32KiB
+			i-cache-size = <0x8000>;	// L1, 32KiB
+			timebase-frequency = <0>;	// from bootloader
+			bus-frequency = <0>;		// from bootloader
+			clock-frequency = <0>;		// from bootloader
+		};
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000>;	// 32KiB internal SRAM
+	};
+
+	xbar@fff04000 {		// System Bus Crossbar Switch (XBAR)
+		compatible = "fsl,mpc5554-xbar";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		// The full memory range is covered by XBAR
+		ranges = <>;
+		reg = <0xfff04000 0x4000>;
+
+		flash@0 {	// read-only FLASH
+			compatible = "fsl,mpc5554-flash";
+			reg = <0x00000000 0x200000>;	// 2MiB internal FLASH
+		};
+
+		bridge@c3f00000 {
+			compatible = "fsl,mpc5554-pbridge-a";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0xc0000000 0x20000000>;
+			reg = <0xc3f00000 0x4000>;
+
+			fmpll@3f80000 {		// Frequency Modulated PLL
+				compatible = "fsl,mpc5554-fmpll";
+				reg = <0x03f80000 0x4000>;
+			};
+
+			flashconfig@3f88000 {	// Flash Configuration
+				compatible = "fsl,mpc5554-flashconfig";
+				reg = <0x03f88000 0x4000>;
+			};
+
+			siu@3f89000 {		// System Integration Unit
+				compatible = "fsl,mpc5554-siu";
+				reg = <0x03f90000 0x4000>;
+			};
+
+			emios@3fa0000 {		// Modular Timer System
+				compatible = "fsl,mpc5554-emios";
+				reg = <0x03fa0000 0x4000>;
+			};
+
+			etpu@3fc0000 {		// Enhanced Time Processing Unit
+				compatible = "fsl,mpc5554-etpu";
+				reg = <0x03fc0000 0x4000>;
+			};
+
+			etpudata@3fc8000 {	// eTPU Shared Data Memory (Parameter RAM)
+				compatible = "fsl,mpc5554-etpudata";
+				reg = <0x03fc8000 0x4000>;
+			};
+
+			etpudata@3fcc000 {	// eTPU Shared Data Memory (Parameter RAM) mirror
+				compatible = "fsl,mpc5554-etpudata";
+				reg = <0x03fcc000 0x4000>;
+			};
+
+			etpucode@3fd0000 {		// eTPU Shared Code RAM
+				compatible = "fsl,mpc5554-etpucode";
+				reg = <0x03fd0000 0x4000>;
+			};
+		};
+
+		bridge@fff00000 {
+			compatible = "fsl,mpc5554-pbridge-b";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0xe0000000 0x20000000>;
+			reg = <0xfff00000 0x4000>;
+
+			ecsm@fff40000 {		// Error Correction Status Module (ECSM)
+				compatible = "fsl,mpc5554-ecsm";
+				reg = <0xfff40000 0x4000>;
+			};
+
+			edma@fff44000 {		// Enhanced DMA Controller (eDMA)
+				compatible = "fsl,mpc5554-edma";
+				reg = <0xfff44000 0x4000>;
+			};
+
+			intc@fff48000 {		// Interrupt Controller (INTC)
+				compatible = "fsl,mpc5554-intc";
+				reg = <0xfff48000 0x4000>;
+			};
+
+			eqadc@fff80000 {	// Enhanced Queued Analog-to-Digital Converter (eQADC)
+				compatible = "fsl,mpc5554-eqacd";
+				reg = <0xfff80000 0x4000>;
+			};
+
+			dspi@fff90000 {		// Deserial Serial Peripheral Interface (DSPI_A)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff90000 0x4000>;
+			};
+
+			dspi@fff94000 {		// Deserial Serial Peripheral Interface (DSPI_B)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff94000 0x4000>;
+			};
+
+			dspi@fff98000 {		// Deserial Serial Peripheral Interface (DSPI_C)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff98000 0x4000>;
+			};
+
+			dspi@fff9c000 {		// Deserial Serial Peripheral Interface (DSPI_D)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff9c000 0x4000>;
+			};
+
+			sci@fffb0000 {		// Serial Communications Interface (SCI_A)
+				compatible = "fsl,mpc5554-sci";
+				reg = <0xfffb0000 0x4000>;
+			};
+
+			sci@fffb4000 {		// Serial Communications Interface (SCI_B)
+				compatible = "fsl,mpc5554-sci";
+				reg = <0xfffb4000 0x4000>;
+			};
+
+			can@fffc0000 {		// Controller Area Network (FlexCAN_A)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0xfffc0000 0x4000>;
+			};
+
+			can@fffc4000 {		// Controller Area Network (FlexCAN_B)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0xfffc4000 0x4000>;
+			};
+
+			can@fffc8000 {		// Controller Area Network (FlexCAN_C)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0xfffc8000 0x4000>;
+			};
+
+			bam@ffffc000 {		// Boot Assist Module (BAM)
+				compatible = "fsl,mpc5554-bam";
+				reg = <0xffffc000 0x4000>;
+			};
+
+		};
+
+	};
+
+};

Re: Freescale MPC5554 device tree (was: cross-compiling Linux for PowerPC e200 core?)

[Grant Likely]

2010/3/11 N=E9meth M=E1rton <nm127@freemail.hu>:
> Hi,
>
> thank you for the comments, I reworked the Freescale MPC5554 device tree
> accordingly. I'm listening for comments on this draft.
>
> Regards,
>
> =A0 =A0 =A0 =A0M=E1rton N=E9meth
>
> ---
> From: M=E1rton N=E9meth <nm127@freemail.hu>
>
> Add device tree for Freescale MPC5554.
>
> Signed-off-by: M=E1rton N=E9meth <nm127@freemail.hu>
> ---
> diff -uprN linux-2.6.33.orig/arch/powerpc/boot/dts/mpc5554.dts linux/arch=
/powerpc/boot/dts/mpc5554.dts
> --- linux-2.6.33.orig/arch/powerpc/boot/dts/mpc5554.dts 1970-01-01 01:00:=
00.000000000 +0100
> +++ linux/arch/powerpc/boot/dts/mpc5554.dts =A0 =A0 2010-03-12 07:22:37.0=
00000000 +0100
> @@ -0,0 +1,189 @@
> +/*
> + * Freescale MPC5554 Device Tree Source
> + *
> + * Based on MPC5553/5554 Microcontroller Reference Manual, Rev. 4.0, 04/=
2007
> + * http://www.freescale.com/files/32bit/doc/ref_manual/MPC5553_MPC5554_R=
M.pdf
> + *
> + * Copyright 2010 M=E1rton N=E9meth
> + * M=E1rton N=E9meth <nm127@freemail.hu>
> + *
> + * This program is free software; you can redistribute =A0it and/or modi=
fy it
> + * under =A0the terms of =A0the GNU General =A0Public License as publish=
ed by the
> + * Free Software Foundation; =A0either version 2 of the =A0License, or (=
at your
> + * option) any later version.
> + */
> +
> +/dts-v1/;
> +
> +/ {
> + =A0 =A0 =A0 model =3D "MPC5554";
> + =A0 =A0 =A0 compatible =3D "fsl,MPC5554EVB"; =A0 =A0 =A0 =A0 =A0// Free=
scale MPC5554 Evaluation Board
> + =A0 =A0 =A0 #address-cells =3D <1>;
> + =A0 =A0 =A0 #size-cells =3D <1>;

also need: interrupt-parent =3D <&intc>;

I describe why later...

> +
> + =A0 =A0 =A0 cpus {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 #address-cells =3D <1>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 #size-cells =3D <0>;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 cpu@0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 device_type =3D "cpu";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "PowerPC,555=
4";

I'd rather see the same convention used here as for all the other
compatible values in this file.  ie:

compatible =3D "fsl,mpc5554-e200z6", "fsl,powerpc-e200z6";

Dave, what do you think?

> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 d-cache-line-size =3D <32>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 i-cache-line-size =3D <32>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 d-cache-size =3D <0x8000>; =
=A0 =A0 =A0 =A0// L1, 32KiB
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 i-cache-size =3D <0x8000>; =
=A0 =A0 =A0 =A0// L1, 32KiB
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 timebase-frequency =3D <0>;=
 =A0 =A0 =A0 // from bootloader
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 bus-frequency =3D <0>; =A0 =
=A0 =A0 =A0 =A0 =A0// from bootloader
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 clock-frequency =3D <0>; =
=A0 =A0 =A0 =A0 =A0// from bootloader
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> + =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 memory@40000000 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 device_type =3D "memory";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x40000000 0x10000>; =A0 =A0 // 32=
KiB internal SRAM
> + =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 xbar@fff04000 { =A0 =A0 =A0 =A0 // System Bus Crossbar Swit=
ch (XBAR)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554-xbar";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 #address-cells =3D <1>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 #size-cells =3D <1>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 // The full memory range is covered by XBAR
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 ranges =3D <>;

An empty ranges property looks like this:

ranges;

> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 bridge@fff00000 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5554=
-pbridge-b";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 #address-cells =3D <1>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 #size-cells =3D <1>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ranges =3D <0 0xe0000000 0x=
20000000>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0xfff00000 0x4000>=
;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ecsm@fff40000 { =A0 =A0 =A0=
 =A0 // Error Correction Status Module (ECSM)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =
=3D "fsl,mpc5554-ecsm";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x=
fff40000 0x4000>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 edma@fff44000 { =A0 =A0 =A0=
 =A0 // Enhanced DMA Controller (eDMA)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =
=3D "fsl,mpc5554-edma";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x=
fff44000 0x4000>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 intc@fff48000 { =A0 =A0 =A0=
 =A0 // Interrupt Controller (INTC)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =
=3D "fsl,mpc5554-intc";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x=
fff48000 0x4000>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 };

Need a label on this node so that the rest of the tree can find it,
and it needs the interrupt-controller and #interrupt-cells properties:

                       intc: intc@fff48000 {         // Interrupt
Controller (INTC)
                               compatible =3D "fsl,mpc5554-intc";
                               interrupt-controller;
                               #interrupt-cells =3D <2>;
                               reg =3D <0xfff48000 0x4000>;
                       };

I've set #interrupt-cells to 2 which is fairly typical on fsl parts,
but that may or may not make sense.  You need to decide how each
device is going to specify it's interrupt line.  Often the first cell
is the hardware interrupt number, and the second cell encodes the
sense (high, low, edge).  Conversely, PCI interrupts only use
#interrupt-cells =3D <1> because all PCI irqs use the active low sense.

Then, each device in the tree should have an 'interrupts =3D < [hwirq#]
[sense]>;' property.

Otherwise, starting to look pretty good.

g.

Re: Freescale MPC5554 device tree (was: cross-compiling Linux for PowerPC e200 core?)

[David Gibson]

On Fri, Mar 12, 2010 at 05:14:56AM -0700, Grant Likely wrote:
> 2010/3/11 Németh Márton <nm127@freemail.hu>:
[snip]
> > +
> > +       cpus {
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +
> > +               cpu@0 {
> > +                       device_type = "cpu";
> > +                       compatible = "PowerPC,5554";
> 
> I'd rather see the same convention used here as for all the other
> compatible values in this file.  ie:
> 
> compatible = "fsl,mpc5554-e200z6", "fsl,powerpc-e200z6";
> 
> Dave, what do you think?

Well, you could add those too, but "PowerPC,5554" should probably
remain.

The historical background here is that in the original OF spec, driver
matching was done on node name, and only then on compatible.
Essentially the node name was treated as an implicit first entry in
the compatible list.  The the generic names convention came along, and
instead name became a human readable generic type for the device
("ethernet", "i2c", etc..).

That convention has been widely used since long before flat trees
existed, but for some reason it was never really used for cpu nodes;
they remained as "PowerPC,XXXX" or whatever.  Because the varying
names of cpu nodes was sometimes awkward to deal with in bootloaders,
we decided it would be sensible to apply the generic names convention
here too, so "cpu@X".  But then, the previous node name, which was
treated as being prepended to compatible, should now explicitly be put
into compatible.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: Freescale MPC5554 device tree (was: cross-compiling Linux for PowerPC e200 core?)

[Grant Likely]

On Fri, Mar 12, 2010 at 3:36 PM, David Gibson
<david@gibson.dropbear.id.au> wrote:
> On Fri, Mar 12, 2010 at 05:14:56AM -0700, Grant Likely wrote:
>> 2010/3/11 N=E9meth M=E1rton <nm127@freemail.hu>:
> [snip]
>> > +
>> > + =A0 =A0 =A0 cpus {
>> > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 #address-cells =3D <1>;
>> > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 #size-cells =3D <0>;
>> > +
>> > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 cpu@0 {
>> > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 device_type =3D "cpu";
>> > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "PowerPC,=
5554";
>>
>> I'd rather see the same convention used here as for all the other
>> compatible values in this file. =A0ie:
>>
>> compatible =3D "fsl,mpc5554-e200z6", "fsl,powerpc-e200z6";
>>
>> Dave, what do you think?
>
> Well, you could add those too, but "PowerPC,5554" should probably
> remain.
>
> The historical background here is that in the original OF spec, driver
> matching was done on node name, and only then on compatible.
> Essentially the node name was treated as an implicit first entry in
> the compatible list. =A0The the generic names convention came along, and
> instead name became a human readable generic type for the device
> ("ethernet", "i2c", etc..).
>
> That convention has been widely used since long before flat trees
> existed, but for some reason it was never really used for cpu nodes;
> they remained as "PowerPC,XXXX" or whatever. =A0Because the varying
> names of cpu nodes was sometimes awkward to deal with in bootloaders,
> we decided it would be sensible to apply the generic names convention
> here too, so "cpu@X". =A0But then, the previous node name, which was
> treated as being prepended to compatible, should now explicitly be put
> into compatible.

In this particular case, we're talking about a part that has never
previously been described in a device tree.  So, since this is
something entirely new, what is the value in preserving the
PowerPC,XXXX style when there isn't any code that will be relying on
it?

g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: Freescale MPC5554 device tree (was: cross-compiling Linux for PowerPC e200 core?)

[Segher Boessenkool]

> The historical background here is that in the original OF spec, driver
> matching was done on node name, and only then on compatible.
> Essentially the node name was treated as an implicit first entry in
> the compatible list.  The the generic names convention came along, and
> instead name became a human readable generic type for the device
> ("ethernet", "i2c", etc..).

Even with the generic names recommended practice, matching is _still_
done on "name" first, and only then "compatible".  It isn't expected
that anything will try to match one the generic names, so for "new style"
nodes that in effect means matching on "compatible" only, but it is
important for compatibility.

> That convention has been widely used since long before flat trees
> existed, but for some reason it was never really used for cpu nodes;
> they remained as "PowerPC,XXXX" or whatever.

The PowerPC binding was not updated for generic names.

> Because the varying
> names of cpu nodes was sometimes awkward to deal with in bootloaders,
> we decided it would be sensible to apply the generic names convention
> here too, so "cpu@X".  But then, the previous node name, which was
> treated as being prepended to compatible, should now explicitly be put
> into compatible.

Yes.


Segher

Re: Freescale MPC5554 device tree (was: cross-compiling Linux for PowerPC e200 core?)

[Segher Boessenkool]

> In this particular case, we're talking about a part that has never
> previously been described in a device tree.  So, since this is
> something entirely new, what is the value in preserving the
> PowerPC,XXXX style when there isn't any code that will be relying on
> it?

There could be code that matches anything starting with "PowerPC,".
Also, consistency is a good thing no matter what.


Segher

Re: Freescale MPC5554 device tree (was: cross-compiling Linux for PowerPC e200 core?)

[Németh Márton]

Hi,

here is a version with modified cpu node, xbar ranges and added interrupt sources.
Please send comments.

Regards,

	Márton Németh

---
From: Márton Németh <nm127@freemail.hu>

Add device tree for Freescale MPC5554.

Signed-off-by: Márton Németh <nm127@freemail.hu>
---
diff -uprN linux-2.6.33.orig/arch/powerpc/boot/dts/mpc5554.dts linux/arch/powerpc/boot/dts/mpc5554.dts
--- linux-2.6.33.orig/arch/powerpc/boot/dts/mpc5554.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux/arch/powerpc/boot/dts/mpc5554.dts	2010-03-13 12:52:32.000000000 +0100
@@ -0,0 +1,473 @@
+/*
+ * Freescale MPC5554 Device Tree Source
+ *
+ * Based on MPC5553/5554 Microcontroller Reference Manual, Rev. 4.0, 04/2007
+ * http://www.freescale.com/files/32bit/doc/ref_manual/MPC5553_MPC5554_RM.pdf
+ *  - Block Diagram: page 1-3, Figure 1-1
+ *  - Memory Map: page 1-21, Table 1-2
+ *  - Interrupt Request Sources: page 10-16, Table 10-9
+ *
+ * Copyright 2010 Márton Németh
+ * Márton Németh <nm127@freemail.hu>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "MPC5554";
+	compatible = "fsl,MPC5554EVB";		// Freescale MPC5554 Evaluation Board
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&intc>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "PowerPC,5554", "fsl,mpc5554-e200z6", "fsl,powerpc-e200z6";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;	// L1, 32KiB
+			i-cache-size = <0x8000>;	// L1, 32KiB
+			timebase-frequency = <0>;	// from bootloader
+			bus-frequency = <0>;		// from bootloader
+			clock-frequency = <0>;		// from bootloader
+		};
+	};
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x40000000 0x10000>;	// 32KiB internal SRAM
+	};
+
+	xbar@fff04000 {		// System Bus Crossbar Switch (XBAR)
+		compatible = "fsl,mpc5554-xbar";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		// The full memory range is covered by XBAR
+		ranges;
+		reg = <0xfff04000 0x4000>;
+
+		flash@0 {	// read-only FLASH
+			compatible = "fsl,mpc5554-flash";
+			reg = <0x00000000 0x200000>;	// 2MiB internal FLASH
+		};
+
+		bridge@c3f00000 {
+			compatible = "fsl,mpc5554-pbridge-a";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0xc0000000 0x20000000>;
+			reg = <0xc3f00000 0x4000>;
+
+			fmpll@3f80000 {		// Frequency Modulated PLL
+				compatible = "fsl,mpc5554-fmpll";
+				reg = <0x03f80000 0x4000>;
+				interrupts = <43 1	// Loss of Clock
+					      44 1>;	// Loss of Lock
+			};
+
+			flashconfig@3f88000 {	// Flash Configuration
+				compatible = "fsl,mpc5554-flashconfig";
+				reg = <0x03f88000 0x4000>;
+			};
+
+			siu@3f89000 {		// System Integration Unit
+				compatible = "fsl,mpc5554-siu";
+				reg = <0x03f90000 0x4000>;
+				interrupts = <45 1	// External Interrupt Overrun 0-15
+					      46 1	// External Interrupt 0
+					      47 1	// External Interrupt 1
+					      48 1	// External Interrupt 2
+					      49 1	// External Interrupt 3
+					      50 1>;	// External Interrupt 4-15
+			};
+
+			emios@3fa0000 {		// Modular Timer System
+				compatible = "fsl,mpc5554-emios";
+				reg = <0x03fa0000 0x4000>;
+				interrupts = <51 1	// Channel 0
+					      52 1	// Channel 1
+					      53 1	// Channel 2
+					      54 1	// Channel 3
+					      55 1	// Channel 4
+					      56 1	// Channel 5
+					      57 1	// Channel 6
+					      58 1	// Channel 7
+					      59 1	// Channel 8
+					      60 1	// Channel 9
+					      61 1	// Channel 10
+					      62 1	// Channel 11
+					      63 1	// Channel 12
+					      64 1	// Channel 13
+					      65 1	// Channel 14
+					      66 1	// Channel 15
+					      202 1	// Channel 16
+					      203 1	// Channel 17
+					      204 1	// Channel 18
+					      205 1	// Channel 19
+					      206 1	// Channel 20
+					      207 1	// Channel 21
+					      208 1	// Channel 22
+					      209 1>;	// Channel 23
+			};
+
+			etpu@3fc0000 {		// Enhanced Time Processing Unit
+				compatible = "fsl,mpc5554-etpu";
+				reg = <0x03fc0000 0x4000>;
+				interrupts = <67 1	// Global Exception
+					      68 1	// A Channel 0
+					      69 1	// A Channel 1
+					      70 1	// A Channel 2
+					      71 1	// A Channel 3
+					      72 1	// A Channel 4
+					      73 1	// A Channel 5
+					      74 1	// A Channel 6
+					      75 1	// A Channel 7
+					      76 1	// A Channel 8
+					      77 1	// A Channel 9
+					      78 1	// A Channel 10
+					      79 1	// A Channel 11
+					      80 1	// A Channel 12
+					      81 1	// A Channel 13
+					      82 1	// A Channel 14
+					      83 1	// A Channel 15
+					      84 1	// A Channel 16
+					      85 1	// A Channel 17
+					      86 1	// A Channel 18
+					      87 1	// A Channel 19
+					      88 1	// A Channel 20
+					      89 1	// A Channel 21
+					      90 1	// A Channel 22
+					      91 1	// A Channel 23
+					      92 1	// A Channel 24
+					      93 1	// A Channel 25
+					      94 1	// A Channel 26
+					      95 1	// A Channel 27
+					      96 1	// A Channel 28
+					      97 1	// A Channel 29
+					      98 1	// A Channel 30
+					      99 1	// A Channel 31
+					      243 1	// B Channel 0
+					      244 1	// B Channel 1
+					      245 1	// B Channel 2
+					      246 1	// B Channel 3
+					      247 1	// B Channel 4
+					      248 1	// B Channel 5
+					      249 1	// B Channel 6
+					      250 1	// B Channel 7
+					      251 1	// B Channel 8
+					      252 1	// B Channel 9
+					      253 1	// B Channel 10
+					      254 1	// B Channel 11
+					      255 1	// B Channel 12
+					      256 1	// B Channel 13
+					      257 1	// B Channel 14
+					      258 1	// B Channel 15
+					      259 1	// B Channel 16
+					      260 1	// B Channel 17
+					      261 1	// B Channel 18
+					      262 1	// B Channel 19
+					      263 1	// B Channel 20
+					      264 1	// B Channel 21
+					      265 1	// B Channel 22
+					      266 1	// B Channel 23
+					      267 1	// B Channel 24
+					      268 1	// B Channel 25
+					      269 1	// B Channel 26
+					      270 1	// B Channel 27
+					      271 1	// B Channel 28
+					      272 1	// B Channel 29
+					      273 1	// B Channel 30
+					      274 1>;	// B Channel 31
+			};
+
+			etpudata@3fc8000 {	// eTPU Shared Data Memory (Parameter RAM)
+				compatible = "fsl,mpc5554-etpudata";
+				reg = <0x03fc8000 0x4000>;
+			};
+
+			etpudata@3fcc000 {	// eTPU Shared Data Memory (Parameter RAM) mirror
+				compatible = "fsl,mpc5554-etpudata";
+				reg = <0x03fcc000 0x4000>;
+			};
+
+			etpucode@3fd0000 {		// eTPU Shared Code RAM
+				compatible = "fsl,mpc5554-etpucode";
+				reg = <0x03fd0000 0x4000>;
+			};
+		};
+
+		bridge@fff00000 {
+			compatible = "fsl,mpc5554-pbridge-b";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0xe0000000 0x20000000>;
+			reg = <0xfff00000 0x4000>;
+
+			ecsm@fff40000 {		// Error Correction Status Module (ECSM)
+				compatible = "fsl,mpc5554-ecsm";
+				reg = <0xfff40000 0x4000>;
+				interrupts = <8 1	// Software Watchdog Interrupt
+					      9 1>;	// Combined: Internal SRAM Non-Correctable Error, Flash Non-Correctable Error
+			};
+
+			edma@fff44000 {		// Enhanced DMA Controller (eDMA)
+				compatible = "fsl,mpc5554-edma";
+				reg = <0xfff44000 0x4000>;
+				interrupts = <10 1	// Channel Error 0-31
+					      11 1	// Channel 0
+					      12 1	// Channel 1
+					      13 1	// Channel 2
+					      14 1	// Channel 3
+					      15 1	// Channel 4
+					      16 1	// Channel 5
+					      17 1	// Channel 6
+					      18 1	// Channel 7
+					      19 1	// Channel 8
+					      20 1	// Channel 9
+					      21 1	// Channel 10
+					      22 1	// Channel 11
+					      23 1	// Channel 12
+					      24 1	// Channel 13
+					      25 1	// Channel 14
+					      26 1	// Channel 15
+					      27 1	// Channel 16
+					      28 1	// Channel 17
+					      29 1	// Channel 18
+					      30 1	// Channel 19
+					      31 1	// Channel 20
+					      32 1	// Channel 21
+					      33 1	// Channel 22
+					      34 1	// Channel 23
+					      35 1	// Channel 24
+					      36 1	// Channel 25
+					      37 1	// Channel 26
+					      38 1	// Channel 27
+					      39 1	// Channel 28
+					      40 1	// Channel 29
+					      41 1	// Channel 30
+					      42 1	// Channel 31
+					      210 1	// Channel Error 32-63
+					      211 1	// Channel 32
+					      212 1	// Channel 33
+					      213 1	// Channel 34
+					      214 1	// Channel 35
+					      215 1	// Channel 36
+					      216 1	// Channel 37
+					      217 1	// Channel 38
+					      218 1	// Channel 39
+					      219 1	// Channel 40
+					      220 1	// Channel 41
+					      221 1	// Channel 42
+					      222 1	// Channel 43
+					      223 1	// Channel 44
+					      224 1	// Channel 45
+					      225 1	// Channel 46
+					      226 1	// Channel 47
+					      227 1	// Channel 48
+					      228 1	// Channel 49
+					      229 1	// Channel 50
+					      230 1	// Channel 51
+					      231 1	// Channel 52
+					      232 1	// Channel 53
+					      233 1	// Channel 54
+					      234 1	// Channel 55
+					      235 1	// Channel 56
+					      236 1	// Channel 57
+					      237 1	// Channel 58
+					      238 1	// Channel 59
+					      239 1	// Channel 60
+					      240 1	// Channel 61
+					      241 1	// Channel 62
+					      242 1>;	// Channel 63
+			};
+
+			intc: intc@fff48000 {		// Interrupt Controller (INTC)
+				compatible = "fsl,mpc5554-intc";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				reg = <0xfff48000 0x4000>;
+			};
+
+			eqadc@fff80000 {	// Enhanced Queued Analog-to-Digital Converter (eQADC)
+				compatible = "fsl,mpc5554-eqacd";
+				reg = <0xfff80000 0x4000>;
+				interrupts = <100 1	// Combined: Trigger Overrun, Receive FIFO Overflow, Command FIFO Underflow
+					      101 1	// Command FIFO 0 Non-Coherency
+					      102 1	// Command FIFO 0 Pause
+					      103 1	// Command FIFO 0 End of Queue
+					      104 1	// Command FIFO 0 Fill
+					      105 1	// Command FIFO 0 Drain
+					      106 1	// Command FIFO 1 Non-Coherency
+					      107 1	// Command FIFO 1 Pause
+					      108 1	// Command FIFO 1 End of Queue
+					      109 1	// Command FIFO 1 Fill
+					      111 1	// Command FIFO 1 Drain
+					      111 1	// Command FIFO 2 Non-Coherency
+					      112 1	// Command FIFO 2 Pause
+					      113 1	// Command FIFO 2 End of Queue
+					      114 1	// Command FIFO 2 Fill
+					      115 1	// Command FIFO 2 Drain
+					      116 1	// Command FIFO 3 Non-Coherency
+					      117 1	// Command FIFO 3 Pause
+					      118 1	// Command FIFO 3 End of Queue
+					      119 1	// Command FIFO 3 Fill
+					      120 1	// Command FIFO 3 Drain
+					      121 1	// Command FIFO 4 Non-Coherency
+					      122 1	// Command FIFO 4 Pause
+					      123 1	// Command FIFO 4 End of Queue
+					      124 1	// Command FIFO 4 Fill
+					      125 1	// Command FIFO 4 Drain
+					      126 1	// Command FIFO 5 Non-Coherency
+					      127 1	// Command FIFO 5 Pause
+					      128 1	// Command FIFO 5 End of Queue
+					      129 1	// Command FIFO 5 Fill
+					      130 1>;	// Command FIFO 5 Drain
+			};
+
+			dspi@fff90000 {		// Deserial Serial Peripheral Interface (DSPI_A)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff90000 0x4000>;
+				interrupts = <275 1	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
+					      276 1	// Transmit FIFO End of Queue
+					      277 1	// Transmit FIFO Fill Flag
+					      278 1	// Transfer Complete
+					      279 1>;	// Receive FIFO Drain
+			};
+
+			dspi@fff94000 {		// Deserial Serial Peripheral Interface (DSPI_B)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff94000 0x4000>;
+				interrupts = <131 1	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
+					      132 1	// Transmit FIFO End of Queue
+					      133 1	// Transmit FIFO Fill Flag
+					      134 1	// Transfer Complete
+					      135 1>;	// Receive FIFO Drain
+			};
+
+			dspi@fff98000 {		// Deserial Serial Peripheral Interface (DSPI_C)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff98000 0x4000>;
+				interrupts = <136 1	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
+					      137 1	// Transmit FIFO End of Queue
+					      138 1	// Transmit FIFO Fill Flag
+					      139 1	// Transfer Complete
+					      140 1>;	// Receive FIFO Drain
+			};
+
+			dspi@fff9c000 {		// Deserial Serial Peripheral Interface (DSPI_D)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff9c000 0x4000>;
+				interrupts = <141 1	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
+					      142 1	// Transmit FIFO End of Queue
+					      143 1	// Transmit FIFO Fill Flag
+					      144 1	// Transfer Complete
+					      145 1>;	// Receive FIFO Drain
+			};
+
+			esci@fffb0000 {		// Serial Communications Interface (SCI_A)
+				compatible = "fsl,mpc5554-esci";
+				reg = <0xfffb0000 0x4000>;
+				interrupts = <146 1>;	// Combined request for all SCI_A interrupts
+			};
+
+			esci@fffb4000 {		// Serial Communications Interface (SCI_B)
+				compatible = "fsl,mpc5554-esci";
+				reg = <0xfffb4000 0x4000>;
+				interrupts = <149 1>;	// Combined request for all SCI_A interrupts
+			};
+
+			can@fffc0000 {		// Controller Area Network (FlexCAN_A)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0xfffc0000 0x4000>;
+				interrupts = <152 1	// Bus off
+					      153 1	// Error
+					      155 1	// Buffer 0
+					      156 1	// Buffer 1
+					      157 1	// Buffer 2
+					      158 1	// Buffer 3
+					      159 1	// Buffer 4
+					      160 1	// Buffer 5
+					      161 1	// Buffer 6
+					      162 1	// Buffer 7
+					      163 1	// Buffer 8
+					      164 1	// Buffer 9
+					      165 1	// Buffer 10
+					      166 1	// Buffer 11
+					      167 1	// Buffer 12
+					      168 1	// Buffer 13
+					      169 1	// Buffer 14
+					      170 1	// Buffer 15
+					      171 1	// Buffers 16-31
+					      172 1>;	// Buffers 32-63
+			};
+
+			can@fffc4000 {		// Controller Area Network (FlexCAN_B)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0xfffc4000 0x4000>;
+				interrupts = <280 1	// Bus off
+					      281 1	// Error
+					      283 1	// Buffer 0
+					      284 1	// Buffer 1
+					      285 1	// Buffer 2
+					      286 1	// Buffer 3
+					      287 1	// Buffer 4
+					      288 1	// Buffer 5
+					      289 1	// Buffer 6
+					      290 1	// Buffer 7
+					      291 1	// Buffer 8
+					      292 1	// Buffer 9
+					      293 1	// Buffer 10
+					      294 1	// Buffer 11
+					      295 1	// Buffer 12
+					      296 1	// Buffer 13
+					      297 1	// Buffer 14
+					      298 1	// Buffer 15
+					      299 1	// Buffers 16-31
+					      300 1>;	// Buffers 32-63
+			};
+
+			can@fffc8000 {		// Controller Area Network (FlexCAN_C)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0xfffc8000 0x4000>;
+				interrupts = <173 1	// Bus off
+					      174 1	// Error
+					      176 1	// Buffer 0
+					      177 1	// Buffer 1
+					      178 1	// Buffer 2
+					      179 1	// Buffer 3
+					      180 1	// Buffer 4
+					      181 1	// Buffer 5
+					      182 1	// Buffer 6
+					      183 1	// Buffer 7
+					      184 1	// Buffer 8
+					      185 1	// Buffer 9
+					      186 1	// Buffer 10
+					      187 1	// Buffer 11
+					      188 1	// Buffer 12
+					      189 1	// Buffer 13
+					      190 1	// Buffer 14
+					      191 1	// Buffer 15
+					      192 1	// Buffers 16-31
+					      193 1>;	// Buffers 32-63
+			};
+
+			bam@ffffc000 {		// Boot Assist Module (BAM)
+				compatible = "fsl,mpc5554-bam";
+				reg = <0xffffc000 0x4000>;
+			};
+
+		};
+
+	};
+
+};

Re: Freescale MPC5554 device tree (was: cross-compiling Linux for PowerPC e200 core?)

[Németh Márton]

Hi Grant, David and Segher,

is there any comments or suggestions about this MPC5554 device tree?

Regards,

	Márton Németh

Németh Márton wrote:
> Hi,
> 
> here is a version with modified cpu node, xbar ranges and added interrupt sources.
> Please send comments.
> 
> Regards,
> 
> 	Márton Németh
> 
> ---
> From: Márton Németh <nm127@freemail.hu>
> 
> Add device tree for Freescale MPC5554.
> 
> Signed-off-by: Márton Németh <nm127@freemail.hu>
> ---
> diff -uprN linux-2.6.33.orig/arch/powerpc/boot/dts/mpc5554.dts linux/arch/powerpc/boot/dts/mpc5554.dts
> --- linux-2.6.33.orig/arch/powerpc/boot/dts/mpc5554.dts	1970-01-01 01:00:00.000000000 +0100
> +++ linux/arch/powerpc/boot/dts/mpc5554.dts	2010-03-13 12:52:32.000000000 +0100
> @@ -0,0 +1,473 @@
> +/*
> + * Freescale MPC5554 Device Tree Source
> + *
> + * Based on MPC5553/5554 Microcontroller Reference Manual, Rev. 4.0, 04/2007
> + * http://www.freescale.com/files/32bit/doc/ref_manual/MPC5553_MPC5554_RM.pdf
> + *  - Block Diagram: page 1-3, Figure 1-1
> + *  - Memory Map: page 1-21, Table 1-2
> + *  - Interrupt Request Sources: page 10-16, Table 10-9
> + *
> + * Copyright 2010 Márton Németh
> + * Márton Németh <nm127@freemail.hu>
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + */
> +
> +/dts-v1/;
> +
> +/ {
> +	model = "MPC5554";
> +	compatible = "fsl,MPC5554EVB";		// Freescale MPC5554 Evaluation Board
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	interrupt-parent = <&intc>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu@0 {
> +			device_type = "cpu";
> +			compatible = "PowerPC,5554", "fsl,mpc5554-e200z6", "fsl,powerpc-e200z6";
> +			reg = <0>;
> +			d-cache-line-size = <32>;
> +			i-cache-line-size = <32>;
> +			d-cache-size = <0x8000>;	// L1, 32KiB
> +			i-cache-size = <0x8000>;	// L1, 32KiB
> +			timebase-frequency = <0>;	// from bootloader
> +			bus-frequency = <0>;		// from bootloader
> +			clock-frequency = <0>;		// from bootloader
> +		};
> +	};
> +
> +	memory@40000000 {
> +		device_type = "memory";
> +		reg = <0x40000000 0x10000>;	// 32KiB internal SRAM
> +	};
> +
> +	xbar@fff04000 {		// System Bus Crossbar Switch (XBAR)
> +		compatible = "fsl,mpc5554-xbar";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		// The full memory range is covered by XBAR
> +		ranges;
> +		reg = <0xfff04000 0x4000>;
> +
> +		flash@0 {	// read-only FLASH
> +			compatible = "fsl,mpc5554-flash";
> +			reg = <0x00000000 0x200000>;	// 2MiB internal FLASH
> +		};
> +
> +		bridge@c3f00000 {
> +			compatible = "fsl,mpc5554-pbridge-a";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0xc0000000 0x20000000>;
> +			reg = <0xc3f00000 0x4000>;
> +
> +			fmpll@3f80000 {		// Frequency Modulated PLL
> +				compatible = "fsl,mpc5554-fmpll";
> +				reg = <0x03f80000 0x4000>;
> +				interrupts = <43 1	// Loss of Clock
> +					      44 1>;	// Loss of Lock
> +			};
> +
> +			flashconfig@3f88000 {	// Flash Configuration
> +				compatible = "fsl,mpc5554-flashconfig";
> +				reg = <0x03f88000 0x4000>;
> +			};
> +
> +			siu@3f89000 {		// System Integration Unit
> +				compatible = "fsl,mpc5554-siu";
> +				reg = <0x03f90000 0x4000>;
> +				interrupts = <45 1	// External Interrupt Overrun 0-15
> +					      46 1	// External Interrupt 0
> +					      47 1	// External Interrupt 1
> +					      48 1	// External Interrupt 2
> +					      49 1	// External Interrupt 3
> +					      50 1>;	// External Interrupt 4-15
> +			};
> +
> +			emios@3fa0000 {		// Modular Timer System
> +				compatible = "fsl,mpc5554-emios";
> +				reg = <0x03fa0000 0x4000>;
> +				interrupts = <51 1	// Channel 0
> +					      52 1	// Channel 1
> +					      53 1	// Channel 2
> +					      54 1	// Channel 3
> +					      55 1	// Channel 4
> +					      56 1	// Channel 5
> +					      57 1	// Channel 6
> +					      58 1	// Channel 7
> +					      59 1	// Channel 8
> +					      60 1	// Channel 9
> +					      61 1	// Channel 10
> +					      62 1	// Channel 11
> +					      63 1	// Channel 12
> +					      64 1	// Channel 13
> +					      65 1	// Channel 14
> +					      66 1	// Channel 15
> +					      202 1	// Channel 16
> +					      203 1	// Channel 17
> +					      204 1	// Channel 18
> +					      205 1	// Channel 19
> +					      206 1	// Channel 20
> +					      207 1	// Channel 21
> +					      208 1	// Channel 22
> +					      209 1>;	// Channel 23
> +			};
> +
> +			etpu@3fc0000 {		// Enhanced Time Processing Unit
> +				compatible = "fsl,mpc5554-etpu";
> +				reg = <0x03fc0000 0x4000>;
> +				interrupts = <67 1	// Global Exception
> +					      68 1	// A Channel 0
> +					      69 1	// A Channel 1
> +					      70 1	// A Channel 2
> +					      71 1	// A Channel 3
> +					      72 1	// A Channel 4
> +					      73 1	// A Channel 5
> +					      74 1	// A Channel 6
> +					      75 1	// A Channel 7
> +					      76 1	// A Channel 8
> +					      77 1	// A Channel 9
> +					      78 1	// A Channel 10
> +					      79 1	// A Channel 11
> +					      80 1	// A Channel 12
> +					      81 1	// A Channel 13
> +					      82 1	// A Channel 14
> +					      83 1	// A Channel 15
> +					      84 1	// A Channel 16
> +					      85 1	// A Channel 17
> +					      86 1	// A Channel 18
> +					      87 1	// A Channel 19
> +					      88 1	// A Channel 20
> +					      89 1	// A Channel 21
> +					      90 1	// A Channel 22
> +					      91 1	// A Channel 23
> +					      92 1	// A Channel 24
> +					      93 1	// A Channel 25
> +					      94 1	// A Channel 26
> +					      95 1	// A Channel 27
> +					      96 1	// A Channel 28
> +					      97 1	// A Channel 29
> +					      98 1	// A Channel 30
> +					      99 1	// A Channel 31
> +					      243 1	// B Channel 0
> +					      244 1	// B Channel 1
> +					      245 1	// B Channel 2
> +					      246 1	// B Channel 3
> +					      247 1	// B Channel 4
> +					      248 1	// B Channel 5
> +					      249 1	// B Channel 6
> +					      250 1	// B Channel 7
> +					      251 1	// B Channel 8
> +					      252 1	// B Channel 9
> +					      253 1	// B Channel 10
> +					      254 1	// B Channel 11
> +					      255 1	// B Channel 12
> +					      256 1	// B Channel 13
> +					      257 1	// B Channel 14
> +					      258 1	// B Channel 15
> +					      259 1	// B Channel 16
> +					      260 1	// B Channel 17
> +					      261 1	// B Channel 18
> +					      262 1	// B Channel 19
> +					      263 1	// B Channel 20
> +					      264 1	// B Channel 21
> +					      265 1	// B Channel 22
> +					      266 1	// B Channel 23
> +					      267 1	// B Channel 24
> +					      268 1	// B Channel 25
> +					      269 1	// B Channel 26
> +					      270 1	// B Channel 27
> +					      271 1	// B Channel 28
> +					      272 1	// B Channel 29
> +					      273 1	// B Channel 30
> +					      274 1>;	// B Channel 31
> +			};
> +
> +			etpudata@3fc8000 {	// eTPU Shared Data Memory (Parameter RAM)
> +				compatible = "fsl,mpc5554-etpudata";
> +				reg = <0x03fc8000 0x4000>;
> +			};
> +
> +			etpudata@3fcc000 {	// eTPU Shared Data Memory (Parameter RAM) mirror
> +				compatible = "fsl,mpc5554-etpudata";
> +				reg = <0x03fcc000 0x4000>;
> +			};
> +
> +			etpucode@3fd0000 {		// eTPU Shared Code RAM
> +				compatible = "fsl,mpc5554-etpucode";
> +				reg = <0x03fd0000 0x4000>;
> +			};
> +		};
> +
> +		bridge@fff00000 {
> +			compatible = "fsl,mpc5554-pbridge-b";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0 0xe0000000 0x20000000>;
> +			reg = <0xfff00000 0x4000>;
> +
> +			ecsm@fff40000 {		// Error Correction Status Module (ECSM)
> +				compatible = "fsl,mpc5554-ecsm";
> +				reg = <0xfff40000 0x4000>;
> +				interrupts = <8 1	// Software Watchdog Interrupt
> +					      9 1>;	// Combined: Internal SRAM Non-Correctable Error, Flash Non-Correctable Error
> +			};
> +
> +			edma@fff44000 {		// Enhanced DMA Controller (eDMA)
> +				compatible = "fsl,mpc5554-edma";
> +				reg = <0xfff44000 0x4000>;
> +				interrupts = <10 1	// Channel Error 0-31
> +					      11 1	// Channel 0
> +					      12 1	// Channel 1
> +					      13 1	// Channel 2
> +					      14 1	// Channel 3
> +					      15 1	// Channel 4
> +					      16 1	// Channel 5
> +					      17 1	// Channel 6
> +					      18 1	// Channel 7
> +					      19 1	// Channel 8
> +					      20 1	// Channel 9
> +					      21 1	// Channel 10
> +					      22 1	// Channel 11
> +					      23 1	// Channel 12
> +					      24 1	// Channel 13
> +					      25 1	// Channel 14
> +					      26 1	// Channel 15
> +					      27 1	// Channel 16
> +					      28 1	// Channel 17
> +					      29 1	// Channel 18
> +					      30 1	// Channel 19
> +					      31 1	// Channel 20
> +					      32 1	// Channel 21
> +					      33 1	// Channel 22
> +					      34 1	// Channel 23
> +					      35 1	// Channel 24
> +					      36 1	// Channel 25
> +					      37 1	// Channel 26
> +					      38 1	// Channel 27
> +					      39 1	// Channel 28
> +					      40 1	// Channel 29
> +					      41 1	// Channel 30
> +					      42 1	// Channel 31
> +					      210 1	// Channel Error 32-63
> +					      211 1	// Channel 32
> +					      212 1	// Channel 33
> +					      213 1	// Channel 34
> +					      214 1	// Channel 35
> +					      215 1	// Channel 36
> +					      216 1	// Channel 37
> +					      217 1	// Channel 38
> +					      218 1	// Channel 39
> +					      219 1	// Channel 40
> +					      220 1	// Channel 41
> +					      221 1	// Channel 42
> +					      222 1	// Channel 43
> +					      223 1	// Channel 44
> +					      224 1	// Channel 45
> +					      225 1	// Channel 46
> +					      226 1	// Channel 47
> +					      227 1	// Channel 48
> +					      228 1	// Channel 49
> +					      229 1	// Channel 50
> +					      230 1	// Channel 51
> +					      231 1	// Channel 52
> +					      232 1	// Channel 53
> +					      233 1	// Channel 54
> +					      234 1	// Channel 55
> +					      235 1	// Channel 56
> +					      236 1	// Channel 57
> +					      237 1	// Channel 58
> +					      238 1	// Channel 59
> +					      239 1	// Channel 60
> +					      240 1	// Channel 61
> +					      241 1	// Channel 62
> +					      242 1>;	// Channel 63
> +			};
> +
> +			intc: intc@fff48000 {		// Interrupt Controller (INTC)
> +				compatible = "fsl,mpc5554-intc";
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				reg = <0xfff48000 0x4000>;
> +			};
> +
> +			eqadc@fff80000 {	// Enhanced Queued Analog-to-Digital Converter (eQADC)
> +				compatible = "fsl,mpc5554-eqacd";
> +				reg = <0xfff80000 0x4000>;
> +				interrupts = <100 1	// Combined: Trigger Overrun, Receive FIFO Overflow, Command FIFO Underflow
> +					      101 1	// Command FIFO 0 Non-Coherency
> +					      102 1	// Command FIFO 0 Pause
> +					      103 1	// Command FIFO 0 End of Queue
> +					      104 1	// Command FIFO 0 Fill
> +					      105 1	// Command FIFO 0 Drain
> +					      106 1	// Command FIFO 1 Non-Coherency
> +					      107 1	// Command FIFO 1 Pause
> +					      108 1	// Command FIFO 1 End of Queue
> +					      109 1	// Command FIFO 1 Fill
> +					      111 1	// Command FIFO 1 Drain
> +					      111 1	// Command FIFO 2 Non-Coherency
> +					      112 1	// Command FIFO 2 Pause
> +					      113 1	// Command FIFO 2 End of Queue
> +					      114 1	// Command FIFO 2 Fill
> +					      115 1	// Command FIFO 2 Drain
> +					      116 1	// Command FIFO 3 Non-Coherency
> +					      117 1	// Command FIFO 3 Pause
> +					      118 1	// Command FIFO 3 End of Queue
> +					      119 1	// Command FIFO 3 Fill
> +					      120 1	// Command FIFO 3 Drain
> +					      121 1	// Command FIFO 4 Non-Coherency
> +					      122 1	// Command FIFO 4 Pause
> +					      123 1	// Command FIFO 4 End of Queue
> +					      124 1	// Command FIFO 4 Fill
> +					      125 1	// Command FIFO 4 Drain
> +					      126 1	// Command FIFO 5 Non-Coherency
> +					      127 1	// Command FIFO 5 Pause
> +					      128 1	// Command FIFO 5 End of Queue
> +					      129 1	// Command FIFO 5 Fill
> +					      130 1>;	// Command FIFO 5 Drain
> +			};
> +
> +			dspi@fff90000 {		// Deserial Serial Peripheral Interface (DSPI_A)
> +				compatible = "fsl,mpc5554-dspi";
> +				reg = <0xfff90000 0x4000>;
> +				interrupts = <275 1	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
> +					      276 1	// Transmit FIFO End of Queue
> +					      277 1	// Transmit FIFO Fill Flag
> +					      278 1	// Transfer Complete
> +					      279 1>;	// Receive FIFO Drain
> +			};
> +
> +			dspi@fff94000 {		// Deserial Serial Peripheral Interface (DSPI_B)
> +				compatible = "fsl,mpc5554-dspi";
> +				reg = <0xfff94000 0x4000>;
> +				interrupts = <131 1	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
> +					      132 1	// Transmit FIFO End of Queue
> +					      133 1	// Transmit FIFO Fill Flag
> +					      134 1	// Transfer Complete
> +					      135 1>;	// Receive FIFO Drain
> +			};
> +
> +			dspi@fff98000 {		// Deserial Serial Peripheral Interface (DSPI_C)
> +				compatible = "fsl,mpc5554-dspi";
> +				reg = <0xfff98000 0x4000>;
> +				interrupts = <136 1	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
> +					      137 1	// Transmit FIFO End of Queue
> +					      138 1	// Transmit FIFO Fill Flag
> +					      139 1	// Transfer Complete
> +					      140 1>;	// Receive FIFO Drain
> +			};
> +
> +			dspi@fff9c000 {		// Deserial Serial Peripheral Interface (DSPI_D)
> +				compatible = "fsl,mpc5554-dspi";
> +				reg = <0xfff9c000 0x4000>;
> +				interrupts = <141 1	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
> +					      142 1	// Transmit FIFO End of Queue
> +					      143 1	// Transmit FIFO Fill Flag
> +					      144 1	// Transfer Complete
> +					      145 1>;	// Receive FIFO Drain
> +			};
> +
> +			esci@fffb0000 {		// Serial Communications Interface (SCI_A)
> +				compatible = "fsl,mpc5554-esci";
> +				reg = <0xfffb0000 0x4000>;
> +				interrupts = <146 1>;	// Combined request for all SCI_A interrupts
> +			};
> +
> +			esci@fffb4000 {		// Serial Communications Interface (SCI_B)
> +				compatible = "fsl,mpc5554-esci";
> +				reg = <0xfffb4000 0x4000>;
> +				interrupts = <149 1>;	// Combined request for all SCI_A interrupts
> +			};
> +
> +			can@fffc0000 {		// Controller Area Network (FlexCAN_A)
> +				compatible = "fsl,mpc5554-flexcan";
> +				reg = <0xfffc0000 0x4000>;
> +				interrupts = <152 1	// Bus off
> +					      153 1	// Error
> +					      155 1	// Buffer 0
> +					      156 1	// Buffer 1
> +					      157 1	// Buffer 2
> +					      158 1	// Buffer 3
> +					      159 1	// Buffer 4
> +					      160 1	// Buffer 5
> +					      161 1	// Buffer 6
> +					      162 1	// Buffer 7
> +					      163 1	// Buffer 8
> +					      164 1	// Buffer 9
> +					      165 1	// Buffer 10
> +					      166 1	// Buffer 11
> +					      167 1	// Buffer 12
> +					      168 1	// Buffer 13
> +					      169 1	// Buffer 14
> +					      170 1	// Buffer 15
> +					      171 1	// Buffers 16-31
> +					      172 1>;	// Buffers 32-63
> +			};
> +
> +			can@fffc4000 {		// Controller Area Network (FlexCAN_B)
> +				compatible = "fsl,mpc5554-flexcan";
> +				reg = <0xfffc4000 0x4000>;
> +				interrupts = <280 1	// Bus off
> +					      281 1	// Error
> +					      283 1	// Buffer 0
> +					      284 1	// Buffer 1
> +					      285 1	// Buffer 2
> +					      286 1	// Buffer 3
> +					      287 1	// Buffer 4
> +					      288 1	// Buffer 5
> +					      289 1	// Buffer 6
> +					      290 1	// Buffer 7
> +					      291 1	// Buffer 8
> +					      292 1	// Buffer 9
> +					      293 1	// Buffer 10
> +					      294 1	// Buffer 11
> +					      295 1	// Buffer 12
> +					      296 1	// Buffer 13
> +					      297 1	// Buffer 14
> +					      298 1	// Buffer 15
> +					      299 1	// Buffers 16-31
> +					      300 1>;	// Buffers 32-63
> +			};
> +
> +			can@fffc8000 {		// Controller Area Network (FlexCAN_C)
> +				compatible = "fsl,mpc5554-flexcan";
> +				reg = <0xfffc8000 0x4000>;
> +				interrupts = <173 1	// Bus off
> +					      174 1	// Error
> +					      176 1	// Buffer 0
> +					      177 1	// Buffer 1
> +					      178 1	// Buffer 2
> +					      179 1	// Buffer 3
> +					      180 1	// Buffer 4
> +					      181 1	// Buffer 5
> +					      182 1	// Buffer 6
> +					      183 1	// Buffer 7
> +					      184 1	// Buffer 8
> +					      185 1	// Buffer 9
> +					      186 1	// Buffer 10
> +					      187 1	// Buffer 11
> +					      188 1	// Buffer 12
> +					      189 1	// Buffer 13
> +					      190 1	// Buffer 14
> +					      191 1	// Buffer 15
> +					      192 1	// Buffers 16-31
> +					      193 1>;	// Buffers 32-63
> +			};
> +
> +			bam@ffffc000 {		// Boot Assist Module (BAM)
> +				compatible = "fsl,mpc5554-bam";
> +				reg = <0xffffc000 0x4000>;
> +			};
> +
> +		};
> +
> +	};
> +
> +};
> 

Re: Freescale MPC5554 device tree (was: cross-compiling Linux for PowerPC e200 core?)

[Grant Likely]

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ZC4KCkNoZWVycywKZy4K

Re: Freescale MPC5554 device tree (was: cross-compiling Linux for PowerPC e200 core?)

[Németh Márton]

Hi Grant,

thanks for the comments, I solved some of the points you mentioned. I need some
more time to work on the others. In the meantime I send the intermediate version.

Grant Likely wrote:
> 2010/3/13 Németh Márton <nm127@freemail.hu>:
[...]
>> +       memory@40000000 {
>> +               device_type = "memory";
>> +               reg = <0x40000000 0x10000>;     // 32KiB internal SRAM
>> +       };
> 
> Oh.... this is the small SRAM.  yeah, you should move this under the
> appropriate bridge node, remove the device_type property, and add a
> compatible property.  Memory nodes at the root like this are used to
> describe what is basically main memory (what Linux will execute out
> of).  You'll want a new memory node for the external ram hooked up to
> the 5554.

Yes, it is the small one (actually 64KiB, I corrected the comment also).
I added the external memory of the MPC5554DEMO evaluation board which has
a size of 512KiB.

Would it be possible to program the uncompressed kernel to the FLASH so
it can run directly from there? I guess for the code and the constant sections
the FLASH could be a good place. Then cstart has to initialize the initialized
variables by copying data from FLASH to RAM and fill the BSS area with zero.

[...]
>> +                       siu@3f89000 {           // System Integration Unit
>> +                               compatible = "fsl,mpc5554-siu";
>> +                               reg = <0x03f90000 0x4000>;
>> +                               interrupts = <45 1      // External Interrupt Overrun 0-15
>> +                                             46 1      // External Interrupt 0
>> +                                             47 1      // External Interrupt 1
>> +                                             48 1      // External Interrupt 2
>> +                                             49 1      // External Interrupt 3
>> +                                             50 1>;    // External Interrupt 4-15
>> +                       };
> 
> This doesn't look quite right.... /me goes to look at the 5554
> reference manual....
> 
> Okay, so all the external IRQs go through the SIU then, even though
> the first 4 get passed straight through to the intc?  And I see that
> all the level/edge sensing and masking/acknowledging is done at the
> SIU level, not the intc level, correct?  So, what you effectively have
> is the SIU is *another* interrupt controller that is cascaded to the
> intc.  Therefore you need to add the following to this node:
> 
> #interrupt-cells = <2>;   // cell1:extirq#, cell2:level/edge flags
> interrupt-controller;
> 
> Also give the node a label so that nodes for external devices can
> reference it for hooking up external irqs by overriding the top-level
> interrupt-parent property.
> 
> Also, it would appear that intc interrupts don't have any level/edge
> configuration associated with them.  They are either asserted, or they
> are not, correct?  At the moment you're specifying every intc
> interrupt with 2 cells, and the 2nd cell is always '1'.  I think you
> can change #interrupt-cells to <1> in the intc node and drop the '1'
> everywhere.
> 
> When you write your intc driver, you'll also need to write the
> cascaded driver for the external IRQs.

I tried to solve this point but I'm not quite sure whether the SIU interrupt
numbers shall be kept on the siu@3f89000 node or not.

>> +                       emios@3fa0000 {         // Modular Timer System
>> +                               compatible = "fsl,mpc5554-emios";
>> +                               reg = <0x03fa0000 0x4000>;
>> +                               interrupts = <51 1      // Channel 0
>> +                                             52 1      // Channel 1
>> +                                             53 1      // Channel 2
>> +                                             54 1      // Channel 3
>> +                                             55 1      // Channel 4
>> +                                             56 1      // Channel 5
>> +                                             57 1      // Channel 6
>> +                                             58 1      // Channel 7
>> +                                             59 1      // Channel 8
>> +                                             60 1      // Channel 9
>> +                                             61 1      // Channel 10
>> +                                             62 1      // Channel 11
>> +                                             63 1      // Channel 12
>> +                                             64 1      // Channel 13
>> +                                             65 1      // Channel 14
>> +                                             66 1      // Channel 15
>> +                                             202 1     // Channel 16
>> +                                             203 1     // Channel 17
>> +                                             204 1     // Channel 18
>> +                                             205 1     // Channel 19
>> +                                             206 1     // Channel 20
>> +                                             207 1     // Channel 21
>> +                                             208 1     // Channel 22
>> +                                             209 1>;   // Channel 23
> 
> These long lists bother me, but looking at the manual they seem to
> describe the actual hardware architecture, so I think they are
> probably fine.  But you may want to compact your formatting somewhat.
> You can probably list more than one channel per
> source line in the file.
>
> Ditto through the rest of the file.

I would keep the list like this because in this case it is easy to find
which comment belongs to which interrupt number. Otherwise one would need
to count the interrupt numbers and the comment to find out which number match
which comment.

>> +                       etpu@3fc0000 {          // Enhanced Time Processing Unit
>> +                               compatible = "fsl,mpc5554-etpu";
>> +                               reg = <0x03fc0000 0x4000>;
>> +                               interrupts = <67 1      // Global Exception
>> +                                             68 1      // A Channel 0
>> +                                             69 1      // A Channel 1
>> +                                             70 1      // A Channel 2
>> +                                             71 1      // A Channel 3
>> +                                             72 1      // A Channel 4
>> +                                             73 1      // A Channel 5
>> +                                             74 1      // A Channel 6
>> +                                             75 1      // A Channel 7
>> +                                             76 1      // A Channel 8
>> +                                             77 1      // A Channel 9
>> +                                             78 1      // A Channel 10
>> +                                             79 1      // A Channel 11
>> +                                             80 1      // A Channel 12
>> +                                             81 1      // A Channel 13
>> +                                             82 1      // A Channel 14
>> +                                             83 1      // A Channel 15
>> +                                             84 1      // A Channel 16
>> +                                             85 1      // A Channel 17
>> +                                             86 1      // A Channel 18
>> +                                             87 1      // A Channel 19
>> +                                             88 1      // A Channel 20
>> +                                             89 1      // A Channel 21
>> +                                             90 1      // A Channel 22
>> +                                             91 1      // A Channel 23
>> +                                             92 1      // A Channel 24
>> +                                             93 1      // A Channel 25
>> +                                             94 1      // A Channel 26
>> +                                             95 1      // A Channel 27
>> +                                             96 1      // A Channel 28
>> +                                             97 1      // A Channel 29
>> +                                             98 1      // A Channel 30
>> +                                             99 1      // A Channel 31
>> +                                             243 1     // B Channel 0
>> +                                             244 1     // B Channel 1
>> +                                             245 1     // B Channel 2
>> +                                             246 1     // B Channel 3
>> +                                             247 1     // B Channel 4
>> +                                             248 1     // B Channel 5
>> +                                             249 1     // B Channel 6
>> +                                             250 1     // B Channel 7
>> +                                             251 1     // B Channel 8
>> +                                             252 1     // B Channel 9
>> +                                             253 1     // B Channel 10
>> +                                             254 1     // B Channel 11
>> +                                             255 1     // B Channel 12
>> +                                             256 1     // B Channel 13
>> +                                             257 1     // B Channel 14
>> +                                             258 1     // B Channel 15
>> +                                             259 1     // B Channel 16
>> +                                             260 1     // B Channel 17
>> +                                             261 1     // B Channel 18
>> +                                             262 1     // B Channel 19
>> +                                             263 1     // B Channel 20
>> +                                             264 1     // B Channel 21
>> +                                             265 1     // B Channel 22
>> +                                             266 1     // B Channel 23
>> +                                             267 1     // B Channel 24
>> +                                             268 1     // B Channel 25
>> +                                             269 1     // B Channel 26
>> +                                             270 1     // B Channel 27
>> +                                             271 1     // B Channel 28
>> +                                             272 1     // B Channel 29
>> +                                             273 1     // B Channel 30
>> +                                             274 1>;   // B Channel 31
> 
> Are A and B two instances of the same hardware block?  Consider having
> a subnode for each instance to give some logical separation to this
> list and associate register ranges with instances.  Doing it that way
> also makes it easier for external device nodes to describe an
> attachment to a particular channel.

I'll try to do this later, I need some more time to do this.

> 
>> +                       };
>> +
>> +                       etpudata@3fc8000 {      // eTPU Shared Data Memory (Parameter RAM)
>> +                               compatible = "fsl,mpc5554-etpudata";
>> +                               reg = <0x03fc8000 0x4000>;
>> +                       };
>> +
>> +                       etpudata@3fcc000 {      // eTPU Shared Data Memory (Parameter RAM) mirror
>> +                               compatible = "fsl,mpc5554-etpudata";
>> +                               reg = <0x03fcc000 0x4000>;
>> +                       };
>> +
>> +                       etpucode@3fd0000 {              // eTPU Shared Code RAM
>> +                               compatible = "fsl,mpc5554-etpucode";
>> +                               reg = <0x03fd0000 0x4000>;
>> +                       };
> 
> Should all this etpu stuff be part of the etpu node?
> 
> This looks like it is getting close.  Once you've got a version that
> looks good to everyone, you also need to document what the new
> bindings mean.  Essentially this task involves writing down all the
> new compatible property values that you've defined, what device each
> one describes, and what properties/subnodes are expected for each new
> compatible value.  Documentation currently goes in the
> Documentation/powerpc/dts-bindings directory, and you can see lots of
> examples there.  (However, I'm hoping to moving it to
> http://devicetree.org in the near future so it can be shared by other
> OSes.  I've currently got a test site up at http://fdt.secretlab.ca).
> 
> The rule is that we will not merge drivers using new OF bindings until
> those bindings have been documented and reviewed.

The documentation is still missing from this version.

Regards,

	Márton Németh

---
From: Márton Németh <nm127@freemail.hu>

Add device tree for Freescale MPC5554.

Signed-off-by: Márton Németh <nm127@freemail.hu>
---
diff -uprN linux-2.6.33.orig/arch/powerpc/boot/dts/mpc5554.dts linux-2.6.33/arch/powerpc/boot/dts/mpc5554.dts
--- linux-2.6.33.orig/arch/powerpc/boot/dts/mpc5554.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.33/arch/powerpc/boot/dts/mpc5554.dts	2010-03-22 07:09:02.000000000 +0100
@@ -0,0 +1,488 @@
+/*
+ * Freescale MPC5554 Device Tree Source
+ *
+ * Based on MPC5553/5554 Microcontroller Reference Manual, Rev. 4.0, 04/2007
+ * http://www.freescale.com/files/32bit/doc/ref_manual/MPC5553_MPC5554_RM.pdf
+ *  - Block Diagram: page 1-3, Figure 1-1
+ *  - Memory Map: page 1-21, Table 1-2
+ *  - Interrupt Request Sources: page 10-16, Table 10-9
+ *
+ * This device tree also contains external components found on MPC5554DEMO
+ * http://www.axman.com/files/MPC5554DEMO_man_G.pdf
+ * http://www.axman.com/files/MPC5554DEMO_SCH_G.pdf
+ *
+ * Copyright 2010 Márton Németh
+ * Márton Németh <nm127@freemail.hu>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "MPC5554";
+	compatible = "fsl,MPC5554EVB";		// Freescale MPC5554 Evaluation Board
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&intc>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "PowerPC,5554", "fsl,mpc5554-e200z6", "fsl,powerpc-e200z6";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;	// L1, 32KiB
+			i-cache-size = <0x8000>;	// L1, 32KiB
+			timebase-frequency = <0>;	// from bootloader
+			bus-frequency = <0>;		// from bootloader
+			clock-frequency = <0>;		// from bootloader
+		};
+	};
+
+	memory@20000000 {
+		device_type = "memory";
+		reg = <0x20000000 0x80000>;	// 512KiB external SRAM: ISSI IS61SF12832
+		// CS0 or CS1 selectable by the SRAM_SEL jumper
+	};
+
+	xbar@fff04000 {		// System Bus Crossbar Switch (XBAR)
+		compatible = "fsl,mpc5554-xbar";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		// The full memory range is covered by XBAR
+		ranges;
+		reg = <0xfff04000 0x4000>;
+
+		flash@0 {	// read-only FLASH
+			compatible = "fsl,mpc5554-flash";
+			reg = <0x00000000 0x200000>;	// 2MiB internal FLASH
+		};
+
+		memory@40000000 {
+			compatible = "fsl,mpc5554-sram";
+			reg = <0x40000000 0x10000>;	// 64KiB internal SRAM
+		};
+
+		bridge@c3f00000 {
+			compatible = "fsl,mpc5554-pbridge-a";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0xc0000000 0x20000000>;
+			reg = <0xc3f00000 0x4000>;
+
+			fmpll@3f80000 {		// Frequency Modulated PLL
+				compatible = "fsl,mpc5554-fmpll";
+				reg = <0x03f80000 0x4000>;
+				interrupts = <43	// Loss of Clock
+					      44>;	// Loss of Lock
+			};
+
+			flashconfig@3f88000 {	// Flash Configuration
+				compatible = "fsl,mpc5554-flashconfig";
+				reg = <0x03f88000 0x4000>;
+			};
+
+			siuintc: siu@3f89000 {		// System Integration Unit
+				compatible = "fsl,mpc5554-siu";
+				reg = <0x03f90000 0x4000>;
+
+				// SIU is an interrupt controller by means that it handles
+				// the external interrupts
+				#interrupt-cells = <2>;   // cell 1: extirq#, cell 2: level/edge flags
+				interrupt-controller;
+				interrupts = <45 1	// External Interrupt Overrun 0-15
+					      46 1	// External Interrupt 0
+					      47 1	// External Interrupt 1
+					      48 1	// External Interrupt 2
+					      49 1	// External Interrupt 3
+					      50 1>;	// External Interrupt 4-15
+			};
+
+			emios@3fa0000 {		// Modular Timer System
+				compatible = "fsl,mpc5554-emios";
+				reg = <0x03fa0000 0x4000>;
+				interrupts = <51	// Channel 0
+					      52	// Channel 1
+					      53	// Channel 2
+					      54	// Channel 3
+					      55	// Channel 4
+					      56	// Channel 5
+					      57	// Channel 6
+					      58	// Channel 7
+					      59	// Channel 8
+					      60	// Channel 9
+					      61	// Channel 10
+					      62	// Channel 11
+					      63	// Channel 12
+					      64	// Channel 13
+					      65	// Channel 14
+					      66	// Channel 15
+					      202	// Channel 16
+					      203	// Channel 17
+					      204	// Channel 18
+					      205	// Channel 19
+					      206	// Channel 20
+					      207	// Channel 21
+					      208	// Channel 22
+					      209>;	// Channel 23
+			};
+
+			etpu@3fc0000 {		// Enhanced Time Processing Unit
+				compatible = "fsl,mpc5554-etpu";
+				reg = <0x03fc0000 0x4000>;
+				interrupts = <67	// Global Exception
+					      68	// A Channel 0
+					      69	// A Channel 1
+					      70	// A Channel 2
+					      71	// A Channel 3
+					      72	// A Channel 4
+					      73	// A Channel 5
+					      74	// A Channel 6
+					      75	// A Channel 7
+					      76	// A Channel 8
+					      77	// A Channel 9
+					      78	// A Channel 10
+					      79	// A Channel 11
+					      80	// A Channel 12
+					      81	// A Channel 13
+					      82	// A Channel 14
+					      83	// A Channel 15
+					      84	// A Channel 16
+					      85	// A Channel 17
+					      86	// A Channel 18
+					      87	// A Channel 19
+					      88	// A Channel 20
+					      89	// A Channel 21
+					      90	// A Channel 22
+					      91	// A Channel 23
+					      92	// A Channel 24
+					      93	// A Channel 25
+					      94	// A Channel 26
+					      95	// A Channel 27
+					      96	// A Channel 28
+					      97	// A Channel 29
+					      98	// A Channel 30
+					      99	// A Channel 31
+					      243	// B Channel 0
+					      244	// B Channel 1
+					      245	// B Channel 2
+					      246	// B Channel 3
+					      247	// B Channel 4
+					      248	// B Channel 5
+					      249	// B Channel 6
+					      250	// B Channel 7
+					      251	// B Channel 8
+					      252	// B Channel 9
+					      253	// B Channel 10
+					      254	// B Channel 11
+					      255	// B Channel 12
+					      256	// B Channel 13
+					      257	// B Channel 14
+					      258	// B Channel 15
+					      259	// B Channel 16
+					      260	// B Channel 17
+					      261	// B Channel 18
+					      262	// B Channel 19
+					      263	// B Channel 20
+					      264	// B Channel 21
+					      265	// B Channel 22
+					      266	// B Channel 23
+					      267	// B Channel 24
+					      268	// B Channel 25
+					      269	// B Channel 26
+					      270	// B Channel 27
+					      271	// B Channel 28
+					      272	// B Channel 29
+					      273	// B Channel 30
+					      274>;	// B Channel 31
+			};
+
+			etpudata@3fc8000 {	// eTPU Shared Data Memory (Parameter RAM)
+				compatible = "fsl,mpc5554-etpudata";
+				reg = <0x03fc8000 0x4000>;
+			};
+
+			etpudata@3fcc000 {	// eTPU Shared Data Memory (Parameter RAM) mirror
+				compatible = "fsl,mpc5554-etpudata";
+				reg = <0x03fcc000 0x4000>;
+			};
+
+			etpucode@3fd0000 {		// eTPU Shared Code RAM
+				compatible = "fsl,mpc5554-etpucode";
+				reg = <0x03fd0000 0x4000>;
+			};
+		};
+
+		bridge@fff00000 {
+			compatible = "fsl,mpc5554-pbridge-b";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0xe0000000 0x20000000>;
+			reg = <0xfff00000 0x4000>;
+
+			ecsm@fff40000 {		// Error Correction Status Module (ECSM)
+				compatible = "fsl,mpc5554-ecsm";
+				reg = <0xfff40000 0x4000>;
+				interrupts = <8	// Software Watchdog Interrupt
+					      9>;	// Combined: Internal SRAM Non-Correctable Error, Flash Non-Correctable Error
+			};
+
+			edma@fff44000 {		// Enhanced DMA Controller (eDMA)
+				compatible = "fsl,mpc5554-edma";
+				reg = <0xfff44000 0x4000>;
+				interrupts = <10	// Channel Error 0-31
+					      11	// Channel 0
+					      12	// Channel 1
+					      13	// Channel 2
+					      14	// Channel 3
+					      15	// Channel 4
+					      16	// Channel 5
+					      17	// Channel 6
+					      18	// Channel 7
+					      19	// Channel 8
+					      20	// Channel 9
+					      21	// Channel 10
+					      22	// Channel 11
+					      23	// Channel 12
+					      24	// Channel 13
+					      25	// Channel 14
+					      26	// Channel 15
+					      27	// Channel 16
+					      28	// Channel 17
+					      29	// Channel 18
+					      30	// Channel 19
+					      31	// Channel 20
+					      32	// Channel 21
+					      33	// Channel 22
+					      34	// Channel 23
+					      35	// Channel 24
+					      36	// Channel 25
+					      37	// Channel 26
+					      38	// Channel 27
+					      39	// Channel 28
+					      40	// Channel 29
+					      41	// Channel 30
+					      42	// Channel 31
+					      210	// Channel Error 32-63
+					      211	// Channel 32
+					      212	// Channel 33
+					      213	// Channel 34
+					      214	// Channel 35
+					      215	// Channel 36
+					      216	// Channel 37
+					      217	// Channel 38
+					      218	// Channel 39
+					      219	// Channel 40
+					      220	// Channel 41
+					      221	// Channel 42
+					      222	// Channel 43
+					      223	// Channel 44
+					      224	// Channel 45
+					      225	// Channel 46
+					      226	// Channel 47
+					      227	// Channel 48
+					      228	// Channel 49
+					      229	// Channel 50
+					      230	// Channel 51
+					      231	// Channel 52
+					      232	// Channel 53
+					      233	// Channel 54
+					      234	// Channel 55
+					      235	// Channel 56
+					      236	// Channel 57
+					      237	// Channel 58
+					      238	// Channel 59
+					      239	// Channel 60
+					      240	// Channel 61
+					      241	// Channel 62
+					      242>;	// Channel 63
+			};
+
+			intc: intc@fff48000 {		// Interrupt Controller (INTC)
+				compatible = "fsl,mpc5554-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0xfff48000 0x4000>;
+			};
+
+			eqadc@fff80000 {	// Enhanced Queued Analog-to-Digital Converter (eQADC)
+				compatible = "fsl,mpc5554-eqacd";
+				reg = <0xfff80000 0x4000>;
+				interrupts = <100	// Combined: Trigger Overrun, Receive FIFO Overflow, Command FIFO Underflow
+					      101	// Command FIFO 0 Non-Coherency
+					      102	// Command FIFO 0 Pause
+					      103	// Command FIFO 0 End of Queue
+					      104	// Command FIFO 0 Fill
+					      105	// Command FIFO 0 Drain
+					      106	// Command FIFO 1 Non-Coherency
+					      107	// Command FIFO 1 Pause
+					      108	// Command FIFO 1 End of Queue
+					      109	// Command FIFO 1 Fill
+					      111	// Command FIFO 1 Drain
+					      111	// Command FIFO 2 Non-Coherency
+					      112	// Command FIFO 2 Pause
+					      113	// Command FIFO 2 End of Queue
+					      114	// Command FIFO 2 Fill
+					      115	// Command FIFO 2 Drain
+					      116	// Command FIFO 3 Non-Coherency
+					      117	// Command FIFO 3 Pause
+					      118	// Command FIFO 3 End of Queue
+					      119	// Command FIFO 3 Fill
+					      120	// Command FIFO 3 Drain
+					      121	// Command FIFO 4 Non-Coherency
+					      122	// Command FIFO 4 Pause
+					      123	// Command FIFO 4 End of Queue
+					      124	// Command FIFO 4 Fill
+					      125	// Command FIFO 4 Drain
+					      126	// Command FIFO 5 Non-Coherency
+					      127	// Command FIFO 5 Pause
+					      128	// Command FIFO 5 End of Queue
+					      129	// Command FIFO 5 Fill
+					      130>;	// Command FIFO 5 Drain
+			};
+
+			dspi@fff90000 {		// Deserial Serial Peripheral Interface (DSPI_A)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff90000 0x4000>;
+				interrupts = <275	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
+					      276	// Transmit FIFO End of Queue
+					      277	// Transmit FIFO Fill Flag
+					      278	// Transfer Complete
+					      279>;	// Receive FIFO Drain
+			};
+
+			dspi@fff94000 {		// Deserial Serial Peripheral Interface (DSPI_B)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff94000 0x4000>;
+				interrupts = <131	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
+					      132	// Transmit FIFO End of Queue
+					      133	// Transmit FIFO Fill Flag
+					      134	// Transfer Complete
+					      135>;	// Receive FIFO Drain
+			};
+
+			dspi@fff98000 {		// Deserial Serial Peripheral Interface (DSPI_C)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff98000 0x4000>;
+				interrupts = <136	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
+					      137	// Transmit FIFO End of Queue
+					      138	// Transmit FIFO Fill Flag
+					      139	// Transfer Complete
+					      140>;	// Receive FIFO Drain
+			};
+
+			dspi@fff9c000 {		// Deserial Serial Peripheral Interface (DSPI_D)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff9c000 0x4000>;
+				interrupts = <141	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
+					      142	// Transmit FIFO End of Queue
+					      143	// Transmit FIFO Fill Flag
+					      144	// Transfer Complete
+					      145>;	// Receive FIFO Drain
+			};
+
+			esci@fffb0000 {		// Serial Communications Interface (SCI_A)
+				compatible = "fsl,mpc5554-esci";
+				reg = <0xfffb0000 0x4000>;
+				interrupts = <146>;	// Combined request for all SCI_A interrupts
+			};
+
+			esci@fffb4000 {		// Serial Communications Interface (SCI_B)
+				compatible = "fsl,mpc5554-esci";
+				reg = <0xfffb4000 0x4000>;
+				interrupts = <149>;	// Combined request for all SCI_A interrupts
+			};
+
+			can@fffc0000 {		// Controller Area Network (FlexCAN_A)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0xfffc0000 0x4000>;
+				interrupts = <152	// Bus off
+					      153	// Error
+					      155	// Buffer 0
+					      156	// Buffer 1
+					      157	// Buffer 2
+					      158	// Buffer 3
+					      159	// Buffer 4
+					      160	// Buffer 5
+					      161	// Buffer 6
+					      162	// Buffer 7
+					      163	// Buffer 8
+					      164	// Buffer 9
+					      165	// Buffer 10
+					      166	// Buffer 11
+					      167	// Buffer 12
+					      168	// Buffer 13
+					      169	// Buffer 14
+					      170	// Buffer 15
+					      171	// Buffers 16-31
+					      172>;	// Buffers 32-63
+			};
+
+			can@fffc4000 {		// Controller Area Network (FlexCAN_B)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0xfffc4000 0x4000>;
+				interrupts = <280	// Bus off
+					      281	// Error
+					      283	// Buffer 0
+					      284	// Buffer 1
+					      285	// Buffer 2
+					      286	// Buffer 3
+					      287	// Buffer 4
+					      288	// Buffer 5
+					      289	// Buffer 6
+					      290	// Buffer 7
+					      291	// Buffer 8
+					      292	// Buffer 9
+					      293	// Buffer 10
+					      294	// Buffer 11
+					      295	// Buffer 12
+					      296	// Buffer 13
+					      297	// Buffer 14
+					      298	// Buffer 15
+					      299	// Buffers 16-31
+					      300>;	// Buffers 32-63
+			};
+
+			can@fffc8000 {		// Controller Area Network (FlexCAN_C)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0xfffc8000 0x4000>;
+				interrupts = <173	// Bus off
+					      174	// Error
+					      176	// Buffer 0
+					      177	// Buffer 1
+					      178	// Buffer 2
+					      179	// Buffer 3
+					      180	// Buffer 4
+					      181	// Buffer 5
+					      182	// Buffer 6
+					      183	// Buffer 7
+					      184	// Buffer 8
+					      185	// Buffer 9
+					      186	// Buffer 10
+					      187	// Buffer 11
+					      188	// Buffer 12
+					      189	// Buffer 13
+					      190	// Buffer 14
+					      191	// Buffer 15
+					      192	// Buffers 16-31
+					      193>;	// Buffers 32-63
+			};
+
+			bam@ffffc000 {		// Boot Assist Module (BAM)
+				compatible = "fsl,mpc5554-bam";
+				reg = <0xffffc000 0x4000>;
+			};
+
+		};
+
+	};
+
+};

Re: Freescale MPC5554 device tree (was: cross-compiling Linux for PowerPC e200 core?)

[Grant Likely]

2010/3/22 N=E9meth M=E1rton <nm127@freemail.hu>:
> Hi Grant,
>
> thanks for the comments, I solved some of the points you mentioned. I nee=
d some
> more time to work on the others. In the meantime I send the intermediate =
version.
>
> Grant Likely wrote:
>> 2010/3/13 N=E9meth M=E1rton <nm127@freemail.hu>:
> [...]
>>> + =A0 =A0 =A0 memory@40000000 {
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 device_type =3D "memory";
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x40000000 0x10000>; =A0 =A0 // =
32KiB internal SRAM
>>> + =A0 =A0 =A0 };
>>
>> Oh.... this is the small SRAM. =A0yeah, you should move this under the
>> appropriate bridge node, remove the device_type property, and add a
>> compatible property. =A0Memory nodes at the root like this are used to
>> describe what is basically main memory (what Linux will execute out
>> of). =A0You'll want a new memory node for the external ram hooked up to
>> the 5554.
>
> Yes, it is the small one (actually 64KiB, I corrected the comment also).
> I added the external memory of the MPC5554DEMO evaluation board which has
> a size of 512KiB.

Yikes.  Half a meg is tiny for running Linux.

> Would it be possible to program the uncompressed kernel to the FLASH so
> it can run directly from there? I guess for the code and the constant sec=
tions
> the FLASH could be a good place. Then cstart has to initialize the initia=
lized
> variables by copying data from FLASH to RAM and fill the BSS area with ze=
ro.

Hmmm.  I don't know if anyone has kernel execute in place (XIP)
working on PowerPC.

>
> [...]
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 siu@3f89000 { =A0 =A0 =A0=
 =A0 =A0 // System Integration Unit
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatibl=
e =3D "fsl,mpc5554-siu";
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <=
0x03f90000 0x4000>;
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 interrupt=
s =3D <45 1 =A0 =A0 =A0// External Interrupt Overrun 0-15
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 46 1 =A0 =A0 =A0// External Interrupt 0
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 47 1 =A0 =A0 =A0// External Interrupt 1
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 48 1 =A0 =A0 =A0// External Interrupt 2
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 49 1 =A0 =A0 =A0// External Interrupt 3
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 50 1>; =A0 =A0// External Interrupt 4-15
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
>>
>> This doesn't look quite right.... /me goes to look at the 5554
>> reference manual....
>>
>> Okay, so all the external IRQs go through the SIU then, even though
>> the first 4 get passed straight through to the intc? =A0And I see that
>> all the level/edge sensing and masking/acknowledging is done at the
>> SIU level, not the intc level, correct? =A0So, what you effectively have
>> is the SIU is *another* interrupt controller that is cascaded to the
>> intc. =A0Therefore you need to add the following to this node:
>>
>> #interrupt-cells =3D <2>; =A0 // cell1:extirq#, cell2:level/edge flags
>> interrupt-controller;
>>
>> Also give the node a label so that nodes for external devices can
>> reference it for hooking up external irqs by overriding the top-level
>> interrupt-parent property.
>>
>> Also, it would appear that intc interrupts don't have any level/edge
>> configuration associated with them. =A0They are either asserted, or they
>> are not, correct? =A0At the moment you're specifying every intc
>> interrupt with 2 cells, and the 2nd cell is always '1'. =A0I think you
>> can change #interrupt-cells to <1> in the intc node and drop the '1'
>> everywhere.
>>
>> When you write your intc driver, you'll also need to write the
>> cascaded driver for the external IRQs.
>
> I tried to solve this point but I'm not quite sure whether the SIU interr=
upt
> numbers shall be kept on the siu@3f89000 node or not.

Yes, you'll want the irq numbers to remain in the siu node because
those are the 'cascade' irqs that the siu raises when the external
irqs are asserted.

>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 emios@3fa0000 { =A0 =A0 =
=A0 =A0 // Modular Timer System
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatibl=
e =3D "fsl,mpc5554-emios";
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <=
0x03fa0000 0x4000>;
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 interrupt=
s =3D <51 1 =A0 =A0 =A0// Channel 0
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 52 1 =A0 =A0 =A0// Channel 1
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 53 1 =A0 =A0 =A0// Channel 2
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 54 1 =A0 =A0 =A0// Channel 3
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 55 1 =A0 =A0 =A0// Channel 4
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 56 1 =A0 =A0 =A0// Channel 5
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 57 1 =A0 =A0 =A0// Channel 6
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 58 1 =A0 =A0 =A0// Channel 7
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 59 1 =A0 =A0 =A0// Channel 8
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 60 1 =A0 =A0 =A0// Channel 9
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 61 1 =A0 =A0 =A0// Channel 10
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 62 1 =A0 =A0 =A0// Channel 11
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 63 1 =A0 =A0 =A0// Channel 12
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 64 1 =A0 =A0 =A0// Channel 13
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 65 1 =A0 =A0 =A0// Channel 14
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 66 1 =A0 =A0 =A0// Channel 15
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 202 1 =A0 =A0 // Channel 16
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 203 1 =A0 =A0 // Channel 17
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 204 1 =A0 =A0 // Channel 18
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 205 1 =A0 =A0 // Channel 19
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 206 1 =A0 =A0 // Channel 20
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 207 1 =A0 =A0 // Channel 21
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 208 1 =A0 =A0 // Channel 22
>>> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 209 1>; =A0 // Channel 23
>>
>> These long lists bother me, but looking at the manual they seem to
>> describe the actual hardware architecture, so I think they are
>> probably fine. =A0But you may want to compact your formatting somewhat.
>> You can probably list more than one channel per
>> source line in the file.
>>
>> Ditto through the rest of the file.
>
> I would keep the list like this because in this case it is easy to find
> which comment belongs to which interrupt number. Otherwise one would need
> to count the interrupt numbers and the comment to find out which number m=
atch
> which comment.

You could do it in this style to keep the verbosity down:

      interrupts =3D <51 52 53 54 55 56 57 58  // Channels 0-7
                    59 60 61 62 63 64 65 66  // Channels 8-15
                    202 203 204 205 206 207 208 209>;  // Channel 16-23

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: Freescale MPC5554 device tree (was: cross-compiling Linux for PowerPC e200 core?)

[Németh Márton]

Grant Likely wrote:
> 2010/3/22 Németh Márton <nm127@freemail.hu>:
>> Hi Grant,
>>
>> thanks for the comments, I solved some of the points you mentioned. I need some
>> more time to work on the others. In the meantime I send the intermediate version.
>>
>> Grant Likely wrote:
>>> 2010/3/13 Németh Márton <nm127@freemail.hu>:
>> [...]
>>>> +       memory@40000000 {
>>>> +               device_type = "memory";
>>>> +               reg = <0x40000000 0x10000>;     // 32KiB internal SRAM
>>>> +       };
>>> Oh.... this is the small SRAM.  yeah, you should move this under the
>>> appropriate bridge node, remove the device_type property, and add a
>>> compatible property.  Memory nodes at the root like this are used to
>>> describe what is basically main memory (what Linux will execute out
>>> of).  You'll want a new memory node for the external ram hooked up to
>>> the 5554.
>> Yes, it is the small one (actually 64KiB, I corrected the comment also).
>> I added the external memory of the MPC5554DEMO evaluation board which has
>> a size of 512KiB.
> 
> Yikes.  Half a meg is tiny for running Linux.
> 
>> Would it be possible to program the uncompressed kernel to the FLASH so
>> it can run directly from there? I guess for the code and the constant sections
>> the FLASH could be a good place. Then cstart has to initialize the initialized
>> variables by copying data from FLASH to RAM and fill the BSS area with zero.
> 
> Hmmm.  I don't know if anyone has kernel execute in place (XIP)
> working on PowerPC.

I found some promising links for XIP on PowerPC:
 - XIP for PowerQUICC™I 8xx: http://www.denx.de/wiki/bin/view/DULG/ConfigureLinuxForXIP
 - XIP on Arctic III PowerPC board: http://simplemachines.it/xip/KernelXIP.html#head-3d70ff3a6d5599f6f98f1d4b4becc9271310967d

>> [...]
>>>> +                       siu@3f89000 {           // System Integration Unit
>>>> +                               compatible = "fsl,mpc5554-siu";
>>>> +                               reg = <0x03f90000 0x4000>;
>>>> +                               interrupts = <45 1      // External Interrupt Overrun 0-15
>>>> +                                             46 1      // External Interrupt 0
>>>> +                                             47 1      // External Interrupt 1
>>>> +                                             48 1      // External Interrupt 2
>>>> +                                             49 1      // External Interrupt 3
>>>> +                                             50 1>;    // External Interrupt 4-15
>>>> +                       };
>>> This doesn't look quite right.... /me goes to look at the 5554
>>> reference manual....
>>>
>>> Okay, so all the external IRQs go through the SIU then, even though
>>> the first 4 get passed straight through to the intc?  And I see that
>>> all the level/edge sensing and masking/acknowledging is done at the
>>> SIU level, not the intc level, correct?  So, what you effectively have
>>> is the SIU is *another* interrupt controller that is cascaded to the
>>> intc.  Therefore you need to add the following to this node:
>>>
>>> #interrupt-cells = <2>;   // cell1:extirq#, cell2:level/edge flags
>>> interrupt-controller;
>>>
>>> Also give the node a label so that nodes for external devices can
>>> reference it for hooking up external irqs by overriding the top-level
>>> interrupt-parent property.
>>>
>>> Also, it would appear that intc interrupts don't have any level/edge
>>> configuration associated with them.  They are either asserted, or they
>>> are not, correct?  At the moment you're specifying every intc
>>> interrupt with 2 cells, and the 2nd cell is always '1'.  I think you
>>> can change #interrupt-cells to <1> in the intc node and drop the '1'
>>> everywhere.
>>>
>>> When you write your intc driver, you'll also need to write the
>>> cascaded driver for the external IRQs.
>> I tried to solve this point but I'm not quite sure whether the SIU interrupt
>> numbers shall be kept on the siu@3f89000 node or not.
> 
> Yes, you'll want the irq numbers to remain in the siu node because
> those are the 'cascade' irqs that the siu raises when the external
> irqs are asserted.
> 
>>>> +                       emios@3fa0000 {         // Modular Timer System
>>>> +                               compatible = "fsl,mpc5554-emios";
>>>> +                               reg = <0x03fa0000 0x4000>;
>>>> +                               interrupts = <51 1      // Channel 0
>>>> +                                             52 1      // Channel 1
>>>> +                                             53 1      // Channel 2
>>>> +                                             54 1      // Channel 3
>>>> +                                             55 1      // Channel 4
>>>> +                                             56 1      // Channel 5
>>>> +                                             57 1      // Channel 6
>>>> +                                             58 1      // Channel 7
>>>> +                                             59 1      // Channel 8
>>>> +                                             60 1      // Channel 9
>>>> +                                             61 1      // Channel 10
>>>> +                                             62 1      // Channel 11
>>>> +                                             63 1      // Channel 12
>>>> +                                             64 1      // Channel 13
>>>> +                                             65 1      // Channel 14
>>>> +                                             66 1      // Channel 15
>>>> +                                             202 1     // Channel 16
>>>> +                                             203 1     // Channel 17
>>>> +                                             204 1     // Channel 18
>>>> +                                             205 1     // Channel 19
>>>> +                                             206 1     // Channel 20
>>>> +                                             207 1     // Channel 21
>>>> +                                             208 1     // Channel 22
>>>> +                                             209 1>;   // Channel 23
>>> These long lists bother me, but looking at the manual they seem to
>>> describe the actual hardware architecture, so I think they are
>>> probably fine.  But you may want to compact your formatting somewhat.
>>> You can probably list more than one channel per
>>> source line in the file.
>>>
>>> Ditto through the rest of the file.
>> I would keep the list like this because in this case it is easy to find
>> which comment belongs to which interrupt number. Otherwise one would need
>> to count the interrupt numbers and the comment to find out which number match
>> which comment.
> 
> You could do it in this style to keep the verbosity down:
> 
>       interrupts = <51 52 53 54 55 56 57 58  // Channels 0-7
>                     59 60 61 62 63 64 65 66  // Channels 8-15
>                     202 203 204 205 206 207 208 209>;  // Channel 16-23
> 

I compacted the different channel interrupt lists as you proposed.

The eTPU related nodes still needs improvement.

Regards,

	Márton Németh
---
From: Márton Németh <nm127@freemail.hu>

Add device tree for Freescale MPC5554.

Signed-off-by: Márton Németh <nm127@freemail.hu>
---
diff -uprN linux-2.6.33.orig/arch/powerpc/boot/dts/mpc5554.dts linux-2.6.33/arch/powerpc/boot/dts/mpc5554.dts
--- linux-2.6.33.orig/arch/powerpc/boot/dts/mpc5554.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.33/arch/powerpc/boot/dts/mpc5554.dts	2010-03-23 06:39:37.000000000 +0100
@@ -0,0 +1,313 @@
+/*
+ * Freescale MPC5554 Device Tree Source
+ *
+ * Based on MPC5553/5554 Microcontroller Reference Manual, Rev. 4.0, 04/2007
+ * http://www.freescale.com/files/32bit/doc/ref_manual/MPC5553_MPC5554_RM.pdf
+ *  - Block Diagram: page 1-3, Figure 1-1
+ *  - Memory Map: page 1-21, Table 1-2
+ *  - Interrupt Request Sources: page 10-16, Table 10-9
+ *
+ * This device tree also contains external components found on MPC5554DEMO
+ * http://www.axman.com/files/MPC5554DEMO_man_G.pdf
+ * http://www.axman.com/files/MPC5554DEMO_SCH_G.pdf
+ *
+ * Copyright 2010 Márton Németh
+ * Márton Németh <nm127@freemail.hu>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "MPC5554";
+	compatible = "fsl,MPC5554EVB";		// Freescale MPC5554 Evaluation Board
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&intc>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "PowerPC,5554", "fsl,mpc5554-e200z6", "fsl,powerpc-e200z6";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;	// L1, 32KiB
+			i-cache-size = <0x8000>;	// L1, 32KiB
+			timebase-frequency = <0>;	// from bootloader
+			bus-frequency = <0>;		// from bootloader
+			clock-frequency = <0>;		// from bootloader
+		};
+	};
+
+	memory@20000000 {
+		device_type = "memory";
+		reg = <0x20000000 0x80000>;	// 512KiB external SRAM: ISSI IS61SF12832
+		// CS0 or CS1 selectable by the SRAM_SEL jumper
+	};
+
+	xbar@fff04000 {		// System Bus Crossbar Switch (XBAR)
+		compatible = "fsl,mpc5554-xbar";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		// The full memory range is covered by XBAR
+		ranges;
+		reg = <0xfff04000 0x4000>;
+
+		flash@0 {	// read-only FLASH
+			compatible = "fsl,mpc5554-flash";
+			reg = <0x00000000 0x200000>;	// 2MiB internal FLASH
+		};
+
+		memory@40000000 {
+			compatible = "fsl,mpc5554-sram";
+			reg = <0x40000000 0x10000>;	// 64KiB internal SRAM
+		};
+
+		bridge@c3f00000 {
+			compatible = "fsl,mpc5554-pbridge-a";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0xc0000000 0x20000000>;
+			reg = <0xc3f00000 0x4000>;
+
+			fmpll@3f80000 {		// Frequency Modulated PLL
+				compatible = "fsl,mpc5554-fmpll";
+				reg = <0x03f80000 0x4000>;
+				interrupts = <43	// Loss of Clock
+					      44>;	// Loss of Lock
+			};
+
+			flashconfig@3f88000 {	// Flash Configuration
+				compatible = "fsl,mpc5554-flashconfig";
+				reg = <0x03f88000 0x4000>;
+			};
+
+			siuintc: siu@3f89000 {		// System Integration Unit
+				compatible = "fsl,mpc5554-siu";
+				reg = <0x03f90000 0x4000>;
+
+				// SIU is an interrupt controller by means that it handles
+				// the external interrupts
+				#interrupt-cells = <2>;   // cell 1: extirq#, cell 2: level/edge flags
+				interrupt-controller;
+				interrupts = <45 1	// External Interrupt Overrun 0-15
+					      46 1	// External Interrupt 0
+					      47 1	// External Interrupt 1
+					      48 1	// External Interrupt 2
+					      49 1	// External Interrupt 3
+					      50 1>;	// External Interrupt 4-15
+			};
+
+			emios@3fa0000 {		// Modular Timer System
+				compatible = "fsl,mpc5554-emios";
+				reg = <0x03fa0000 0x4000>;
+				interrupts = < 51  52  53  54  55  56  57  58	// Channels 0-7
+					       59  60  61  62  63  64  65  66	// Channels 8-15
+					      202 203 204 205 206 207 208 209>;	// Channel 16-23
+			};
+
+			etpu@3fc0000 {		// Enhanced Time Processing Unit
+				compatible = "fsl,mpc5554-etpu";
+				reg = <0x03fc0000 0x4000>;
+				interrupts = <67	// Global Exception
+					      68 69 70 71 72 73 74 75	// A Channels 0-7
+					      76 77 78 79 80 81 82 83	// A Channels 8-15
+					      84 85 86 87 88 89 90 91	// A Channels 16-23
+					      92 93 94 95 96 97 98 99	// A Channels 24-31
+					      243 244 245 256 247 248 249 250	// B Channels 0-7
+					      251 252 253 254 255 256 257 248	// B Channels 8-15
+					      259 260 261 262 263 264 265 266	// B Channels 16-23
+					      267 268 269 270 271 272 273 274>;	// B Channels 24-31
+			};
+
+			etpudata@3fc8000 {	// eTPU Shared Data Memory (Parameter RAM)
+				compatible = "fsl,mpc5554-etpudata";
+				reg = <0x03fc8000 0x4000>;
+			};
+
+			etpudata@3fcc000 {	// eTPU Shared Data Memory (Parameter RAM) mirror
+				compatible = "fsl,mpc5554-etpudata";
+				reg = <0x03fcc000 0x4000>;
+			};
+
+			etpucode@3fd0000 {		// eTPU Shared Code RAM
+				compatible = "fsl,mpc5554-etpucode";
+				reg = <0x03fd0000 0x4000>;
+			};
+		};
+
+		bridge@fff00000 {
+			compatible = "fsl,mpc5554-pbridge-b";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0xe0000000 0x20000000>;
+			reg = <0xfff00000 0x4000>;
+
+			ecsm@fff40000 {		// Error Correction Status Module (ECSM)
+				compatible = "fsl,mpc5554-ecsm";
+				reg = <0xfff40000 0x4000>;
+				interrupts = <8	// Software Watchdog Interrupt
+					      9>;	// Combined: Internal SRAM Non-Correctable Error, Flash Non-Correctable Error
+			};
+
+			edma@fff44000 {		// Enhanced DMA Controller (eDMA)
+				compatible = "fsl,mpc5554-edma";
+				reg = <0xfff44000 0x4000>;
+				interrupts = <10				// Channel Error 0-31
+					      11 12 13 14 15 16 17 18		// Channels 0-7
+					      19 20 21 22 23 24 25 26		// Channels 8-15
+					      27 28 29 30 31 32 33 34		// Channels 16-23
+					      35 36 37 38 39 40 41 42		// Channels 24-31
+					      210				// Channel Error 32-63
+					      211 212 213 214 215 216 217 218	// Channels 32-39
+					      219 220 221 222 223 224 225 226	// Channels 40-47
+					      227 228 229 230 231 232 233 234	// Channels 48-55
+					      235 236 237 238 239 240 241 242>;	// Channels 56-63
+			};
+
+			intc: intc@fff48000 {		// Interrupt Controller (INTC)
+				compatible = "fsl,mpc5554-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0xfff48000 0x4000>;
+			};
+
+			eqadc@fff80000 {	// Enhanced Queued Analog-to-Digital Converter (eQADC)
+				compatible = "fsl,mpc5554-eqacd";
+				reg = <0xfff80000 0x4000>;
+				interrupts = <100	// Combined: Trigger Overrun, Receive FIFO Overflow, Command FIFO Underflow
+					      101	// Command FIFO 0 Non-Coherency
+					      102	// Command FIFO 0 Pause
+					      103	// Command FIFO 0 End of Queue
+					      104	// Command FIFO 0 Fill
+					      105	// Command FIFO 0 Drain
+					      106	// Command FIFO 1 Non-Coherency
+					      107	// Command FIFO 1 Pause
+					      108	// Command FIFO 1 End of Queue
+					      109	// Command FIFO 1 Fill
+					      111	// Command FIFO 1 Drain
+					      111	// Command FIFO 2 Non-Coherency
+					      112	// Command FIFO 2 Pause
+					      113	// Command FIFO 2 End of Queue
+					      114	// Command FIFO 2 Fill
+					      115	// Command FIFO 2 Drain
+					      116	// Command FIFO 3 Non-Coherency
+					      117	// Command FIFO 3 Pause
+					      118	// Command FIFO 3 End of Queue
+					      119	// Command FIFO 3 Fill
+					      120	// Command FIFO 3 Drain
+					      121	// Command FIFO 4 Non-Coherency
+					      122	// Command FIFO 4 Pause
+					      123	// Command FIFO 4 End of Queue
+					      124	// Command FIFO 4 Fill
+					      125	// Command FIFO 4 Drain
+					      126	// Command FIFO 5 Non-Coherency
+					      127	// Command FIFO 5 Pause
+					      128	// Command FIFO 5 End of Queue
+					      129	// Command FIFO 5 Fill
+					      130>;	// Command FIFO 5 Drain
+			};
+
+			dspi@fff90000 {		// Deserial Serial Peripheral Interface (DSPI_A)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff90000 0x4000>;
+				interrupts = <275	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
+					      276	// Transmit FIFO End of Queue
+					      277	// Transmit FIFO Fill Flag
+					      278	// Transfer Complete
+					      279>;	// Receive FIFO Drain
+			};
+
+			dspi@fff94000 {		// Deserial Serial Peripheral Interface (DSPI_B)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff94000 0x4000>;
+				interrupts = <131	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
+					      132	// Transmit FIFO End of Queue
+					      133	// Transmit FIFO Fill Flag
+					      134	// Transfer Complete
+					      135>;	// Receive FIFO Drain
+			};
+
+			dspi@fff98000 {		// Deserial Serial Peripheral Interface (DSPI_C)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff98000 0x4000>;
+				interrupts = <136	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
+					      137	// Transmit FIFO End of Queue
+					      138	// Transmit FIFO Fill Flag
+					      139	// Transfer Complete
+					      140>;	// Receive FIFO Drain
+			};
+
+			dspi@fff9c000 {		// Deserial Serial Peripheral Interface (DSPI_D)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff9c000 0x4000>;
+				interrupts = <141	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
+					      142	// Transmit FIFO End of Queue
+					      143	// Transmit FIFO Fill Flag
+					      144	// Transfer Complete
+					      145>;	// Receive FIFO Drain
+			};
+
+			esci@fffb0000 {		// Serial Communications Interface (SCI_A)
+				compatible = "fsl,mpc5554-esci";
+				reg = <0xfffb0000 0x4000>;
+				interrupts = <146>;	// Combined request for all SCI_A interrupts
+			};
+
+			esci@fffb4000 {		// Serial Communications Interface (SCI_B)
+				compatible = "fsl,mpc5554-esci";
+				reg = <0xfffb4000 0x4000>;
+				interrupts = <149>;	// Combined request for all SCI_A interrupts
+			};
+
+			can@fffc0000 {		// Controller Area Network (FlexCAN_A)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0xfffc0000 0x4000>;
+				interrupts = <152				// Bus off
+					      153				// Error
+					      155 156 157 158 159 160 161 162	// Buffers 0-7
+					      163 164 165 166 167 168 169 170	// Buffers 8-15
+					      171				// Buffers 16-31
+					      172>;				// Buffers 32-63
+			};
+
+			can@fffc4000 {		// Controller Area Network (FlexCAN_B)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0xfffc4000 0x4000>;
+				interrupts = <280				// Bus off
+					      281				// Error
+					      283 284 285 186 287 288 289 290	// Buffers 0-7
+					      291 292 293 294 295 296 297 298	// Buffers 8-15
+					      299				// Buffers 16-31
+					      300>;				// Buffers 32-63
+			};
+
+			can@fffc8000 {		// Controller Area Network (FlexCAN_C)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0xfffc8000 0x4000>;
+				interrupts = <173				// Bus off
+					      174				// Error
+					      176 177 178 179 180 181 182 183	// Buffers 0-7
+					      184 185 186 187 188 189 190 191	// Buffers 8-15
+					      192				// Buffers 16-31
+					      193>;				// Buffers 32-63
+			};
+
+			bam@ffffc000 {		// Boot Assist Module (BAM)
+				compatible = "fsl,mpc5554-bam";
+				reg = <0xffffc000 0x4000>;
+			};
+
+		};
+
+	};
+
+};

Re: Freescale MPC5554 device tree (was: cross-compiling Linux for PowerPC e200 core?)

[Németh Márton]

Hi,

Grant Likely wrote:
> 2010/3/13 Németh Márton <nm127@freemail.hu>:
[...]
>> +                       };
>> +
>> +                       etpu@3fc0000 {          // Enhanced Time Processing Unit
>> +                               compatible = "fsl,mpc5554-etpu";
>> +                               reg = <0x03fc0000 0x4000>;
>> +                               interrupts = <67 1      // Global Exception
>> +                                             68 1      // A Channel 0
>> +                                             69 1      // A Channel 1
>> +                                             70 1      // A Channel 2
>> +                                             71 1      // A Channel 3
>> +                                             72 1      // A Channel 4
>> +                                             73 1      // A Channel 5
>> +                                             74 1      // A Channel 6
>> +                                             75 1      // A Channel 7
>> +                                             76 1      // A Channel 8
>> +                                             77 1      // A Channel 9
>> +                                             78 1      // A Channel 10
>> +                                             79 1      // A Channel 11
>> +                                             80 1      // A Channel 12
>> +                                             81 1      // A Channel 13
>> +                                             82 1      // A Channel 14
>> +                                             83 1      // A Channel 15
>> +                                             84 1      // A Channel 16
>> +                                             85 1      // A Channel 17
>> +                                             86 1      // A Channel 18
>> +                                             87 1      // A Channel 19
>> +                                             88 1      // A Channel 20
>> +                                             89 1      // A Channel 21
>> +                                             90 1      // A Channel 22
>> +                                             91 1      // A Channel 23
>> +                                             92 1      // A Channel 24
>> +                                             93 1      // A Channel 25
>> +                                             94 1      // A Channel 26
>> +                                             95 1      // A Channel 27
>> +                                             96 1      // A Channel 28
>> +                                             97 1      // A Channel 29
>> +                                             98 1      // A Channel 30
>> +                                             99 1      // A Channel 31
>> +                                             243 1     // B Channel 0
>> +                                             244 1     // B Channel 1
>> +                                             245 1     // B Channel 2
>> +                                             246 1     // B Channel 3
>> +                                             247 1     // B Channel 4
>> +                                             248 1     // B Channel 5
>> +                                             249 1     // B Channel 6
>> +                                             250 1     // B Channel 7
>> +                                             251 1     // B Channel 8
>> +                                             252 1     // B Channel 9
>> +                                             253 1     // B Channel 10
>> +                                             254 1     // B Channel 11
>> +                                             255 1     // B Channel 12
>> +                                             256 1     // B Channel 13
>> +                                             257 1     // B Channel 14
>> +                                             258 1     // B Channel 15
>> +                                             259 1     // B Channel 16
>> +                                             260 1     // B Channel 17
>> +                                             261 1     // B Channel 18
>> +                                             262 1     // B Channel 19
>> +                                             263 1     // B Channel 20
>> +                                             264 1     // B Channel 21
>> +                                             265 1     // B Channel 22
>> +                                             266 1     // B Channel 23
>> +                                             267 1     // B Channel 24
>> +                                             268 1     // B Channel 25
>> +                                             269 1     // B Channel 26
>> +                                             270 1     // B Channel 27
>> +                                             271 1     // B Channel 28
>> +                                             272 1     // B Channel 29
>> +                                             273 1     // B Channel 30
>> +                                             274 1>;   // B Channel 31
>
> Are A and B two instances of the same hardware block?  Consider having
> a subnode for each instance to give some logical separation to this
> list and associate register ranges with instances.  Doing it that way
> also makes it easier for external device nodes to describe an
> attachment to a particular channel.
>
>> +                       };
>> +
>> +                       etpudata@3fc8000 {      // eTPU Shared Data Memory (Parameter RAM)
>> +                               compatible = "fsl,mpc5554-etpudata";
>> +                               reg = <0x03fc8000 0x4000>;
>> +                       };
>> +
>> +                       etpudata@3fcc000 {      // eTPU Shared Data Memory (Parameter RAM) mirror
>> +                               compatible = "fsl,mpc5554-etpudata";
>> +                               reg = <0x03fcc000 0x4000>;
>> +                       };
>> +
>> +                       etpucode@3fd0000 {              // eTPU Shared Code RAM
>> +                               compatible = "fsl,mpc5554-etpucode";
>> +                               reg = <0x03fd0000 0x4000>;
>> +                       };
>
> Should all this etpu stuff be part of the etpu node?

With this version of MPC5554 device tree I try to improve the eTPU
related node. The Table 18-6 on page 18-15 in the
http://www.freescale.com/files/32bit/doc/ref_manual/MPC5553_MPC5554_RM.pdf
shows the detailed memory map of the eTPU. What is visible is that the
eTPU A and eTPU B is interleaved in the memory map. For example ETPU_ECR_A
is at Base + 0x0_0014 while ETPU_ECR_B is at Base + 0x0_0018. Then comes a
register set for time base configuration: ETPU_TBCR_A is at Base + 0x0_0020,
and ETPU_TBCR_B is at Base + 0x0_0040. As you can see the eTPU A and eTPU B
registers are not just shifted by a fixed offset but comes interleaved
according to the hardware designer wish.

How can the multiple register ranges be expressed in device tree?

Regards,

	Márton Németh

---
From: Márton Németh <nm127@freemail.hu>

Add device tree for Freescale MPC5554.

Signed-off-by: Márton Németh <nm127@freemail.hu>
---
diff -uprN linux-2.6.33.orig/arch/powerpc/boot/dts//mpc5554.dts linux-2.6.33/arch/powerpc/boot/dts/mpc5554.dts
--- linux-2.6.33.orig/arch/powerpc/boot/dts//mpc5554.dts	1970-01-01 01:00:00.000000000 +0100
+++ linux-2.6.33/arch/powerpc/boot/dts/mpc5554.dts	2010-03-30 08:17:06.000000000 +0200
@@ -0,0 +1,321 @@
+/*
+ * Freescale MPC5554 Device Tree Source
+ *
+ * Based on MPC5553/5554 Microcontroller Reference Manual, Rev. 4.0, 04/2007
+ * http://www.freescale.com/files/32bit/doc/ref_manual/MPC5553_MPC5554_RM.pdf
+ *  - Block Diagram: page 1-3, Figure 1-1
+ *  - Memory Map: page 1-21, Table 1-2
+ *  - Interrupt Request Sources: page 10-16, Table 10-9
+ *
+ * This device tree also contains external components found on MPC5554DEMO
+ * http://www.axman.com/files/MPC5554DEMO_man_G.pdf
+ * http://www.axman.com/files/MPC5554DEMO_SCH_G.pdf
+ *
+ * Copyright 2010 Márton Németh
+ * Márton Németh <nm127@freemail.hu>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+
+/ {
+	model = "MPC5554";
+	compatible = "fsl,MPC5554EVB";		// Freescale MPC5554 Evaluation Board
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&intc>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "PowerPC,5554", "fsl,mpc5554-e200z6", "fsl,powerpc-e200z6";
+			reg = <0>;
+			d-cache-line-size = <32>;
+			i-cache-line-size = <32>;
+			d-cache-size = <0x8000>;	// L1, 32KiB
+			i-cache-size = <0x8000>;	// L1, 32KiB
+			timebase-frequency = <0>;	// from bootloader
+			bus-frequency = <0>;		// from bootloader
+			clock-frequency = <0>;		// from bootloader
+		};
+	};
+
+	memory@20000000 {
+		device_type = "memory";
+		reg = <0x20000000 0x80000>;	// 512KiB external SRAM: ISSI IS61SF12832
+		// CS0 or CS1 selectable by the SRAM_SEL jumper
+	};
+
+	xbar@fff04000 {		// System Bus Crossbar Switch (XBAR)
+		compatible = "fsl,mpc5554-xbar";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		// The full memory range is covered by XBAR
+		ranges;
+		reg = <0xfff04000 0x4000>;
+
+		flash@0 {	// read-only FLASH
+			compatible = "fsl,mpc5554-flash";
+			reg = <0x00000000 0x200000>;	// 2MiB internal FLASH
+		};
+
+		memory@40000000 {
+			compatible = "fsl,mpc5554-sram";
+			reg = <0x40000000 0x10000>;	// 64KiB internal SRAM
+		};
+
+		bridge@c3f00000 {
+			compatible = "fsl,mpc5554-pbridge-a";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0xc0000000 0x20000000>;
+			reg = <0xc3f00000 0x4000>;
+
+			fmpll@3f80000 {		// Frequency Modulated PLL
+				compatible = "fsl,mpc5554-fmpll";
+				reg = <0x03f80000 0x4000>;
+				interrupts = <43	// Loss of Clock
+					      44>;	// Loss of Lock
+			};
+
+			flashconfig@3f88000 {	// Flash Configuration
+				compatible = "fsl,mpc5554-flashconfig";
+				reg = <0x03f88000 0x4000>;
+			};
+
+			siuintc: siu@3f89000 {		// System Integration Unit
+				compatible = "fsl,mpc5554-siu";
+				reg = <0x03f90000 0x4000>;
+
+				// SIU is an interrupt controller by means that it handles
+				// the external interrupts
+				#interrupt-cells = <2>;   // cell 1: extirq#, cell 2: level/edge flags
+				interrupt-controller;
+				interrupts = <45 1	// External Interrupt Overrun 0-15
+					      46 1	// External Interrupt 0
+					      47 1	// External Interrupt 1
+					      48 1	// External Interrupt 2
+					      49 1	// External Interrupt 3
+					      50 1>;	// External Interrupt 4-15
+			};
+
+			emios@3fa0000 {		// Modular Timer System
+				compatible = "fsl,mpc5554-emios";
+				reg = <0x03fa0000 0x4000>;
+				interrupts = < 51  52  53  54  55  56  57  58	// Channels 0-7
+					       59  60  61  62  63  64  65  66	// Channels 8-15
+					      202 203 204 205 206 207 208 209>;	// Channel 16-23
+			};
+
+			etpu@3fc0000 {		// Enhanced Time Processing Unit
+				compatible = "fsl,mpc5554-etpu";
+				reg = <0x03fc0000 0x4000>;
+				interrupts = <67>;	// Global Exception
+
+				etpuengine@3fc0014 {	// eTPU Engine A
+					compatible = "fsl,mpc5554-etpuengine";
+					interrupts = <68 69 70 71 72 73 74 75	// A Channels 0-7
+						      76 77 78 79 80 81 82 83	// A Channels 8-15
+						      84 85 86 87 88 89 90 91	// A Channels 16-23
+						      92 93 94 95 96 97 98 99	// A Channels 24-31
+				};
+
+				etpuengine@3fc0018 {	// eTPU Engine B
+					compatible = "fsl,mpc5554-etpuengine";
+					interrupts = <243 244 245 256 247 248 249 250	// B Channels 0-7
+						      251 252 253 254 255 256 257 248	// B Channels 8-15
+						      259 260 261 262 263 264 265 266	// B Channels 16-23
+						      267 268 269 270 271 272 273 274>;	// B Channels 24-31
+				};
+
+				etpudata@3fc8000 {	// eTPU Shared Data Memory (Parameter RAM)
+					compatible = "fsl,mpc5554-etpudata";
+					reg = <0x03fc8000 0x4000>;	// 3 KiB
+				};
+
+				etpudata@3fcc000 {	// eTPU Shared Data Memory (Parameter RAM) mirror
+					compatible = "fsl,mpc5554-etpudata";
+					reg = <0x03fcc000 0x4000>;	// 3 KiB
+				};
+
+				etpucode@3fd0000 {		// eTPU Shared Code RAM
+					compatible = "fsl,mpc5554-etpucode";
+					reg = <0x03fd0000 0x4000>;	// 16 KiB
+				};
+			};
+		};
+
+		bridge@fff00000 {
+			compatible = "fsl,mpc5554-pbridge-b";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0 0xe0000000 0x20000000>;
+			reg = <0xfff00000 0x4000>;
+
+			ecsm@fff40000 {		// Error Correction Status Module (ECSM)
+				compatible = "fsl,mpc5554-ecsm";
+				reg = <0xfff40000 0x4000>;
+				interrupts = <8	// Software Watchdog Interrupt
+					      9>;	// Combined: Internal SRAM Non-Correctable Error, Flash Non-Correctable Error
+			};
+
+			edma@fff44000 {		// Enhanced DMA Controller (eDMA)
+				compatible = "fsl,mpc5554-edma";
+				reg = <0xfff44000 0x4000>;
+				interrupts = <10				// Channel Error 0-31
+					      11 12 13 14 15 16 17 18		// Channels 0-7
+					      19 20 21 22 23 24 25 26		// Channels 8-15
+					      27 28 29 30 31 32 33 34		// Channels 16-23
+					      35 36 37 38 39 40 41 42		// Channels 24-31
+					      210				// Channel Error 32-63
+					      211 212 213 214 215 216 217 218	// Channels 32-39
+					      219 220 221 222 223 224 225 226	// Channels 40-47
+					      227 228 229 230 231 232 233 234	// Channels 48-55
+					      235 236 237 238 239 240 241 242>;	// Channels 56-63
+			};
+
+			intc: intc@fff48000 {		// Interrupt Controller (INTC)
+				compatible = "fsl,mpc5554-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				reg = <0xfff48000 0x4000>;
+			};
+
+			eqadc@fff80000 {	// Enhanced Queued Analog-to-Digital Converter (eQADC)
+				compatible = "fsl,mpc5554-eqacd";
+				reg = <0xfff80000 0x4000>;
+				interrupts = <100	// Combined: Trigger Overrun, Receive FIFO Overflow, Command FIFO Underflow
+					      101	// Command FIFO 0 Non-Coherency
+					      102	// Command FIFO 0 Pause
+					      103	// Command FIFO 0 End of Queue
+					      104	// Command FIFO 0 Fill
+					      105	// Command FIFO 0 Drain
+					      106	// Command FIFO 1 Non-Coherency
+					      107	// Command FIFO 1 Pause
+					      108	// Command FIFO 1 End of Queue
+					      109	// Command FIFO 1 Fill
+					      111	// Command FIFO 1 Drain
+					      111	// Command FIFO 2 Non-Coherency
+					      112	// Command FIFO 2 Pause
+					      113	// Command FIFO 2 End of Queue
+					      114	// Command FIFO 2 Fill
+					      115	// Command FIFO 2 Drain
+					      116	// Command FIFO 3 Non-Coherency
+					      117	// Command FIFO 3 Pause
+					      118	// Command FIFO 3 End of Queue
+					      119	// Command FIFO 3 Fill
+					      120	// Command FIFO 3 Drain
+					      121	// Command FIFO 4 Non-Coherency
+					      122	// Command FIFO 4 Pause
+					      123	// Command FIFO 4 End of Queue
+					      124	// Command FIFO 4 Fill
+					      125	// Command FIFO 4 Drain
+					      126	// Command FIFO 5 Non-Coherency
+					      127	// Command FIFO 5 Pause
+					      128	// Command FIFO 5 End of Queue
+					      129	// Command FIFO 5 Fill
+					      130>;	// Command FIFO 5 Drain
+			};
+
+			dspi@fff90000 {		// Deserial Serial Peripheral Interface (DSPI_A)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff90000 0x4000>;
+				interrupts = <275	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
+					      276	// Transmit FIFO End of Queue
+					      277	// Transmit FIFO Fill Flag
+					      278	// Transfer Complete
+					      279>;	// Receive FIFO Drain
+			};
+
+			dspi@fff94000 {		// Deserial Serial Peripheral Interface (DSPI_B)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff94000 0x4000>;
+				interrupts = <131	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
+					      132	// Transmit FIFO End of Queue
+					      133	// Transmit FIFO Fill Flag
+					      134	// Transfer Complete
+					      135>;	// Receive FIFO Drain
+			};
+
+			dspi@fff98000 {		// Deserial Serial Peripheral Interface (DSPI_C)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff98000 0x4000>;
+				interrupts = <136	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
+					      137	// Transmit FIFO End of Queue
+					      138	// Transmit FIFO Fill Flag
+					      139	// Transfer Complete
+					      140>;	// Receive FIFO Drain
+			};
+
+			dspi@fff9c000 {		// Deserial Serial Peripheral Interface (DSPI_D)
+				compatible = "fsl,mpc5554-dspi";
+				reg = <0xfff9c000 0x4000>;
+				interrupts = <141	// Combined: Transmit FIFO Underflow, Receive FIFO Overflow
+					      142	// Transmit FIFO End of Queue
+					      143	// Transmit FIFO Fill Flag
+					      144	// Transfer Complete
+					      145>;	// Receive FIFO Drain
+			};
+
+			esci@fffb0000 {		// Serial Communications Interface (SCI_A)
+				compatible = "fsl,mpc5554-esci";
+				reg = <0xfffb0000 0x4000>;
+				interrupts = <146>;	// Combined request for all SCI_A interrupts
+			};
+
+			esci@fffb4000 {		// Serial Communications Interface (SCI_B)
+				compatible = "fsl,mpc5554-esci";
+				reg = <0xfffb4000 0x4000>;
+				interrupts = <149>;	// Combined request for all SCI_A interrupts
+			};
+
+			can@fffc0000 {		// Controller Area Network (FlexCAN_A)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0xfffc0000 0x4000>;
+				interrupts = <152				// Bus off
+					      153				// Error
+					      155 156 157 158 159 160 161 162	// Buffers 0-7
+					      163 164 165 166 167 168 169 170	// Buffers 8-15
+					      171				// Buffers 16-31
+					      172>;				// Buffers 32-63
+			};
+
+			can@fffc4000 {		// Controller Area Network (FlexCAN_B)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0xfffc4000 0x4000>;
+				interrupts = <280				// Bus off
+					      281				// Error
+					      283 284 285 186 287 288 289 290	// Buffers 0-7
+					      291 292 293 294 295 296 297 298	// Buffers 8-15
+					      299				// Buffers 16-31
+					      300>;				// Buffers 32-63
+			};
+
+			can@fffc8000 {		// Controller Area Network (FlexCAN_C)
+				compatible = "fsl,mpc5554-flexcan";
+				reg = <0xfffc8000 0x4000>;
+				interrupts = <173				// Bus off
+					      174				// Error
+					      176 177 178 179 180 181 182 183	// Buffers 0-7
+					      184 185 186 187 188 189 190 191	// Buffers 8-15
+					      192				// Buffers 16-31
+					      193>;				// Buffers 32-63
+			};
+
+			bam@ffffc000 {		// Boot Assist Module (BAM)
+				compatible = "fsl,mpc5554-bam";
+				reg = <0xffffc000 0x4000>;
+			};
+
+		};
+
+	};
+
+};