From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1O2Uij-000402-GY for qemu-devel@nongnu.org; Thu, 15 Apr 2010 15:27:25 -0400 Received: from [140.186.70.92] (port=56026 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1O2Uii-0003xV-1p for qemu-devel@nongnu.org; Thu, 15 Apr 2010 15:27:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1O2Uih-0000fu-1K for qemu-devel@nongnu.org; Thu, 15 Apr 2010 15:27:23 -0400 Received: from mail-pz0-f204.google.com ([209.85.222.204]:39120) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1O2Uig-0000fd-SB for qemu-devel@nongnu.org; Thu, 15 Apr 2010 15:27:22 -0400 Received: by pzk42 with SMTP id 42so1428370pzk.4 for ; Thu, 15 Apr 2010 12:27:21 -0700 (PDT) Sender: Richard Henderson Message-ID: <4BC76887.5060300@twiddle.net> Date: Thu, 15 Apr 2010 14:27:03 -0500 From: Richard Henderson MIME-Version: 1.0 Subject: Re: [Qemu-devel] Re: [RfC PATCH 08/11] spice: add qxl device References: <1271238922-10008-1-git-send-email-kraxel@redhat.com> <1271238922-10008-9-git-send-email-kraxel@redhat.com> <4BC64AD6.6040209@redhat.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com, kraxel@redhat.com On 04/15/2010 11:47 AM, Blue Swirl wrote: > On 4/15/10, Paolo Bonzini wrote: >> On 04/14/2010 06:52 PM, Blue Swirl wrote: >> >>> On 4/14/10, Gerd Hoffmann wrote: >>> >>>> +static inline void atomic_or(uint32_t *var, uint32_t add) >>>> +{ >>>> + __asm__ __volatile__ ("lock; orl %1, %0" : "+m" (*var) : "r" (add) >> : "memory"); >>>> +} >>>> >>> >>> This will break on non-x86 hosts. >>> >> >> I'd just use __sync_fetch_and_or here. > > And on environments without __sync_fetch_and_or? Where is that available? GCC will provide it for capable cpus. So sparcv9 has it via CAS. For less capable cpus, there may be cooperation with the system in some way. For instance, ARM, SH, and HPPA Linux kernels all provide various mechanisms to implement atomic sequences. The result continues to be provided by GCC in the form of entry points in libgcc.so. For less capable cpus with no system support... well, the program itself needs to figure out what an appropriate response should be. I haven't gone back to look at the context from which this snippet was taken to know if a locally defined mutex would be adequate. In either case, some configure tests that detect when various forms of atomic operations are available in the host compiler would not be amiss. r~