Re: [PATCH -v2] x86, pci: Handle fallout pci devices with peer root bus

[Yinghai Lu <yinghai.lu@oracle.com>]

On 06/14/2010 11:39 AM, H. Peter Anvin wrote:
> On 06/14/2010 11:34 AM, Bjorn Helgaas wrote:
>>
>> I made the point there that an HT chain may contain multiple HT/PCI
>> host bridges, but you are stuck on the idea that "one HT chain == one
>> PCI root bus."

should be.

>>
>> I have not found the "one PCI host bridge per HT chain" requirement
>> in the HT spec (if you find it, please point me to it).

according to my experience with LinuxBIOS. AMD chipset, nvidia and serverworks (broadcom)

>>
>> If an HT chain may contain multiple HT/PCI host bridges, then it's
>> obvious that the HT host bridge registers read by amd_bus.c don't
>> contain enough information to correctly assign address space to the
>> PCI root buses.

the host bridges is on AMD CPUs, 

>>
> 
> A HT-to-PCI bridge appears as a PCI-to-PCI bridge (i.e. a Header Type 1
> device), not as a host bridge (a Header Type 0 device).
> 
> That is at least the software model as defined.

one HT chain could have some HT devices, HT devices could be HT tunnel or HT bridge.

If it is HT tunnel, the next device will use same primary pci bus number with some addon device number.
It it is HT bridge, will like some kind pci-to-pci bridge.

link between KT890 and vt32551? is some kind va-link? it is not HT between them

somehow the southbridge vt32551 respond the sound_intel from 80:01.0... and it is supposed to be under some pci bridge.

YH