From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wy0-f174.google.com ([74.125.82.174]:51077 "EHLO mail-wy0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755070Ab0F2TDV (ORCPT ); Tue, 29 Jun 2010 15:03:21 -0400 Received: by wyb38 with SMTP id 38so2971977wyb.19 for ; Tue, 29 Jun 2010 12:03:20 -0700 (PDT) Message-ID: <4C2A4376.9050602@gmail.com> Date: Tue, 29 Jun 2010 21:03:18 +0200 From: Martijn Stolk MIME-Version: 1.0 Subject: Re: QSD8250 illegal instruction on WinCE devices References: <20100622011413.awcghidf4s8wkwwg@webmail.htc-linux.org> <20100627225011.9a3evahodco80s8s@webmail.htc-linux.org> <1277746481.5186.9.camel@m0nster> <4C29212F.4060709@gmail.com> <1277830196.30743.1.camel@c-dwalke-linux.qualcomm.com> In-Reply-To: <1277830196.30743.1.camel@c-dwalke-linux.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-arm-msm-owner@vger.kernel.org List-ID: To: linux-arm-msm@vger.kernel.org No worries. I wanted to isolate what specifically fixes the problem myself in order to make a minimal patch. I'm also hoping for some help regarding information, as I don't have access to official QSD8250 documentation. I've found the key register that differs between between how it is initialized for Windows CE and for Linux, and solves the problem for us. It is the Auxilliary Control Register (cp15, 0, c1, c0, 1). For Windows CE it is initialized to 0x002C0077 (=0b00000000001011000000000001110111) For Linux it is initialized to 0x000C0037 (=0b00000000000011000000000000110111) The following page explains this register for the Cortex-A8, the ARM core on which the QSD8250 is based: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344k/Bgbffjhh.html The 7th bit (bit 6 on that page) controls the behaviour of the Invalidate All & by MVA instructions. It needs to be disabled for Linux. The 22nd bit, however, is in an area marked as "reserved" on that page. I am very curious what this bit does. Maybe this reserved area is documented in QSD8250 documentation? Could anyone provide clearity about this bit? In conclusion, we are able to continue our work using the following asm, but do not know what the second flag means: MRC p15, 0, r0, c1, c0, 1 BIC r0, #0x40 BIC r0, #0x200000 MCR p15, 0, r0, c1, c0, 1 Thanks in advance for any information. Regards, Martijn On 06/29/2010 06:49 PM, Daniel Walker wrote: > > Don't do it on my account, I was just wondering if that was discovered.. > > Daniel >