* [PATCH v3 1/2] net: phy: dp83867: Add binding for the CLK_OUT pin muxing option
@ 2018-02-14 16:07 Daniel Schultz
2018-02-14 16:07 ` [PATCH v3 2/2] net: phy: dp83867: Add documentation for CLK_OUT pin muxing Daniel Schultz
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Daniel Schultz @ 2018-02-14 16:07 UTC (permalink / raw)
To: robh+dt, mark.rutland, andrew, f.fainelli, netdev, devicetree,
linux-kernel
Cc: w.egorov
From: Wadim Egorov <w.egorov@phytec.de>
The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
---
Changes:
v2:
Added check if clk_output_sel has a valid value
Only write the clock ouput register if a musing is desired
v3:
-
drivers/net/phy/dp83867.c | 19 +++++++++++++++++++
include/dt-bindings/net/ti-dp83867.h | 14 ++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
index c1ab976..a862194 100644
--- a/drivers/net/phy/dp83867.c
+++ b/drivers/net/phy/dp83867.c
@@ -75,6 +75,8 @@
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
+#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
+#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
/* CFG4 bits */
#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
@@ -92,6 +94,7 @@ struct dp83867_private {
int io_impedance;
int port_mirroring;
bool rxctrl_strap_quirk;
+ int clk_output_sel;
};
static int dp83867_ack_interrupt(struct phy_device *phydev)
@@ -160,6 +163,14 @@ static int dp83867_of_init(struct phy_device *phydev)
dp83867->io_impedance = -EINVAL;
/* Optional configuration */
+ ret = of_property_read_u32(of_node, "ti,clk-output-sel",
+ &dp83867->clk_output_sel);
+ if (ret || dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK)
+ /* Keep the default value if ti,clk-output-sel is not set
+ * or too high
+ */
+ dp83867->clk_output_sel = DP83867_CLK_O_SEL_REF_CLK;
+
if (of_property_read_bool(of_node, "ti,max-output-impedance"))
dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
@@ -295,6 +306,14 @@ static int dp83867_config_init(struct phy_device *phydev)
if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
dp83867_config_port_mirroring(phydev);
+ /* Clock output selection if muxing property is set */
+ if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
+ val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG);
+ val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
+ val |= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
+ phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val);
+ }
+
return 0;
}
diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h
index 172744a..7b16564 100644
--- a/include/dt-bindings/net/ti-dp83867.h
+++ b/include/dt-bindings/net/ti-dp83867.h
@@ -42,4 +42,18 @@
#define DP83867_RGMIIDCTL_3_75_NS 0xe
#define DP83867_RGMIIDCTL_4_00_NS 0xf
+/* IO_MUX_CFG - Clock output selection */
+#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0
+#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1
+#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2
+#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3
+#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4
+#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5
+#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6
+#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7
+#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8
+#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9
+#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA
+#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB
+#define DP83867_CLK_O_SEL_REF_CLK 0xC
#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v3 2/2] net: phy: dp83867: Add documentation for CLK_OUT pin muxing
2018-02-14 16:07 [PATCH v3 1/2] net: phy: dp83867: Add binding for the CLK_OUT pin muxing option Daniel Schultz
@ 2018-02-14 16:07 ` Daniel Schultz
2018-02-14 17:06 ` Florian Fainelli
2018-02-14 20:34 ` David Miller
2018-02-14 16:14 ` Andrew Lunn
` (2 subsequent siblings)
3 siblings, 2 replies; 10+ messages in thread
From: Daniel Schultz @ 2018-02-14 16:07 UTC (permalink / raw)
To: robh+dt, mark.rutland, andrew, f.fainelli, netdev, devicetree,
linux-kernel
Cc: w.egorov
From: Wadim Egorov <w.egorov@phytec.de>
Add documentation of ti,clk-output-sel which can be used to select
a specific clock for CLK_OUT.
Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
---
Changes:
v2:
-
v3:
Fixed indentation.
Documentation/devicetree/bindings/net/ti,dp83867.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/ti,dp83867.txt b/Documentation/devicetree/bindings/net/ti,dp83867.txt
index 02c4353..9ef9338 100644
--- a/Documentation/devicetree/bindings/net/ti,dp83867.txt
+++ b/Documentation/devicetree/bindings/net/ti,dp83867.txt
@@ -25,6 +25,8 @@ Optional property:
software needs to take when this pin is
strapped in these modes. See data manual
for details.
+ - ti,clk-output-sel - Muxing option for CLK_OUT pin - see dt-bindings/net/ti-dp83867.h
+ for applicable values.
Note: ti,min-output-impedance and ti,max-output-impedance are mutually
exclusive. When both properties are present ti,max-output-impedance
--
2.7.4
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v3 1/2] net: phy: dp83867: Add binding for the CLK_OUT pin muxing option
@ 2018-02-14 16:14 ` Andrew Lunn
0 siblings, 0 replies; 10+ messages in thread
From: Andrew Lunn @ 2018-02-14 16:14 UTC (permalink / raw)
To: Daniel Schultz
Cc: robh+dt, mark.rutland, f.fainelli, netdev, devicetree,
linux-kernel, w.egorov
On Wed, Feb 14, 2018 at 05:07:11PM +0100, Daniel Schultz wrote:
> From: Wadim Egorov <w.egorov@phytec.de>
>
> The DP83867 has a muxing option for the CLK_OUT pin. It is possible
> to set CLK_OUT for different channels.
> Create a binding to select a specific clock for CLK_OUT pin.
>
> Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
> Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 1/2] net: phy: dp83867: Add binding for the CLK_OUT pin muxing option
@ 2018-02-14 16:14 ` Andrew Lunn
0 siblings, 0 replies; 10+ messages in thread
From: Andrew Lunn @ 2018-02-14 16:14 UTC (permalink / raw)
To: Daniel Schultz
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
f.fainelli-Re5JQEeQqe8AvxtiuMwx3w, netdev-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
w.egorov-guT5V/WYfQezQB+pC5nmwQ
On Wed, Feb 14, 2018 at 05:07:11PM +0100, Daniel Schultz wrote:
> From: Wadim Egorov <w.egorov-guT5V/WYfQezQB+pC5nmwQ@public.gmane.org>
>
> The DP83867 has a muxing option for the CLK_OUT pin. It is possible
> to set CLK_OUT for different channels.
> Create a binding to select a specific clock for CLK_OUT pin.
>
> Signed-off-by: Wadim Egorov <w.egorov-guT5V/WYfQezQB+pC5nmwQ@public.gmane.org>
> Signed-off-by: Daniel Schultz <d.schultz-guT5V/WYfQezQB+pC5nmwQ@public.gmane.org>
Reviewed-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
Andrew
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 1/2] net: phy: dp83867: Add binding for the CLK_OUT pin muxing option
@ 2018-02-14 17:04 ` Florian Fainelli
0 siblings, 0 replies; 10+ messages in thread
From: Florian Fainelli @ 2018-02-14 17:04 UTC (permalink / raw)
To: Daniel Schultz, robh+dt, mark.rutland, andrew, netdev,
devicetree, linux-kernel
Cc: w.egorov
On February 14, 2018 8:07:11 AM PST, Daniel Schultz <d.schultz@phytec.de> wrote:
>From: Wadim Egorov <w.egorov@phytec.de>
>
>The DP83867 has a muxing option for the CLK_OUT pin. It is possible
>to set CLK_OUT for different channels.
>Create a binding to select a specific clock for CLK_OUT pin.
>
>Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
>Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
>---
>Changes:
> v2:
> Added check if clk_output_sel has a valid value
> Only write the clock ouput register if a musing is desired
> v3:
> -
>
> drivers/net/phy/dp83867.c | 19 +++++++++++++++++++
> include/dt-bindings/net/ti-dp83867.h | 14 ++++++++++++++
> 2 files changed, 33 insertions(+)
>
>diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
>index c1ab976..a862194 100644
>--- a/drivers/net/phy/dp83867.c
>+++ b/drivers/net/phy/dp83867.c
>@@ -75,6 +75,8 @@
>
> #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
> #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
>+#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
>+#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
>
Nit: it looks like you could use the shift constant you define for defining the mask as well.
Other than that:
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
--
Florian
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 1/2] net: phy: dp83867: Add binding for the CLK_OUT pin muxing option
@ 2018-02-14 17:04 ` Florian Fainelli
0 siblings, 0 replies; 10+ messages in thread
From: Florian Fainelli @ 2018-02-14 17:04 UTC (permalink / raw)
To: Daniel Schultz, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, andrew-g2DYL2Zd6BY,
netdev-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: w.egorov-guT5V/WYfQezQB+pC5nmwQ
On February 14, 2018 8:07:11 AM PST, Daniel Schultz <d.schultz@phytec.de> wrote:
>From: Wadim Egorov <w.egorov@phytec.de>
>
>The DP83867 has a muxing option for the CLK_OUT pin. It is possible
>to set CLK_OUT for different channels.
>Create a binding to select a specific clock for CLK_OUT pin.
>
>Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
>Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
>---
>Changes:
> v2:
> Added check if clk_output_sel has a valid value
> Only write the clock ouput register if a musing is desired
> v3:
> -
>
> drivers/net/phy/dp83867.c | 19 +++++++++++++++++++
> include/dt-bindings/net/ti-dp83867.h | 14 ++++++++++++++
> 2 files changed, 33 insertions(+)
>
>diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c
>index c1ab976..a862194 100644
>--- a/drivers/net/phy/dp83867.c
>+++ b/drivers/net/phy/dp83867.c
>@@ -75,6 +75,8 @@
>
> #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
> #define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
>+#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
>+#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
>
Nit: it looks like you could use the shift constant you define for defining the mask as well.
Other than that:
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
--
Florian
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/2] net: phy: dp83867: Add documentation for CLK_OUT pin muxing
@ 2018-02-14 17:06 ` Florian Fainelli
0 siblings, 0 replies; 10+ messages in thread
From: Florian Fainelli @ 2018-02-14 17:06 UTC (permalink / raw)
To: Daniel Schultz, robh+dt, mark.rutland, andrew, netdev,
devicetree, linux-kernel
Cc: w.egorov
On February 14, 2018 8:07:12 AM PST, Daniel Schultz <d.schultz@phytec.de> wrote:
>From: Wadim Egorov <w.egorov@phytec.de>
>
>Add documentation of ti,clk-output-sel which can be used to select
>a specific clock for CLK_OUT.
>
>Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
>Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Nit: usually the binding patch comes first and the implementation using it right after, not necessary to respin.
--
Florian
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/2] net: phy: dp83867: Add documentation for CLK_OUT pin muxing
@ 2018-02-14 17:06 ` Florian Fainelli
0 siblings, 0 replies; 10+ messages in thread
From: Florian Fainelli @ 2018-02-14 17:06 UTC (permalink / raw)
To: Daniel Schultz, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, andrew-g2DYL2Zd6BY,
netdev-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: w.egorov-guT5V/WYfQezQB+pC5nmwQ
On February 14, 2018 8:07:12 AM PST, Daniel Schultz <d.schultz@phytec.de> wrote:
>From: Wadim Egorov <w.egorov@phytec.de>
>
>Add documentation of ti,clk-output-sel which can be used to select
>a specific clock for CLK_OUT.
>
>Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
>Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Nit: usually the binding patch comes first and the implementation using it right after, not necessary to respin.
--
Florian
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 1/2] net: phy: dp83867: Add binding for the CLK_OUT pin muxing option
2018-02-14 16:07 [PATCH v3 1/2] net: phy: dp83867: Add binding for the CLK_OUT pin muxing option Daniel Schultz
` (2 preceding siblings ...)
2018-02-14 17:04 ` Florian Fainelli
@ 2018-02-14 20:33 ` David Miller
3 siblings, 0 replies; 10+ messages in thread
From: David Miller @ 2018-02-14 20:33 UTC (permalink / raw)
To: d.schultz
Cc: robh+dt, mark.rutland, andrew, f.fainelli, netdev, devicetree,
linux-kernel, w.egorov
From: Daniel Schultz <d.schultz@phytec.de>
Date: Wed, 14 Feb 2018 17:07:11 +0100
> From: Wadim Egorov <w.egorov@phytec.de>
>
> The DP83867 has a muxing option for the CLK_OUT pin. It is possible
> to set CLK_OUT for different channels.
> Create a binding to select a specific clock for CLK_OUT pin.
>
> Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
> Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
> ---
> Changes:
> v2:
> Added check if clk_output_sel has a valid value
> Only write the clock ouput register if a musing is desired
> v3:
> -
Applied to net-next.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v3 2/2] net: phy: dp83867: Add documentation for CLK_OUT pin muxing
2018-02-14 16:07 ` [PATCH v3 2/2] net: phy: dp83867: Add documentation for CLK_OUT pin muxing Daniel Schultz
2018-02-14 17:06 ` Florian Fainelli
@ 2018-02-14 20:34 ` David Miller
1 sibling, 0 replies; 10+ messages in thread
From: David Miller @ 2018-02-14 20:34 UTC (permalink / raw)
To: d.schultz
Cc: robh+dt, mark.rutland, andrew, f.fainelli, netdev, devicetree,
linux-kernel, w.egorov
From: Daniel Schultz <d.schultz@phytec.de>
Date: Wed, 14 Feb 2018 17:07:12 +0100
> From: Wadim Egorov <w.egorov@phytec.de>
>
> Add documentation of ti,clk-output-sel which can be used to select
> a specific clock for CLK_OUT.
>
> Signed-off-by: Wadim Egorov <w.egorov@phytec.de>
> Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
> ---
> Changes:
> v2:
> -
> v3:
> Fixed indentation.
Also applied to net-next, thanks.
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2018-02-14 20:34 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
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2018-02-14 16:07 [PATCH v3 1/2] net: phy: dp83867: Add binding for the CLK_OUT pin muxing option Daniel Schultz
2018-02-14 16:07 ` [PATCH v3 2/2] net: phy: dp83867: Add documentation for CLK_OUT pin muxing Daniel Schultz
2018-02-14 17:06 ` Florian Fainelli
2018-02-14 17:06 ` Florian Fainelli
2018-02-14 20:34 ` David Miller
2018-02-14 16:14 ` [PATCH v3 1/2] net: phy: dp83867: Add binding for the CLK_OUT pin muxing option Andrew Lunn
2018-02-14 16:14 ` Andrew Lunn
2018-02-14 17:04 ` Florian Fainelli
2018-02-14 17:04 ` Florian Fainelli
2018-02-14 20:33 ` David Miller
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