From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=58525 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PesFv-0002HN-3m for qemu-devel@nongnu.org; Mon, 17 Jan 2011 11:48:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PesFl-0006c5-G7 for qemu-devel@nongnu.org; Mon, 17 Jan 2011 11:48:26 -0500 Received: from david.siemens.de ([192.35.17.14]:21261) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PesFl-0006ba-5F for qemu-devel@nongnu.org; Mon, 17 Jan 2011 11:48:25 -0500 Message-ID: <4D3472D3.2000002@siemens.com> Date: Mon, 17 Jan 2011 17:48:19 +0100 From: Jan Kiszka MIME-Version: 1.0 References: <1292879604-22268-1-git-send-email-agraf@suse.de> <1292879604-22268-9-git-send-email-agraf@suse.de> <4D34542D.7080301@siemens.com> <4D3467B9.3070207@suse.de> <4D346834.8000903@siemens.com> <4D3468A0.3060709@suse.de> <4D346C31.8060300@siemens.com> <4D346F5B.7090502@suse.de> In-Reply-To: <4D346F5B.7090502@suse.de> Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] Re: [PATCH 8/8] ahci: fix !msi interrupts List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Kevin Wolf , Joerg Roedel , Sebastian Herbszt , qemu-devel Developers , Gerd Hoffmann On 2011-01-17 17:33, Alexander Graf wrote: > Jan Kiszka wrote: >> On 2011-01-17 17:04, Alexander Graf wrote: >> >>> Jan Kiszka wrote: >>> >>>> On 2011-01-17 17:00, Alexander Graf wrote: >>>> >>>> >>>>> Jan Kiszka wrote: >>>>> >>>>> >>>>>> On 2010-12-20 22:13, Alexander Graf wrote: >>>>>> >>>>>> >>>>>> >>>>>>> When not using MSI, receiving an interrupt while the interrupt line is active >>>>>>> pulses the interrupt line. Without this, guests don't realize that a new >>>>>>> interrupt occured. >>>>>>> >>>>>>> >>>>>>> >>>>>> This doesn't look OK. The device model should look at the currently used >>>>>> mode and switch between edge and level triggering accordingly. As it >>>>>> appears like this is what it already does, this change may just paper >>>>>> over the real issue. >>>>>> >>>>>> >>>>>> >>>>> Well, I have this internal abstraction to make edge and level triggered >>>>> interrupt triggering easier. irq_lower is a simple nop for the edge case. >>>>> >>>>> >>>>> >>>> I'm concerned about the artificial edge you generate for the level >>>> triggered case. That's not like real hw behaves. If you need it, >>>> something else might still be broken. >>>> >>>> >>> Hrm. So worst case we generate a spurious interrupt? >>> >>> >> >> Worse might also be that unknown issue that force you to inject an IRQ >> here. We don't know. That's probably worst. >> > > Well, IIRC the issue was that usually a level high interrupt line would > simply retrigger an interrupt after enabling the interrupt line in the > APIC again. Unless my memory completely fails on me, that didn't happen, > so I added the manual retrigger on a partial command ACK in ahci code. > How many other device models require this workaround? And is this a limitation of a specific irqchip model or of the irq layer (I can't believe it's the latter though)? All fairly suspicious... Jan -- Siemens AG, Corporate Technology, CT T DE IT 1 Corporate Competence Center Embedded Linux