[ 671.152494] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2 [ 671.155709] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 671.163757] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00 [ 671.184024] [drm:intel_sdvo_detect], SDVO response 1 0 [1] [ 671.187225] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 671.203937] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 671.360941] [drm:output_poll_execute], [CONNECTOR:8:DVI-D-1] status updated from 1 to 1 [ 671.368025] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 671.392324] [drm:intel_sdvo_write_cmd], command returns response Pending [4] [ 671.395585] [drm:output_poll_execute], [CONNECTOR:44:VGA-2] status updated from 3 to 3 [ 674.428925] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2 [ 674.450552] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 674.467370] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00 [ 674.494216] [drm:intel_sdvo_detect], SDVO response 1 0 [1] [ 674.500046] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 674.525550] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 674.664722] [drm:output_poll_execute], [CONNECTOR:8:DVI-D-1] status updated from 1 to 1 [ 674.667916] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 674.721883] [drm:intel_sdvo_write_cmd], command returns response Pending [4] [ 674.736528] [drm:output_poll_execute], [CONNECTOR:44:VGA-2] status updated from 3 to 3 [ 677.748021] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2 [ 677.751234] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 677.772763] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00 [ 677.803463] [drm:intel_sdvo_detect], SDVO response 1 0 [1] [ 677.827596] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 677.866445] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 678.303984] [drm:output_poll_execute], [CONNECTOR:8:DVI-D-1] status updated from 1 to 1 [ 678.346999] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 678.553774] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 678.581302] [drm:intel_sdvo_detect], SDVO response 0 0 [2] [ 678.598641] [drm:output_poll_execute], [CONNECTOR:44:VGA-2] status updated from 3 to 2 [ 678.604871] [drm:drm_sysfs_hotplug_event], generating hotplug event [ 678.618793] [drm:drm_fb_helper_hotplug_event], [ 678.628888] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1] [ 678.654238] [drm:drm_crtc_helper_set_mode], [CRTC:4] [ 678.663275] [drm:intel_sdvo_debug_write], SDVOC: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 678.680374] [drm:drm_calc_vbltimestamp_from_scanoutpos], crtc 1 : v 5 p(329,361)@ 1295947882.912751 -> 1295947882.907025 [e 2 us, 0 rep] [ 678.708771] [drm:intel_update_fbc], [ 678.718017] [drm:intel_update_watermarks], plane B (pipe 0) clock: 108000 [ 678.725996] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 678.733867] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 678.741717] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 678.749794] [drm:intel_calculate_wm], FIFO watermark level: 26 [ 678.756453] [drm:intel_calculate_wm], FIFO entries required for mode: 34 [ 678.759577] [drm:intel_calculate_wm], FIFO watermark level: -5 [ 678.769618] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 1 [ 678.777813] [drm:i9xx_update_wm], self-refresh entries: 80 [ 678.785658] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 1, C: 2, SR 15 [ 678.800023] [drm:drm_vblank_get], enabling vblank on crtc 1, ret: -22 [ 678.803328] [drm:intel_crtc_mode_set], Mode for pipe B: [ 678.808800] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa [ 678.824024] [drm:intel_pipe_set_base], No FB bound [ 678.827132] [drm:intel_update_watermarks], plane B (pipe 0) clock: 108000 [ 678.837557] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 678.848017] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 678.851051] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 678.866902] [drm:intel_calculate_wm], FIFO watermark level: 26 [ 678.870126] [drm:intel_calculate_wm], FIFO entries required for mode: 34 [ 678.884043] [drm:intel_calculate_wm], FIFO watermark level: -5 [ 678.887050] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 1 [ 678.898538] [drm:i9xx_update_wm], self-refresh entries: 80 [ 678.904580] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 1, C: 2, SR 15 [ 678.907503] [drm:drm_crtc_helper_set_mode], [ENCODER:6:DAC-6] set [MODE:0:640x480] [ 678.917001] [drm:intel_update_watermarks], plane B (pipe 0) clock: 108000 [ 678.919944] [drm:intel_update_watermarks], plane A (pipe 1) clock: 31500 [ 678.932035] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 678.934922] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 678.946432] [drm:intel_calculate_wm], FIFO entries required for mode: 10 [ 678.953805] [drm:intel_calculate_wm], FIFO watermark level: 16 [ 678.961781] [drm:intel_calculate_wm], FIFO entries required for mode: 34 [ 678.977092] [drm:intel_calculate_wm], FIFO watermark level: -5 [ 678.979854] [drm:i9xx_update_wm], FIFO watermarks - A: 16, B: 1 [ 678.988110] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 16, B: 1, C: 2, SR 1 [ 678.990879] [drm:intel_update_fbc], [ 679.004941] [drm:drm_calc_timestamping_constants], crtc 4: hwmode: htotal 832, vtotal 520, vdisplay 480 [ 679.007723] [drm:drm_calc_timestamping_constants], crtc 4: clock 31500 kHz framedur 13734240 linedur 26412, pixeldur 31 [ 679.037015] [drm:intel_crt_load_detect], starting load-detect on CRT [ 679.068052] [drm:intel_sdvo_debug_write], SDVOC: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 679.083385] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:VGA-1] disconnected [ 679.112709] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:8:DVI-D-1] [ 679.115522] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 679.131696] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00 [ 679.171012] [drm:intel_sdvo_detect], SDVO response 1 0 [1] [ 679.177632] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 679.209267] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 679.566246] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 679.633527] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 680.003280] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:8:DVI-D-1] probed modes : [ 680.032347] [drm:drm_mode_debug_printmodeline], Modeline 61:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5 [ 680.035247] [drm:drm_mode_debug_printmodeline], Modeline 65:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa [ 680.060059] [drm:drm_mode_debug_printmodeline], Modeline 62:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5 [ 680.062824] [drm:drm_mode_debug_printmodeline], Modeline 63:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa [ 680.097908] [drm:drm_mode_debug_printmodeline], Modeline 64:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6 [ 680.112033] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] [ 680.114768] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 680.321398] [drm:intel_sdvo_read_response], SDVOC: R: (Success) 00 00 [ 680.349479] [drm:intel_sdvo_detect], SDVO response 0 0 [8] [ 680.357345] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:10:SVIDEO-1] disconnected [ 680.369126] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:27:SVIDEO-2] [ 680.371855] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 680.417190] [drm:intel_sdvo_write_cmd], command returns response Pending [4] [ 680.419880] [drm:intel_sdvo_debug_write], SDVOC: W: 11 00 00 (SDVO_CMD_SET_TARGET_OUTPUT) [ 680.450190] [drm:intel_sdvo_write_cmd], command returns response Invalid arg [3] [ 680.468113] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:44:VGA-2] [ 680.470894] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 680.511776] [drm:intel_sdvo_write_cmd], command returns response Pending [4] [ 680.524023] [drm:intel_sdvo_debug_write], SDVOC: W: 7A 02 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 680.556503] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:45:SVIDEO-3] [ 680.559416] [drm:drm_crtc_helper_set_mode], [CRTC:4] [ 680.572068] [drm:intel_sdvo_debug_write], SDVOC: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 680.589252] [drm:drm_calc_vbltimestamp_from_scanoutpos], crtc 1 : v 5 p(127,386)@ 1295947884.821631 -> 1295947884.811432 [e 2 us, 0 rep] [ 680.624239] [drm:intel_update_fbc], [ 680.627278] [drm:intel_update_watermarks], plane B (pipe 0) clock: 108000 [ 680.639009] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 680.648029] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 680.650937] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 680.662810] [drm:intel_calculate_wm], FIFO watermark level: 26 [ 680.669489] [drm:intel_calculate_wm], FIFO entries required for mode: 34 [ 680.682378] [drm:intel_calculate_wm], FIFO watermark level: -5 [ 680.693302] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 1 [ 680.701239] [drm:i9xx_update_wm], self-refresh entries: 80 [ 680.714881] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 1, C: 2, SR 15 [ 680.721110] [drm:drm_vblank_get], enabling vblank on crtc 1, ret: -22 [ 680.737117] [drm:intel_crtc_mode_set], Mode for pipe B: [ 680.760451] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0 [ 680.778107] [drm:intel_pipe_set_base], No FB bound [ 680.790444] [drm:intel_update_watermarks], plane B (pipe 0) clock: 108000 [ 680.804030] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 680.807079] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 680.832023] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 680.835064] [drm:intel_calculate_wm], FIFO watermark level: 26 [ 680.855509] [drm:intel_calculate_wm], FIFO entries required for mode: 34 [ 680.861940] [drm:intel_calculate_wm], FIFO watermark level: -5 [ 680.878730] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 1 [ 680.888062] [drm:i9xx_update_wm], self-refresh entries: 80 [ 680.919017] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 1, C: 2, SR 15 [ 680.926102] [drm:drm_crtc_helper_set_mode], [ENCODER:46:TV-46] set [MODE:0:NTSC 480i] [ 681.024988] [drm:intel_update_watermarks], plane B (pipe 0) clock: 108000 [ 681.049767] [drm:intel_update_watermarks], plane A (pipe 1) clock: 107520 [ 681.068044] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 681.071009] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 681.097603] [drm:intel_calculate_wm], FIFO entries required for mode: 34 [ 681.116322] [drm:intel_calculate_wm], FIFO watermark level: -8 [ 681.119205] [drm:intel_calculate_wm], FIFO entries required for mode: 34 [ 681.145340] [drm:intel_calculate_wm], FIFO watermark level: -5 [ 681.168046] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1 [ 681.170864] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1 [ 681.202547] [drm:intel_update_fbc], [ 681.223374] [drm:drm_calc_timestamping_constants], crtc 4: hwmode: htotal 1712, vtotal 1104, vdisplay 1024 [ 681.227767] [drm:drm_calc_timestamping_constants], crtc 4: clock 108000 kHz framedur 17499504 linedur 15851, pixeldur 9 [ 681.308034] [drm:intel_sdvo_debug_write], SDVOC: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 681.345456] [drm:drm_helper_probe_single_connector_modes], [CONNECTOR:45:SVIDEO-3] disconnected [ 681.392038] [drm:drm_setup_crtcs], [ 681.416137] [drm:drm_enable_connectors], connector 5 enabled? no [ 681.419072] [drm:drm_enable_connectors], connector 8 enabled? yes [ 681.448859] [drm:drm_enable_connectors], connector 10 enabled? no [ 681.451740] [drm:drm_enable_connectors], connector 27 enabled? no [ 681.477439] [drm:drm_enable_connectors], connector 44 enabled? no [ 681.493210] [drm:drm_enable_connectors], connector 45 enabled? no [ 681.495922] [drm:drm_target_preferred], looking for cmdline mode on connector 8 [ 681.518773] [drm:drm_target_preferred], looking for preferred mode on connector 8 [ 681.527815] [drm:drm_target_preferred], found mode 1280x1024 [ 681.531482] [drm:drm_setup_crtcs], picking CRTCs for 4096x4096 config [ 681.553389] [drm:drm_setup_crtcs], desired mode 1280x1024 set on crtc 3 [ 681.571369] [drm:drm_crtc_helper_set_config], [ 681.578657] [drm:drm_crtc_helper_set_config], [CRTC:3] [FB:67] #connectors=1 (x y) (0 0) [ 681.592922] [drm:drm_crtc_helper_set_config], crtc changed, full mode switch [ 681.595533] [drm:drm_crtc_helper_set_config], [CONNECTOR:8:DVI-D-1] to [CRTC:3] [ 681.615169] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace [ 681.623390] [drm:drm_mode_debug_printmodeline], Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5 [ 681.631568] [drm:drm_crtc_helper_set_mode], [CRTC:3] [ 681.651445] [drm:intel_sdvo_debug_write], SDVOB: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 681.679492] [drm:intel_sdvo_debug_write], SDVOC: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 681.733722] [drm:drm_calc_vbltimestamp_from_scanoutpos], crtc 0 : v 5 p(1041,424)@ 1295947885.966098 -> 1295947885.959461 [e 2 us, 0 rep] [ 681.807832] [drm:intel_update_fbc], [ 681.811159] [drm:intel_update_watermarks], plane A (pipe 1) clock: 107520 [ 681.827995] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 681.830579] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 681.850640] [drm:intel_calculate_wm], FIFO entries required for mode: 34 [ 681.854871] [drm:intel_calculate_wm], FIFO watermark level: -8 [ 681.868920] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 681.871448] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 681.878698] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 681.909170] [drm:i9xx_update_wm], self-refresh entries: 80 [ 681.911737] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 15 [ 681.936353] [drm:drm_vblank_get], enabling vblank on crtc 0, ret: -22 [ 681.939077] [drm:intel_crtc_mode_set], Mode for pipe A: [ 681.964047] [drm:drm_mode_debug_printmodeline], Modeline 66:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x48 0x5 [ 681.984036] [drm:intel_pipe_set_base_atomic], Writing base 00020000 00000000 0 0 5120 [ 681.986572] [drm:intel_update_fbc], [ 682.020049] [drm:intel_update_watermarks], plane A (pipe 1) clock: 107520 [ 682.022589] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 682.038559] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 682.048026] [drm:intel_calculate_wm], FIFO entries required for mode: 34 [ 682.050571] [drm:intel_calculate_wm], FIFO watermark level: -8 [ 682.074684] [drm:intel_calculate_wm], FIFO entries required for mode: 0 [ 682.083768] [drm:intel_calculate_wm], FIFO watermark level: 29 [ 682.087276] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29 [ 682.106667] [drm:i9xx_update_wm], self-refresh entries: 80 [ 682.116042] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 15 [ 682.118579] [drm:drm_crtc_helper_set_mode], [ENCODER:7:TMDS-7] set [MODE:66:1280x1024] [ 682.142852] [drm:intel_sdvo_debug_write], SDVOB: W: 07 01 00 00 00 (SDVO_CMD_SET_IN_OUT_MAP) [ 682.178355] [drm:intel_sdvo_debug_write], SDVOB: W: 11 01 00 (SDVO_CMD_SET_TARGET_OUTPUT) [ 682.211647] [drm:intel_sdvo_debug_write], SDVOB: W: 11 01 00 (SDVO_CMD_SET_TARGET_OUTPUT) [ 682.243067] [drm:intel_sdvo_debug_write], SDVOB: W: 16 30 2A 00 98 51 00 2A 40 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1) [ 682.301011] [drm:intel_sdvo_debug_write], SDVOB: W: 17 30 70 13 00 1E 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2) [ 682.345382] [drm:intel_sdvo_debug_write], SDVOB: W: 10 00 (SDVO_CMD_SET_TARGET_INPUT) [ 682.376561] [drm:intel_sdvo_debug_write], SDVOB: W: 9F 00 (SDVO_CMD_SET_ENCODE) [ 682.397544] [drm:intel_sdvo_write_cmd], command returns response Not supported [2] [ 682.408047] [drm:intel_sdvo_debug_write], SDVOB: W: 14 30 2A 00 98 51 00 2A 40 (SDVO_CMD_SET_INPUT_TIMINGS_PART1) [ 682.455723] [drm:intel_sdvo_debug_write], SDVOB: W: 15 30 70 13 00 1E 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2) [ 682.499532] [drm:intel_sdvo_debug_write], SDVOB: W: 21 01 (SDVO_CMD_SET_CLOCK_RATE_MULT) [ 682.530029] [drm:intel_update_watermarks], plane B (pipe 0) clock: 108000 [ 682.536183] [drm:intel_update_watermarks], plane A (pipe 1) clock: 107520 [ 682.548049] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28 [ 682.550524] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31 [ 682.564886] [drm:intel_calculate_wm], FIFO entries required for mode: 34 [ 682.567304] [drm:intel_calculate_wm], FIFO watermark level: -8 [ 682.575026] [drm:intel_calculate_wm], FIFO entries required for mode: 34 [ 682.584028] [drm:intel_calculate_wm], FIFO watermark level: -5 [ 682.586487] [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 1 [ 682.601206] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 1, C: 2, SR 1 [ 682.603914] [drm:intel_update_fbc], [ 682.640163] [drm:intel_sdvo_debug_write], SDVOB: W: 03 (SDVO_CMD_GET_TRAINED_INPUTS) [ 682.667224] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 [ 682.695589] [drm:intel_sdvo_debug_write], SDVOB: W: 05 01 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 682.723567] [drm:drm_calc_timestamping_constants], crtc 3: hwmode: htotal 1688, vtotal 1066, vdisplay 1024 [ 682.742433] [drm:drm_calc_timestamping_constants], crtc 3: clock 108000 kHz framedur 16660514 linedur 15629, pixeldur 9 [ 682.751532] [drm:intel_sdvo_debug_write], SDVOC: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 682.786425] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 682.808050] [drm:drm_crtc_helper_set_config], [CONNECTOR:8:DVI-D-1] set DPMS on [ 682.810762] [drm:drm_crtc_helper_set_config], [ 682.835094] [drm:drm_crtc_helper_set_config], [CRTC:4] [FB:67] #connectors=0 (x y) (0 0) [ 682.840599] [drm:drm_crtc_helper_set_config], crtc has no fb, full mode set [ 682.843204] [drm:drm_crtc_helper_set_config], [CONNECTOR:8:DVI-D-1] to [CRTC:3] [ 682.859924] [drm:intel_sdvo_debug_write], SDVOC: W: 05 00 00 (SDVO_CMD_SET_ACTIVE_OUTPUTS) [ 682.891197] [drm:drm_crtc_helper_set_config], Setting connector DPMS state to on [ 682.926640] [drm:output_poll_execute], [CONNECTOR:5:VGA-1] status updated from 2 to 2 [ 682.932969] [drm:intel_sdvo_debug_write], SDVOB: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 682.964877] [drm:intel_sdvo_read_response], SDVOB: R: (Success) 01 00 [ 682.987600] [drm:intel_sdvo_detect], SDVO response 1 0 [1] [ 683.008411] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 683.030942] [drm:intel_sdvo_debug_write], SDVOB: W: 7A 02 (SDVO_CMD_SET_CONTROL_BUS_SWITCH) [ 683.221578] [drm:output_poll_execute], [CONNECTOR:8:DVI-D-1] status updated from 1 to 1 [ 683.236022] [drm:intel_sdvo_debug_write], SDVOC: W: 0B (SDVO_CMD_GET_ATTACHED_DISPLAYS) [ 683.263025] [drm:intel_sdvo_write_cmd], command returns response Pending [4] [ 683.269816] [drm:output_poll_execute], [CONNECTOR:44:VGA-2] status updated from 3 to 3