From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=55660 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pi8L7-0007Jj-2u for qemu-devel@nongnu.org; Wed, 26 Jan 2011 11:35:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pi8L0-0004xF-S2 for qemu-devel@nongnu.org; Wed, 26 Jan 2011 11:35:19 -0500 Received: from mx1.redhat.com ([209.132.183.28]:35048) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pi8L0-0004wu-Kt for qemu-devel@nongnu.org; Wed, 26 Jan 2011 11:35:18 -0500 Message-ID: <4D404D33.1030201@redhat.com> Date: Wed, 26 Jan 2011 18:34:59 +0200 From: Avi Kivity MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 5/7] tcg-i386: Implement deposit operation. References: <1294716228-9299-1-git-send-email-rth@twiddle.net> <1294716228-9299-6-git-send-email-rth@twiddle.net> <20110125122749.GA19736@edde.se.axis.com> <4D3EF6C1.3080502@twiddle.net> <20110125164816.GA23569@laped.lan> <4D3F4993.4010109@twiddle.net> <20110126085338.GA26088@laped.lan> <4D4042B4.4020805@twiddle.net> <4D404533.3060708@suse.de> In-Reply-To: <4D404533.3060708@suse.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: "Edgar E.Iglesias" , qemu-devel@nongnu.org, aurelien@aurel32.net, Richard Henderson On 01/26/2011 06:00 PM, Alexander Graf wrote: > Richard Henderson wrote: > > On 01/26/2011 01:23 AM, Alexander Graf wrote: > > > >> agraf@toonie:/studio/s390/qemu-s390> grep deposit target-s390x/translate.c > >> tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 32); > >> tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 32); > >> tcg_gen_deposit_i64(regs[reg], regs[reg], tmp, 0, 16); > >> tcg_gen_deposit_i64(regs[reg], regs[reg], v, 0, 8); > >> tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 48, 16); > >> tcg_gen_deposit_i64(regs[r1], regs[r1], tmp, 32, 16); > >> > >> The 0, 32 and 0, 16 versions should get accelerated pretty well while > >> the 32, 16 and 48, 16 are not I assume? > >> > > > > No, only the 0,16 and 0,8 deposits correspond to a hardware insn on x86. > > > > Given that the 0,32 lowpart writeback is almost certainly the most common > > operation for s390x, I doubt the deposit patch will help with an x86 host. > > > > Have you thought about buffering the lowpart writeback in the translator? > > I.e. when a 32-bit insn writes to a register, remember that value without > > writing it back. If the next insn in the TB is also 32-bit, reuse the > > saved value, etc. Only perform the writeback for 64-bit insns using the > > register as a source, end of TB, and places that can take an exception. > > > > That's basically what uli's tcg_sync op did which got rejected upstream :). > > Keeping it only inside of the translator would break on page faults, as > the lower 32 bits of the register would lie around in a temporary which > is invisible for the page fault resolver. It should be possible to have the exception injector look up instruction pointer in a bitmap in the TB, and if set, execute a completion which writes back the temporary to the correct register. Not trivial, but I imagine useful for many optimizations which combine several target instructions into one host instruction (probably most useful for risc->cisc translations). -- error compiling committee.c: too many arguments to function