From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=42305 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pi9zc-0005ta-Cj for qemu-devel@nongnu.org; Wed, 26 Jan 2011 13:21:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pi9zY-0007Qs-7C for qemu-devel@nongnu.org; Wed, 26 Jan 2011 13:21:20 -0500 Received: from b.mail.sonic.net ([64.142.19.5]:45940) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pi9zX-0007QT-W2 for qemu-devel@nongnu.org; Wed, 26 Jan 2011 13:21:16 -0500 Message-ID: <4D40660F.9070004@twiddle.net> Date: Wed, 26 Jan 2011 10:21:03 -0800 From: Richard Henderson MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 5/7] tcg-i386: Implement deposit operation. References: <1294716228-9299-1-git-send-email-rth@twiddle.net> <1294716228-9299-6-git-send-email-rth@twiddle.net> <20110125122749.GA19736@edde.se.axis.com> <4D3EF6C1.3080502@twiddle.net> <20110125164816.GA23569@laped.lan> <4D3F4993.4010109@twiddle.net> <20110126085338.GA26088@laped.lan> <4D4042B4.4020805@twiddle.net> <4D404533.3060708@suse.de> <4D404E66.4020109@twiddle.net> <4D4050E3.9010207@suse.de> In-Reply-To: <4D4050E3.9010207@suse.de> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: "Edgar E.Iglesias" , qemu-devel@nongnu.org, aurelien@aurel32.net On 01/26/2011 08:50 AM, Alexander Graf wrote: > Oh, you mean basically to have the following: > > TCGv_i32 regs32[16]; > TCGv_i64 regs[16]; > > Then declare both as globals with offset and just switch between the > access type using a disas struct variable. Once the TB ends, I'd > obviously have to sync back to 64 bit again. Maybe? I don't think that regs32 can overlap with regs in the real cpu structure. Otherwise you have the same sort of sync problems as was originally rejected. I had been picturing regs32 as a member of DisasContext, and it would hold tcg_temp_new_i32 variables as-needed. Something like #if TCG_TARGET_REG_BITS == 64 static void writeback_reg32(DisasContext *dc, int r) { // ??? This macro should really exist to match TCGV_UNUSED_I32 etc. if (!TCGV_IS_UNUSED_I32 (dc->regs32[r])) { tcg_gen_deposit_tl(cpu_regs[r], cpu_regs[r], MAKE_TCGV_I64 (GET_TCGV_I32 (dc->regs32[r])), 0, 32); } } static void writeback_all_reg32(DisasContext *dc) { int i; for (i = 0; i < 16; ++i) { flush_reg32(dc, i); } } static void flush_all_reg32(DisasContext *dc) { int i; for (i = 0; i < 16; ++i) { if (!TCGV_IS_UNUSED_I32 (dc->regs32[r])) { tcg_temp_free_i32 (dc->regs32[r]); TCGV_UNUSED_I32 (dc->regs32[r]); } } } static TCGv_i32 get_reg32(DisasContext *dc, int r) { if (TCGV_IS_UNUSED_I32 (dc->regs32[r])) { dc->regs32[r] = tcg_temp_new_i32(); tcg_gen_trunc_i64_i32(dc->regs32[r], cpu_regs[r]); } return dc->regs32[r]; } static TCGv_i64 get_reg64(DisasContext *dc, int r) { writeback_reg32(dc, r); return cpu_regs[r]; } #elif TCG_TARGET_REG_BITS == 32 static void writeback_reg32(DisasContext *dc, int r) { } static void writeback_all_reg32(DisasContext *dc) { } static void flush_all_reg32(DisasContext *dc) { } static TCGv_i32 get_reg32(DisasContext *dc, int r) { return TCGV_LOW(cpu_regs[r]); } static TCGv_i64 get_reg64(DisasContext *dc, int r) { return cpu_regs[r]; } #endif r~