From mboxrd@z Thu Jan 1 00:00:00 1970 From: Cyrill Gorcunov Subject: Re: [patch 1/2] kvm tools: Fix up PCI pin assignment to conform specification Date: Sat, 07 May 2011 19:09:38 +0400 Message-ID: <4DC560B2.1060702@gmail.com> References: <20110507145514.476517775@gmail.com> <20110507145636.099751964@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Cc: mingo@elte.hu, levinsasha928@gmail.com, asias.hejun@gmail.com, prasadjoshi124@gmail.com, kvm@vger.kernel.org To: Pekka Enberg Return-path: Received: from mail-ey0-f174.google.com ([209.85.215.174]:56286 "EHLO mail-ey0-f174.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755550Ab1EGPJm (ORCPT ); Sat, 7 May 2011 11:09:42 -0400 Received: by eyx24 with SMTP id 24so1213291eyx.19 for ; Sat, 07 May 2011 08:09:41 -0700 (PDT) In-Reply-To: Sender: kvm-owner@vger.kernel.org List-ID: On 05/07/2011 07:05 PM, Pekka Enberg wrote: > On Sat, May 7, 2011 at 5:55 PM, Cyrill Gorcunov wrote: >> Only 4 pins are allowed for every PCI compilant device. Mutlifunctional >> devices can use up to all INTA#,B#,C#,D# pins, for our sindle function >> devices pin INTA# is enough. >> >> Signed-off-by: Cyrill Gorcunov > > Could you point me to the relevant specification and section that I > can use to double-check this patch (and include it in the changelog)? PCI spec 2.2, 2.2.6 Interrupt Pins (Optional) -- Thanks, Cyrill