From mboxrd@z Thu Jan 1 00:00:00 1970 From: Steve Calfee Subject: Re: beagleboardxm 2.6.39rc4 mcbsp problems. Date: Thu, 12 May 2011 11:43:20 -0700 Message-ID: <4DCC2A48.7070602@gmail.com> References: <1305122135-27938-1-git-send-email-premi@ti.com> <4DCB0042.8040202@gmail.com> <20110512092555.17ebf795.jhnikula@gmail.com> <201105121401.44607.peter.ujfalusi@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: Received: from mail-pz0-f46.google.com ([209.85.210.46]:47755 "EHLO mail-pz0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757673Ab1ELSnY (ORCPT ); Thu, 12 May 2011 14:43:24 -0400 Received: by pzk9 with SMTP id 9so836489pzk.19 for ; Thu, 12 May 2011 11:43:24 -0700 (PDT) In-Reply-To: <201105121401.44607.peter.ujfalusi@ti.com> Sender: linux-omap-owner@vger.kernel.org List-Id: linux-omap@vger.kernel.org To: Peter Ujfalusi Cc: Jarkko Nikula , "Premi, Sanjeev" , "linux-omap@vger.kernel.org" , "Girdwood, Liam" On 05/12/11 04:01, Peter Ujfalusi wrote: > On Thursday 12 May 2011 09:25:55 Jarkko Nikula wrote: >> Of course for this you need to use omap as a master and codec as a >> slave. One example for this is sound/soc/omap/omap3pandora.c. >> >> static struct omap_board_mux board_mux[] __initdata = { >> + OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), >> + OMAP3_MUX(MCBSP1_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), >> + OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), >> + OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), >> + > > I think the CLKX, FSX need to be input, since the config suggests,t that > McBSP1 is the slave port: > >> [ 1566.123962] omap-mcbsp omap-mcbsp.1: PCR0: 0x0f0f > Hi, thanks for trying to help. I already tried that, but it still did not xmit. Now I wonder about master/slave. I thought that the omap is set up as a master. I looked at PCR0 docs in the tech ref manual and I get: 11 FSXM Transmit Frame-Synchronization Mode RW 0x0 0x0: Frame-synchronization signal derived from an external source 0x1: Frame synchronization is determined by the SRG frame-synchronization mode bit FSGM in SRGR2. 10 FSRM Receive Frame-Synchronization Mode RW 0x0 0x0: Frame-Synchronization pulses generated by an external device. FSR is an input pin. 0x1: Frame synchronization generated internally by SRG. FSR is an output pin except when GSYNC=1 in SRGR. Etc. Since it is set to 0xF0F, doesn't this set it as master? Also, spelunking the kernel sources, I cannot seem to find the source for mcbsp_data->regs -- do you know where it gets set initially?