Re: [Qemu-devel] [RFC] Memory API

[Jan Kiszka <jan.kiszka@siemens.com>]

On 2011-05-19 15:50, Anthony Liguori wrote:
> On 05/19/2011 08:47 AM, Jan Kiszka wrote:
>> On 2011-05-19 15:44, Anthony Liguori wrote:
>>> Well......
>>>
>>> The i440fx may direct VGA accesses to RAM depending on the SMM
>>> registers.  By the time the PIIX gets the I/O request, we're past the
>>> memory controller.
>>>
>>> This is my biggest concern about this whole notion of "priority".  These
>>> sort of issues are not dealt with by a simple z-ordering.  There is
>>> logic in each component that may be arbitrarily complex.
>>>
>>> We're going to end up having to dynamically change the "priority" based
>>> how registers are programmed.  But priorities are relative so it's
>>> unclear to me how the I440FX would prioritize RAM over dispatch to PIIX
>>> (for VGA, for instance).
>>
>> But creating an extra RAM window region with higher priority than the
>> underlying mappings.
> 
> But the i440fx doesn't register the VGA region.  The PIIX3 (ISA bus) 
> does, so how does it know what the priority of that mapping is?

Everything imported from "below" is of default priority for a bridge. So
it just has to add 1 to that prio value (or more if it needs to support
more layers).

Jan

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