From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:52679) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QN3s1-0002fX-00 for qemu-devel@nongnu.org; Thu, 19 May 2011 10:06:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QN3rv-000422-Vg for qemu-devel@nongnu.org; Thu, 19 May 2011 10:06:32 -0400 Received: from david.siemens.de ([192.35.17.14]:17251) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QN3rv-00041r-Ig for qemu-devel@nongnu.org; Thu, 19 May 2011 10:06:27 -0400 Message-ID: <4DD523DE.5000105@siemens.com> Date: Thu, 19 May 2011 16:06:22 +0200 From: Jan Kiszka MIME-Version: 1.0 References: <4DD3C5B9.1080908@redhat.com> <4DD3D236.90708@siemens.com> <4DD3D95E.2060105@redhat.com> <4DD3E1B3.3020405@siemens.com> <4DD3E610.1080201@siemens.com> <4DD4199E.2000702@codemonkey.ws> <4DD41DBB.2020108@web.de> <20110519082644.GC28399@redhat.com> <4DD4D53F.1090108@web.de> <4DD52082.1080804@codemonkey.ws> <4DD521C8.5020903@siemens.com> <4DD52363.7080201@codemonkey.ws> In-Reply-To: <4DD52363.7080201@codemonkey.ws> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC] Memory API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: Peter Maydell , Avi Kivity , Gleb Natapov , qemu-devel On 2011-05-19 16:04, Anthony Liguori wrote: > On 05/19/2011 08:57 AM, Jan Kiszka wrote: >> On 2011-05-19 15:52, Anthony Liguori wrote: >>> On 05/19/2011 03:30 AM, Jan Kiszka wrote: >>>> On 2011-05-19 10:26, Gleb Natapov wrote: >>>>> On Wed, May 18, 2011 at 09:27:55PM +0200, Jan Kiszka wrote: >>>>>>> if an I/O is to the APIC page, >>>>>>> it's handled by the APIC >>>>>> >>>>>> That's not that simple. We need to tell apart: >>>>>> - if a cpu issued the request, and which one => forward to APIC >>>>> And cpu mode may affect where access is forwarded to. If cpu is in SMM >>>>> mode access to frame buffer may be forwarded to a memory (depends on >>>>> chipset configuration). >>>> >>>> So we have a second use case for CPU-local I/O regions? >>>> >>>> I wonder if only a single CPU can enter SMM or if all have to. >>> >>> For the i440fx, it's a chipset register (not a per-CPU register). >> >> There are two sources: the chipset register and the mode of the first >> CPU. Both things were apparently incorrectly merged into the >> minimalistic i440fx model. > > Right, the chipset register is mainly used to program the contents of SMM. > > There is a single access pin that has effectively the same semantics as > setting the chipset register. > > It's not a per-CPU setting--that's the point. You can't have one CPU > reading SMM memory at the exactly same time as accessing VGA. > > But I guess you can never have two simultaneous accesses anyway so > perhaps it's splitting hairs :-) Not sure. If one CPU enters SMM, it must be able to read SMRAM content, independently of the second CPU - unless there is some magic to stop that CPU in the meantime. Jan -- Siemens AG, Corporate Technology, CT T DE IT 1 Corporate Competence Center Embedded Linux