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Date: Thu, 19 May 2011 20:21:15 +0200
From: Jan Kiszka <jan.kiszka@web.de>
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Subject: Re: [Qemu-devel] [RFC] Memory API
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To: Anthony Liguori <anthony@codemonkey.ws>
Cc: Avi Kivity <avi@redhat.com>, Gleb Natapov <gleb@redhat.com>, qemu-devel <qemu-devel@nongnu.org>

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On 2011-05-19 20:06, Anthony Liguori wrote:
> On 05/19/2011 08:55 AM, Avi Kivity wrote:
>> On 05/19/2011 04:50 PM, Anthony Liguori wrote:
>>>
>>> But the i440fx doesn't register the VGA region. The PIIX3 (ISA bus)
>>> does, so how does it know what the priority of that mapping is?
>>>
>>
>> The PCI bridge also has a say, no?
>=20
> For legacy VGA memory?  That's a good question.  I've always assumed
> that legacy VGA memory is handled directly in the chipset by redirectin=
g
> writes to the first VGA adapter it encounters (which usually happens to=

> be the builtin one these days).

Nope. It's well defined in the PCI specs that every PCI-PCI bridge can
(or have to? need to check) control the flow of legacy VGA to its
downstream devices.

>=20
> I'm not sure it's possible to have a VGA device behind a bridge that
> also handles legacy VGA memory because the bridge pretty clearly can
> only have BARs within a certain region of memory (based on the bridge's=

> config space).

That's part of my notebook PCI tree, I bet you have something similar:

 \-[0000:00]-+-00.0  Intel Corporation Core Processor DRAM Controller
             +-01.0-[01]--+-00.0  nVidia Corporation GT216 [Quadro FX 880=
M]
             |            \-00.1  nVidia Corporation High Definition Audi=
o Controller

So even this single, though not built-in VGA adapter is behind a bridge.

And if you look closer, you can find:

00:01.0 PCI bridge: Intel Corporation Core Processor PCI Express x16 Root=
 Port (rev 02) (prog-if 00 [Normal decode])
        Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParEr=
r- Stepping- SERR- FastB2B- DisINTx+
        Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=3Dfast >TAbort- =
<TAbort- <MAbort- >SERR- <PERR- INTx-
        Latency: 0, Cache Line Size: 64 bytes
        Bus: primary=3D00, secondary=3D01, subordinate=3D01, sec-latency=3D=
0
        I/O behind bridge: 00002000-00002fff
        Memory behind bridge: cc000000-cdefffff
        Prefetchable memory behind bridge: 00000000ce000000-00000000dffff=
fff
        Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=3Dfast >TAbort- =
<TAbort- <MAbort- <SERR- <PERR-
        BridgeCtl: Parity- SERR+ NoISA- VGA+ MAbort- >Reset- FastB2B-
                PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
=2E..

Note that 'VGA+' in BridgeCtl. It allows the NVIDIA adapter to handle
legacy VGA.

Jan


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