Re: [Qemu-devel] [PATCH 21/26] target-xtensa: implement unaligned exception option

[Richard Henderson <rth@twiddle.net>]

On 05/17/2011 03:32 PM, Max Filippov wrote:
> See ISA, 4.4.4 for details.
> 
> Correct (aligned as per ISA) address for unaligned access is generated
> in case this option is not enabled.
> 
> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
> ---
>  target-xtensa/translate.c |   33 +++++++++++++++++++++++++++++++--
>  1 files changed, 31 insertions(+), 2 deletions(-)
> 
> diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
> index 592072a..6e66f3f 100644
> --- a/target-xtensa/translate.c
> +++ b/target-xtensa/translate.c
> @@ -177,6 +177,16 @@ static void gen_exception_cause(DisasContext *dc, uint32_t cause)
>      tcg_temp_free(_cause);
>  }
>  
> +static void gen_exception_cause_vaddr(DisasContext *dc, uint32_t cause,
> +        TCGv_i32 vaddr)
> +{
> +    TCGv_i32 _pc = tcg_const_i32(dc->pc);
> +    TCGv_i32 _cause = tcg_const_i32(cause);
> +    gen_helper_exception_cause_vaddr(_pc, _cause, vaddr);
> +    tcg_temp_free(_pc);
> +    tcg_temp_free(_cause);
> +}
> +
>  static void gen_check_privilege(DisasContext *dc)
>  {
>      if (dc->mem_idx) {
> @@ -349,6 +359,20 @@ static void gen_wsr(DisasContext *dc, uint32_t sr, TCGv_i32 s)
>      }
>  }
>  
> +static void gen_load_store_alignment(DisasContext *dc, int shift, TCGv_i32 addr)
> +{
> +    TCGv_i32 tmp = tcg_temp_local_new_i32();
> +    tcg_gen_mov_i32(tmp, addr);
> +    tcg_gen_andi_i32(addr, addr, ~0 << shift);
> +    if (option_enabled(dc, XTENSA_OPTION_UNALIGNED_EXCEPTION)) {
> +        int label = gen_new_label();
> +        tcg_gen_brcond_i32(TCG_COND_EQ, addr, tmp, label);
> +        gen_exception_cause_vaddr(dc, LOAD_STORE_ALIGNMENT_CAUSE, tmp);
> +        gen_set_label(label);
> +    }
> +    tcg_temp_free(tmp);
> +}

This is not the correct method for this.  Set ALIGNED_ONLY before
defining the softmmu_templates.  Define do_unaligned_access to raise
the exception.  See e.g. target-sparc/op_helper.c.


r~