From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sylwester Nawrocki Date: Wed, 22 Jun 2011 20:33:24 +0000 Subject: Re: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD Message-Id: <4E025194.5040603@gmail.com> List-Id: References: <1308724904-31521-1-git-send-email-jg1.han@samsung.com> <002901cc30c1$5ac6ef70$1054ce50$%szyprowski@samsung.com> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: Anand Kumar N Cc: Marek Szyprowski , Jingoo Han , Kukjin Kim , Paul Mundt , linux-samsung-soc@vger.kernel.org, linux-fbdev@vger.kernel.org, Jonghun Han , Thomas Abraham , Sylwester Nawrocki , Kyungmin Park , Inki Dae , ARM Linux , Ben Dooks On 06/22/2011 03:25 PM, Anand Kumar N wrote: > Instead of hardcoding the parent clock in platform/bootloader code ,is > it not possible to select/set the > parent clock based on the pixel clk(plat data) having the least delta > with the 9 src clks.with this change I have checked it for WA101S. While at first sight this may look as an awesome idea I don't really believe it is. There might be other criteria that need to be considered, like continuous clock availability or frequency stability. That said we could possibly have the driver setting sclk_fimd frequency based on display planes' properties (this was my initial suggestion) but sclk_fimd parent should be fixed either by bootloader or board initialization code. From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sylwester Nawrocki Subject: Re: [PATCH V5 5/5] ARM: EXYNOS4: Add platform data for EXYNOS4 FIMD and LTE480WV platform-lcd Date: Wed, 22 Jun 2011 22:33:24 +0200 Message-ID: <4E025194.5040603@gmail.com> References: <1308724904-31521-1-git-send-email-jg1.han@samsung.com> <002901cc30c1$5ac6ef70$1054ce50$%szyprowski@samsung.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-path: Received: from mail-fx0-f46.google.com ([209.85.161.46]:54466 "EHLO mail-fx0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1758077Ab1FVUdc (ORCPT ); Wed, 22 Jun 2011 16:33:32 -0400 In-Reply-To: Sender: linux-samsung-soc-owner@vger.kernel.org List-Id: linux-samsung-soc@vger.kernel.org To: Anand Kumar N Cc: Marek Szyprowski , Jingoo Han , Kukjin Kim , Paul Mundt , linux-samsung-soc@vger.kernel.org, linux-fbdev@vger.kernel.org, Jonghun Han , Thomas Abraham , Sylwester Nawrocki , Kyungmin Park , Inki Dae , ARM Linux , Ben Dooks On 06/22/2011 03:25 PM, Anand Kumar N wrote: > Instead of hardcoding the parent clock in platform/bootloader code ,is > it not possible to select/set the > parent clock based on the pixel clk(plat data) having the least delta > with the 9 src clks.with this change I have checked it for WA101S. While at first sight this may look as an awesome idea I don't really believe it is. There might be other criteria that need to be considered, like continuous clock availability or frequency stability. That said we could possibly have the driver setting sclk_fimd frequency based on display planes' properties (this was my initial suggestion) but sclk_fimd parent should be fixed either by bootloader or board initialization code.