[U-Boot] Is somebody workin on getting the AT91SAM9G45EKES working on the latest build?

[U-Boot] Is somebody workin on getting the AT91SAM9G45EKES working on the latest build?

[William C. Landolina]

I need the AT91SAM9G45 port - if I need to bring it up to date to keep it  among the living I will volunteer, but if one of the usual AT91 maintainers is already working on it I suspect they can do it more easily than I.

I can start work on the 9G45 update in early July if necessary.  

Thanks,

Bill Landolina
Technology Atlanta Corporation
500 Sugar Mill Road - Suite 202A
Atlanta, Georgia  30350

(404) 303-0446 (Voice)
(678) 596-3625 (Cell)
wcl at techatl.com

[U-Boot] Is somebody workin on getting the AT91SAM9G45EKES working on the latest build?

[Alex Waterman]

Bill,

> I can start work on the 9G45 update in early July if necessary.  

I have been using this board as well. I managed to fix my compilation locally. The patch I submitted was before a lot of the updates for the over all ARM stuff went through. I am pretty sure it should still apply though. I could repost it if you are interested.

Best regards,
Alex

-- 
Alex Waterman
Computer Engineer
Phone: 215-896-4920
Email: awaterman at dawning.com

[U-Boot] Is somebody workin on getting the AT91SAM9G45EKES working on the latest build?

[Albert ARIBAUD]

Hi Aex,

Le 30/06/2011 14:32, Alex Waterman a ?crit :
>
> Bill,
>
>> I can start work on the 9G45 update in early July if necessary.
>
> I have been using this board as well. I managed to fix my compilation locally. The patch I submitted was before a lot of the updates for the over all ARM stuff went through. I am pretty sure it should still apply though. I could repost it if you are interested.

In this case please first, make sure it does apply cleanly, and second, 
add the board maintainer and the Atmel custodian as Cc: when you post it.

> Best regards,
> Alex

Amicalement,
-- 
Albert.

[U-Boot] [PATCH 0/8] Fixes compilation for the at91sam9m10g45ek

[Alex.Waterman.awaterman at dawning.com]

From: Alex Waterman <awaterman@dawning.com>

This patch set fixes the at91sam9mg45ek build for my set up. I have
only been able to test this patch on my own NAND booting 
at91sam9m10g45ek. Dataflash and norflash are untested. Anyway,
this is a rough approximation of a patch; I would need more input
from people with nor-flash, working at91bootstrapers, dataflash,
etc before I can get truely generic working at91sam9m10g45ek board
support.

Also, some notes:

I wrote my own boot strapper because I could not find a working
boot strapper. The boot strappers I found on the web either had their
own issues or did not enable the second bank of RAM. Thus I wrote my
own that works and enables the second bank of RAM. The patch here
expects that the second bank works. If you are using a working
at91bootstrapper or the like, I don't think that should cause this
u-boot patch to not work; just set the number of banks back to 1 in
the config file.

If I am not alone in having trouble with the existing at91bootstrap
projects, maybe we could merge my bootstrapper into (or the preexisting
at91bootstrapper proejcts) into the NAND SPL (for NAND booting boards)
section of U-Boot?

Alex Waterman (8):
  Remove old config stuff from Makefile
  Update at91sam9m10g45_devices.c to fix compile errors.
  Fix compile problem for some boards in the clock code.
  Updates the at91sam9mg45_matrix.h header to new defines.
  Updates the board specific files for the at91sam9mg45ek.
  Adds wait to atmel_usart serial_init function
  Updates the at91sam9m10g45ek.h config file.
  Updates the boards.cfg file

 Makefile                                           |   21 ---
 .../cpu/arm926ejs/at91/at91sam9m10g45_devices.c    |   26 ++--
 arch/arm/cpu/arm926ejs/at91/clock.c                |    4 +
 .../arm/include/asm/arch-at91/at91sam9g45_matrix.h |   84 +++++-----
 board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c    |  128 +++++++-------
 board/atmel/at91sam9m10g45ek/led.c                 |    6 +-
 boards.cfg                                         |    1 +
 drivers/serial/atmel_usart.c                       |    6 +
 include/configs/at91sam9m10g45ek.h                 |  188 ++++++++++++--------
 9 files changed, 246 insertions(+), 218 deletions(-)

-- 
1.7.4.4

[U-Boot] [PATCH 1/8] Remove old config stuff from Makefile

[Alex.Waterman.awaterman at dawning.com]

From: Alex Waterman <awaterman@dawning.com>

Start the process of pushing the at91sam9m10g45ek* boards to
the new builds.cfg configuration style. At the moment just the
generic config is available, add the rest as necessary.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
---
 Makefile |   21 ---------------------
 1 files changed, 0 insertions(+), 21 deletions(-)

diff --git a/Makefile b/Makefile
index 3454db6..63acc94 100644
--- a/Makefile
+++ b/Makefile
@@ -850,27 +850,6 @@ at91sam9rlek_config	:	unconfig
 	fi;
 	@$(MKCONFIG) -n $@ -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
 
-at91sam9m10g45ek_nandflash_config \
-at91sam9m10g45ek_dataflash_config \
-at91sam9m10g45ek_dataflash_cs0_config \
-at91sam9m10g45ek_config \
-at91sam9g45ekes_nandflash_config \
-at91sam9g45ekes_dataflash_config \
-at91sam9g45ekes_dataflash_cs0_config \
-at91sam9g45ekes_config	:	unconfig
-	@mkdir -p $(obj)include
-		@if [ "$(findstring 9m10,$@)" ] ; then \
-		echo "#define CONFIG_AT91SAM9M10G45EK 1"	>>$(obj)include/config.h ; \
-	else \
-		echo "#define CONFIG_AT91SAM9G45EKES 1"	>>$(obj)include/config.h ; \
-	fi;
-	@if [ "$(findstring _nandflash,$@)" ] ; then \
-		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
-	else \
-		echo "#define CONFIG_ATMEL_SPI 1"	>>$(obj)include/config.h ; \
-	fi;
-	@$(MKCONFIG) -n $@ -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91
-
 pm9g45_config	:	unconfig
 	@mkdir -p $(obj)include
 	@$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91
-- 
1.7.4.4

[U-Boot] [PATCH 2/8] Update at91sam9m10g45_devices.c to fix compile errors.

[Alex.Waterman.awaterman at dawning.com]

From: Alex Waterman <awaterman@dawning.com>

Move this file to the new ATMEL_BASE_* and ATMEL_ID_* defines.

Also fixed a problem appearing in the ethernet initialization where
the entire board was being reset, not just the ethernet controller.
This at least makes ethernet work on my board if the correct
environment (mac address, ip address, etc) is available on boot.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
---
 .../cpu/arm926ejs/at91/at91sam9m10g45_devices.c    |   26 ++++++++++----------
 1 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
index 4ad9b1f..9ef8966 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
@@ -26,42 +26,42 @@
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+#include <asm/io.h>
 
 void at91_serial0_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTB, 19, 1);	/* TXD0 */
 	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* RXD0 */
-	writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer);
+	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
 }
 
 void at91_serial1_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD1 */
 	at91_set_a_periph(AT91_PIO_PORTB, 5, 0);		/* RXD1 */
-	writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer);
+	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
 }
 
 void at91_serial2_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTD, 6, 1);		/* TXD2 */
 	at91_set_a_periph(AT91_PIO_PORTD, 7, 0);		/* RXD2 */
-	writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer);
+	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
 }
 
 void at91_serial3_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* DRXD */
 	at91_set_a_periph(AT91_PIO_PORTB, 13, 1);	/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
+	writel(1 << ATMEL_ID_USART3, &pmc->pcer);
 }
 
 void at91_serial_hw_init(void)
@@ -86,14 +86,14 @@ void at91_serial_hw_init(void)
 #ifdef CONFIG_ATMEL_SPI
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* SPI0_MISO */
 	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* SPI0_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* SPI0_SPCK */
 
 	/* Enable clock */
-	writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer);
+	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTB, 3, 0);
@@ -123,14 +123,14 @@ void at91_spi0_hw_init(unsigned long cs_mask)
 
 void at91_spi1_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_MISO */
 	at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* SPI1_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* SPI1_SPCK */
 
 	/* Enable clock */
-	writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer);
+	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTB, 17, 0);
-- 
1.7.4.4

[U-Boot] [PATCH 3/8] Fix compile problem for some boards in the clock code.

[Alex.Waterman.awaterman at dawning.com]

From: Alex Waterman <awaterman@dawning.com>

Some boards use AT91_SLOW_CLOCK and other use
CONFIG_SYS_AT91_SLOW_CLOCK. This patch makes it so the arm926ejs
clock code will return which ever is set.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
---
 arch/arm/cpu/arm926ejs/at91/clock.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c
index 608af2c..0083bd2 100644
--- a/arch/arm/cpu/arm926ejs/at91/clock.c
+++ b/arch/arm/cpu/arm926ejs/at91/clock.c
@@ -57,7 +57,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
 {
 	switch (css) {
 	case AT91_PMC_MCKR_CSS_SLOW:
+#ifdef AT91_SLOW_CLOCK
+		return AT91_SLOW_CLOCK;
+#else
 		return CONFIG_SYS_AT91_SLOW_CLOCK;
+#endif
 	case AT91_PMC_MCKR_CSS_MAIN:
 		return gd->main_clk_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLA:
-- 
1.7.4.4

[U-Boot] [PATCH 4/8] Updates the at91sam9mg45_matrix.h header to new defines.

[Alex.Waterman.awaterman at dawning.com]

From: Alex Waterman <awaterman@dawning.com>

Moves the at91sam9g45_matrix.h header file to use the new
ATMEL_BASE_MATRIX define.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
---
 .../arm/include/asm/arch-at91/at91sam9g45_matrix.h |   84 ++++++++++----------
 1 files changed, 42 insertions(+), 42 deletions(-)

diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h
index 1620e1b..9808e38 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h
@@ -15,18 +15,18 @@
 #ifndef AT91SAM9G45_MATRIX_H
 #define AT91SAM9G45_MATRIX_H
 
-#define AT91_MATRIX_MCFG0	(AT91_MATRIX + 0x00)	/* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1	(AT91_MATRIX + 0x04)	/* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2	(AT91_MATRIX + 0x08)	/* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3	(AT91_MATRIX + 0x0C)	/* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4	(AT91_MATRIX + 0x10)	/* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5	(AT91_MATRIX + 0x14)	/* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6	(AT91_MATRIX + 0x18)	/* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7	(AT91_MATRIX + 0x1C)	/* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8	(AT91_MATRIX + 0x20)	/* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9	(AT91_MATRIX + 0x24)	/* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10	(AT91_MATRIX + 0x28)	/* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11	(AT91_MATRIX + 0x2C)	/* Master Configuration Register 11 */
+#define AT91_MATRIX_MCFG0	(ATMEL_BASE_MATRIX + 0x00)	/* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1	(ATMEL_BASE_MATRIX + 0x04)	/* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2	(ATMEL_BASE_MATRIX + 0x08)	/* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3	(ATMEL_BASE_MATRIX + 0x0C)	/* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4	(ATMEL_BASE_MATRIX + 0x10)	/* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5	(ATMEL_BASE_MATRIX + 0x14)	/* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6	(ATMEL_BASE_MATRIX + 0x18)	/* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7	(ATMEL_BASE_MATRIX + 0x1C)	/* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8	(ATMEL_BASE_MATRIX + 0x20)	/* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG9	(ATMEL_BASE_MATRIX + 0x24)	/* Master Configuration Register 9 */
+#define AT91_MATRIX_MCFG10	(ATMEL_BASE_MATRIX + 0x28)	/* Master Configuration Register 10 */
+#define AT91_MATRIX_MCFG11	(ATMEL_BASE_MATRIX + 0x2C)	/* Master Configuration Register 11 */
 #define		AT91_MATRIX_ULBT	(7 << 0)	/* Undefined Length Burst Type */
 #define			AT91_MATRIX_ULBT_INFINITE	(0 << 0)
 #define			AT91_MATRIX_ULBT_SINGLE		(1 << 0)
@@ -37,14 +37,14 @@
 #define			AT91_MATRIX_ULBT_SIXTYFOUR	(6 << 0)
 #define			AT91_MATRIX_ULBT_128		(7 << 0)
 
-#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x40)	/* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x44)	/* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x48)	/* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x4C)	/* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x50)	/* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5	(AT91_MATRIX + 0x54)	/* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6	(AT91_MATRIX + 0x58)	/* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7	(AT91_MATRIX + 0x5C)	/* Slave Configuration Register 7 */
+#define AT91_MATRIX_SCFG0	(ATMEL_BASE_MATRIX + 0x40)	/* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1	(ATMEL_BASE_MATRIX + 0x44)	/* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2	(ATMEL_BASE_MATRIX + 0x48)	/* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3	(ATMEL_BASE_MATRIX + 0x4C)	/* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4	(ATMEL_BASE_MATRIX + 0x50)	/* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5	(ATMEL_BASE_MATRIX + 0x54)	/* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6	(ATMEL_BASE_MATRIX + 0x58)	/* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7	(ATMEL_BASE_MATRIX + 0x5C)	/* Slave Configuration Register 7 */
 #define		AT91_MATRIX_SLOT_CYCLE		(0x1ff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
 #define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
 #define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
@@ -52,22 +52,22 @@
 #define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
 #define		AT91_MATRIX_FIXED_DEFMSTR	(0xf  << 18)	/* Fixed Index of Default Master */
 
-#define AT91_MATRIX_PRAS0	(AT91_MATRIX + 0x80)	/* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0	(AT91_MATRIX + 0x84)	/* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1	(AT91_MATRIX + 0x88)	/* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1	(AT91_MATRIX + 0x8C)	/* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2	(AT91_MATRIX + 0x90)	/* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2	(AT91_MATRIX + 0x94)	/* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3	(AT91_MATRIX + 0x98)	/* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3	(AT91_MATRIX + 0x9C)	/* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4	(AT91_MATRIX + 0xA0)	/* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4	(AT91_MATRIX + 0xA4)	/* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5	(AT91_MATRIX + 0xA8)	/* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5	(AT91_MATRIX + 0xAC)	/* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6	(AT91_MATRIX + 0xB0)	/* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6	(AT91_MATRIX + 0xB4)	/* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7	(AT91_MATRIX + 0xB8)	/* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7	(AT91_MATRIX + 0xBC)	/* Priority Register B for Slave 7 */
+#define AT91_MATRIX_PRAS0	(ATMEL_BASE_MATRIX + 0x80)	/* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0	(ATMEL_BASE_MATRIX + 0x84)	/* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1	(ATMEL_BASE_MATRIX + 0x88)	/* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1	(ATMEL_BASE_MATRIX + 0x8C)	/* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2	(ATMEL_BASE_MATRIX + 0x90)	/* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2	(ATMEL_BASE_MATRIX + 0x94)	/* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3	(ATMEL_BASE_MATRIX + 0x98)	/* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3	(ATMEL_BASE_MATRIX + 0x9C)	/* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4	(ATMEL_BASE_MATRIX + 0xA0)	/* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4	(ATMEL_BASE_MATRIX + 0xA4)	/* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5	(ATMEL_BASE_MATRIX + 0xA8)	/* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5	(ATMEL_BASE_MATRIX + 0xAC)	/* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6	(ATMEL_BASE_MATRIX + 0xB0)	/* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6	(ATMEL_BASE_MATRIX + 0xB4)	/* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7	(ATMEL_BASE_MATRIX + 0xB8)	/* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7	(ATMEL_BASE_MATRIX + 0xBC)	/* Priority Register B for Slave 7 */
 #define		AT91_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
 #define		AT91_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
 #define		AT91_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
@@ -81,7 +81,7 @@
 #define		AT91_MATRIX_M10PR		(3 << 8)	/* Master 10 Priority (in Register B) */
 #define		AT91_MATRIX_M11PR		(3 << 12)	/* Master 11 Priority (in Register B) */
 
-#define AT91_MATRIX_MRCR	(AT91_MATRIX + 0x100)	/* Master Remap Control Register */
+#define AT91_MATRIX_MRCR	(ATMEL_BASE_MATRIX + 0x100)	/* Master Remap Control Register */
 #define		AT91_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define		AT91_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 #define		AT91_MATRIX_RCB2		(1 << 2)
@@ -95,7 +95,7 @@
 #define		AT91_MATRIX_RCB10		(1 << 10)
 #define		AT91_MATRIX_RCB11		(1 << 11)
 
-#define AT91_MATRIX_TCMR	(AT91_MATRIX + 0x110)	/* TCM Configuration Register */
+#define AT91_MATRIX_TCMR	(ATMEL_BASE_MATRIX + 0x110)	/* TCM Configuration Register */
 #define		AT91_MATRIX_ITCM_SIZE		(0xf << 0)	/* Size of ITCM enabled memory block */
 #define			AT91_MATRIX_ITCM_0		(0 << 0)
 #define			AT91_MATRIX_ITCM_32		(6 << 0)
@@ -107,12 +107,12 @@
 #define			AT91_MATRIX_TCM_NO_WS		(0x0 << 11)
 #define			AT91_MATRIX_TCM_ONE_WS		(0x1 << 11)
 
-#define AT91_MATRIX_VIDEO	(AT91_MATRIX + 0x118)	/* Video Mode Configuration Register */
+#define AT91_MATRIX_VIDEO	(ATMEL_BASE_MATRIX + 0x118)	/* Video Mode Configuration Register */
 #define		AT91C_VDEC_SEL			(0x1 <<  0) /* Video Mode Selection */
 #define			AT91C_VDEC_SEL_OFF		(0 << 0)
 #define			AT91C_VDEC_SEL_ON		(1 << 0)
 
-#define AT91_MATRIX_EBICSA	(AT91_MATRIX + 0x128)	/* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_EBICSA	(ATMEL_BASE_MATRIX + 0x128)	/* EBI Chip Select Assignment Register */
 #define		AT91_MATRIX_EBI_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
 #define			AT91_MATRIX_EBI_CS1A_SMC		(0 << 1)
 #define			AT91_MATRIX_EBI_CS1A_SDRAMC		(1 << 1)
@@ -138,13 +138,13 @@
 #define			AT91_MATRIX_EBI_DDR_IOSR_REDUCED	(0 << 18)
 #define			AT91_MATRIX_EBI_DDR_IOSR_NORMAL		(1 << 18)
 
-#define AT91_MATRIX_WPMR	(AT91_MATRIX + 0x1E4)	/* Write Protect Mode Register */
+#define AT91_MATRIX_WPMR	(ATMEL_BASE_MATRIX + 0x1E4)	/* Write Protect Mode Register */
 #define		AT91_MATRIX_WPMR_WPEN		(1 << 0)	/* Write Protect ENable */
 #define			AT91_MATRIX_WPMR_WP_WPDIS		(0 << 0)
 #define			AT91_MATRIX_WPMR_WP_WPEN		(1 << 0)
 #define		AT91_MATRIX_WPMR_WPKEY		(0xFFFFFF << 8)	/* Write Protect KEY */
 
-#define AT91_MATRIX_WPSR	(AT91_MATRIX + 0x1E8)	/* Write Protect Status Register */
+#define AT91_MATRIX_WPSR	(ATMEL_BASE_MATRIX + 0x1E8)	/* Write Protect Status Register */
 #define		AT91_MATRIX_WPSR_WPVS		(1 << 0)	/* Write Protect Violation Status */
 #define			AT91_MATRIX_WPSR_NO_WPV		(0 << 0)
 #define			AT91_MATRIX_WPSR_WPV		(1 << 0)
-- 
1.7.4.4

[U-Boot] [PATCH 5/8] Updates the board specific files for the at91sam9mg45ek.

[Alex.Waterman.awaterman at dawning.com]

From: Alex Waterman <awaterman@dawning.com>

Fixes the compile errors in the board specific initializations for
the at91sam9m10g45ek specific files.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
---
 board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c |  128 +++++++++++------------
 board/atmel/at91sam9m10g45ek/led.c              |    6 +-
 2 files changed, 67 insertions(+), 67 deletions(-)

diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index f92b20f..f8e687e 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -23,6 +23,7 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/sizes.h>
 #include <asm/arch/at91sam9g45.h>
 #include <asm/arch/at91sam9_matrix.h>
@@ -32,7 +33,6 @@
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
 #include <asm/arch/hardware.h>
 #include <lcd.h>
 #include <atmel_lcdc.h>
@@ -41,6 +41,14 @@
 #endif
 #include <netdev.h>
 
+/*
+ * arch/arm/include/asm/arch-at91/at91sam9g45.h defines ATMEL_BASE_SCM;
+ * however, other code still wants AT91_SMC instead. Likewise for the AT91_PMC
+ * definition.
+ */
+#define AT91_SMC		ATMEL_BASE_SMC
+#define AT91_PMC		ATMEL_BASE_PMC
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /* ------------------------------------------------------------------------- */
@@ -49,35 +57,35 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 
 #ifdef CONFIG_CMD_NAND
-static void at91sam9m10g45ek_nand_hw_init(void)
+void at91sam9m10g45ek_nand_hw_init(void)
 {
 	unsigned long csa;
 
 	/* Enable CS3 */
-	csa = at91_sys_read(AT91_MATRIX_EBICSA);
-	at91_sys_write(AT91_MATRIX_EBICSA,
-		       csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+	csa = readl(AT91_MATRIX_EBICSA);
+	writel(csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA, AT91_MATRIX_EBICSA);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
-	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(3),
-		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
-		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2));
-	at91_sys_write(AT91_SMC_CYCLE(3),
-		       AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4));
-	at91_sys_write(AT91_SMC_MODE(3),
-		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		       AT91_SMC_EXNWMODE_DISABLE |
+	writel(AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+	       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0),
+	       AT91_SMC_SETUP(3));
+	writel(AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
+	       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2),
+	       AT91_SMC_PULSE(3));
+
+	writel(AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4),
+	       AT91_SMC_CYCLE(3));
+	writel(AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+	       AT91_SMC_EXNWMODE_DISABLE |
 #ifdef CONFIG_SYS_NAND_DBW_16
 		       AT91_SMC_DBW_16 |
 #else /* CONFIG_SYS_NAND_DBW_8 */
 		       AT91_SMC_DBW_8 |
 #endif
-		       AT91_SMC_TDF_(3));
+	       AT91_SMC_TDF_(3),
+	       AT91_SMC_MODE(3));
 
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC);
+	writel(1 << ATMEL_ID_PIOC, AT91_PMC_PCER);
 
 	/* Configure RDY/BSY */
 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -90,7 +98,7 @@ static void at91sam9m10g45ek_nand_hw_init(void)
 #ifdef CONFIG_CMD_USB
 static void at91sam9m10g45ek_usb_hw_init(void)
 {
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE);
+	writel(1 << ATMEL_ID_PIODE, AT91_PMC_PCER);
 
 	at91_set_gpio_output(AT91_PIN_PD1, 0);
 	at91_set_gpio_output(AT91_PIN_PD3, 0);
@@ -100,48 +108,13 @@ static void at91sam9m10g45ek_usb_hw_init(void)
 #ifdef CONFIG_MACB
 static void at91sam9m10g45ek_macb_hw_init(void)
 {
-	unsigned long rstc;
 
 	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC);
-
-	/*
-	 * Disable pull-up on:
-	 *	RXDV (PA15) => PHY normal mode (not Test mode)
-	 * 	ERX0 (PA12) => PHY ADDR0
-	 *	ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
-	 *
-	 * PHY has internal pull-down
-	 */
-	writel(pin_to_mask(AT91_PIN_PA15) |
-	       pin_to_mask(AT91_PIN_PA12) |
-	       pin_to_mask(AT91_PIN_PA13),
-	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
-
-	rstc = at91_sys_read(AT91_RSTC_MR);
-
-	/* Need to reset PHY -> 500ms reset */
-	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
-				     AT91_RSTC_URSTEN);
-
-	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
-
-	/* Wait for end hardware reset */
-	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
-
-	/* Restore NRST value */
-	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     (rstc) |
-				     AT91_RSTC_URSTEN);
-
-	/* Re-enable pull-up */
-	writel(pin_to_mask(AT91_PIN_PA15) |
-	       pin_to_mask(AT91_PIN_PA12) |
-	       pin_to_mask(AT91_PIN_PA13),
-	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+	writel(1 << ATMEL_ID_EMAC, AT91_PMC_PCER);
 
+	/* And the pins. */
 	at91_macb_hw_init();
+
 }
 #endif
 
@@ -161,7 +134,7 @@ vidinfo_t panel_info = {
 	vl_vsync_len:	1,
 	vl_upper_margin:40,
 	vl_lower_margin:1,
-	mmio:		AT91SAM9G45_LCDC_BASE,
+	mmio :		 ATMEL_BASE_LCDC,
 };
 
 
@@ -208,7 +181,7 @@ static void at91sam9m10g45ek_lcd_hw_init(void)
 	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
 	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
 
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC);
+	writel(1 << ATMEL_ID_LCDC, AT91_PMC_PCER);
 
 	gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
 }
@@ -227,7 +200,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("(C) 2008 ATMEL Corp\n");
 	lcd_printf ("at91support at atmel.com\n");
 	lcd_printf ("%s CPU at %s MHz\n",
-		CONFIG_SYS_AT91_CPU_NAME,
+		ATMEL_CPU_NAME,
 		strmhz(temp, get_cpu_clk_rate()));
 
 	dram_size = 0;
@@ -257,7 +230,8 @@ int board_init(void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-	at91_serial_hw_init();
+
+
 #ifdef CONFIG_CMD_NAND
 	at91sam9m10g45ek_nand_hw_init();
 #endif
@@ -270,11 +244,9 @@ int board_init(void)
 #ifdef CONFIG_ATMEL_SPI
 	at91_spi0_hw_init(1 << 4);
 #endif
-
 #ifdef CONFIG_MACB
 	at91sam9m10g45ek_macb_hw_init();
 #endif
-
 #ifdef CONFIG_LCD
 	at91sam9m10g45ek_lcd_hw_init();
 #endif
@@ -283,9 +255,23 @@ int board_init(void)
 
 int dram_init(void)
 {
+	gd->ram_size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+void dram_init_banksize()
+{
+
+	/* Bank 1. */
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
-	return 0;
+
+	/* Bank 2. */
+#if (CONFIG_NR_DRAM_BANKS == 2)
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_SIZE_2;
+#endif
+
 }
 
 #ifdef CONFIG_RESET_PHY_R
@@ -298,7 +284,7 @@ int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
 #ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00);
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
 #endif
 	return rc;
 }
@@ -338,3 +324,15 @@ void spi_cs_deactivate(struct spi_slave *slave)
 	}
 }
 #endif /* CONFIG_ATMEL_SPI */
+
+extern void at91_serial_hw_init(void);
+/*
+ * (re)Initialize the serial hardware.
+ */
+int board_early_init_f(void)
+{
+
+	at91_serial_hw_init();
+	return 0;
+
+}
diff --git a/board/atmel/at91sam9m10g45ek/led.c b/board/atmel/at91sam9m10g45ek/led.c
index ff59a2d..b939c5b 100644
--- a/board/atmel/at91sam9m10g45ek/led.c
+++ b/board/atmel/at91sam9m10g45ek/led.c
@@ -23,15 +23,17 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/at91sam9g45.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+
+#define AT91_PMC		ATMEL_BASE_PMC
 
 void coloured_LED_init(void)
 {
 	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE);
+	writel(AT91_PMC_PCER, 1 << ATMEL_ID_PIODE);
 
 	at91_set_gpio_output(CONFIG_RED_LED, 1);
 	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
-- 
1.7.4.4

[U-Boot] [PATCH 6/8] Adds wait to atmel_usart serial_init function

[Alex.Waterman.awaterman at dawning.com]

From: Alex Waterman <awaterman@dawning.com>

Adds a short busy loop wait to the atmel_usart.c serial_init()
function.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
---
 drivers/serial/atmel_usart.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index e326b2b..e355706 100644
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -47,6 +47,8 @@ void serial_setbrg(void)
 
 int serial_init(void)
 {
+
+	volatile int i = 0;
 	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
 
 	writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
@@ -61,6 +63,10 @@ int serial_init(void)
 			   | USART3_BF(NBSTOP, USART3_NBSTOP_1)),
 			   &usart->mr);
 
+	/* Short wait to let the serial port init. */
+	for (; i < 10000; i++)
+		;
+
 	return 0;
 }
 
-- 
1.7.4.4

[U-Boot] [PATCH 7/8] Updates the at91sam9m10g45ek.h config file.

[Alex.Waterman.awaterman at dawning.com]

From: Alex Waterman <awaterman@dawning.com>

Moves to using newer defines and adds possible support for the
second bank of RAM (if so desired).

Also, some coding clean up: removed the needless define to 1s for
defines that just act as flags.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
---
 include/configs/at91sam9m10g45ek.h |  188 +++++++++++++++++++++--------------
 1 files changed, 113 insertions(+), 75 deletions(-)

diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index de74dcf..5e02dde 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -27,48 +27,65 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+/*#define DEBUG*/
+
 #define CONFIG_AT91_LEGACY
+#define CONFIG_ATMEL_LEGACY
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* from 12 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000 /* from 12 MHz crystal */
+#define AT91_SLOW_CLOCK		32768
 #define CONFIG_SYS_HZ		1000
 
-#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
-#ifdef CONFIG_AT91SAM9M10G45EK
-#define CONFIG_AT91SAM9M10G45	1	/* It's an Atmel AT91SAM9M10G45 SoC*/
-#else
-#define CONFIG_AT91SAM9G45	1	/* It's an Atmel AT91SAM9G45 SoC*/
-#endif
+#define CONFIG_AT91SAM9M10G45
+#define CONFIG_AT91FAMILY
 #define CONFIG_ARCH_CPU_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 
-#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	1
+#define CONFIGMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
+#define ATMEL_PIO_PORTS		5 /* 5 PIO ports. */
+#define CONFIG_SYS_SDRAM_BASE   0x70000000
+
 /*
  * Hardware drivers
  */
-#define CONFIG_AT91_GPIO	1
-#define CONFIG_ATMEL_USART	1
+#define CONFIG_AT91_GPIO
+#define CONFIG_ATMEL_USART
 #undef CONFIG_USART0
 #undef CONFIG_USART1
 #undef CONFIG_USART2
-#define CONFIG_USART3		1	/* USART 3 is DBGU */
+#define CONFIG_USART3		/* USART 3 is DBGU */
+#define CONFIG_USART_BASE	0xffffee00 /* Use the DBGU hardware. */
+#define CONFIG_USART_ID		10
+
+/*
+ * This needs to be defined for the OHCI code to work but it is defined as
+ * ATMEL_ID_UHPHS in the CPU specific header files.
+ */
+#define ATMEL_ID_UHP		ATMEL_ID_UHPHS
+
+/*
+ * Specify the clock enable bit in the PMC_SCER register.
+ */
+#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
 
 /* LCD */
-#define CONFIG_LCD			1
+#define CONFIG_LCD
 #define LCD_BPP				LCD_COLOR8
-#define CONFIG_LCD_LOGO			1
+#define CONFIG_LCD_LOGO
 #undef LCD_TEST_PATTERN
-#define CONFIG_LCD_INFO			1
-#define CONFIG_LCD_INFO_BELOW_LOGO	1
-#define CONFIG_SYS_WHITE_ON_BLACK		1
-#define CONFIG_ATMEL_LCD		1
-#define CONFIG_ATMEL_LCD_RGB565		1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_ATMEL_LCD
+#define CONFIG_ATMEL_LCD_RGB565
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 /* board specific(not enough SRAM) */
 #define CONFIG_AT91SAM9G45_LCD_BASE		0x73E00000
 
@@ -82,10 +99,10 @@
 /*
  * BOOTP options
  */
-#define CONFIG_BOOTP_BOOTFILESIZE	1
-#define CONFIG_BOOTP_BOOTPATH		1
-#define CONFIG_BOOTP_GATEWAY		1
-#define CONFIG_BOOTP_HOSTNAME		1
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
 
 /*
  * Command line configuration.
@@ -98,35 +115,37 @@
 #undef CONFIG_CMD_AUTOSCRIPT
 #undef CONFIG_CMD_LOADS
 
-#define CONFIG_CMD_PING		1
-#define CONFIG_CMD_DHCP		1
-#define CONFIG_CMD_NAND		1
-#define CONFIG_CMD_USB		1
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
 
 /* SDRAM */
-#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_NR_DRAM_BANKS		2
 #define PHYS_SDRAM			0x70000000
 #define PHYS_SDRAM_SIZE			0x08000000	/* 128 megs */
+#define PHYS_SDRAM_2			0x20000000
+#define PHYS_SDRAM_SIZE_2		0x08000000	/* 128 megs */
 
 /* DataFlash */
 #ifdef CONFIG_ATMEL_SPI
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH		1
-#define CONFIG_SPI_FLASH_ATMEL		1
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
 #define CONFIG_SYS_MAX_DATAFLASH_BANKS	1
 #endif
 
 /* NOR flash, if populated */
-#ifndef CONFIG_CMD_NAND
-#define CONFIG_SYS_NO_FLASH		1
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_NO_FLASH
 #else
-#define CONFIG_SYS_FLASH_CFI		1
-#define CONFIG_FLASH_CFI_DRIVER		1
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
 #define PHYS_FLASH_1			0x10000000
-#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_SECT		256
-#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
 #endif
 
 /* NAND flash */
@@ -156,51 +175,69 @@
 #define CONFIG_USB_ATMEL
 #define CONFIG_USB_OHCI_NEW		1
 #define CONFIG_DOS_PARTITION		1
-#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00700000	/* AT91SAM9G45_UHP_OHCI_BASE */
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9g45"
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x00700000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9g45"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE		1
 
-#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
-
-#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END			0x23e00000
-
-#ifdef CONFIG_SYS_USE_DATAFLASH
+#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
 
-/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_ENV_IS_IN_SPI_FLASH	1
-#define CONFIG_SYS_MONITOR_BASE	(0xC0000000 + 0x8400)
-#define CONFIG_ENV_OFFSET		0x4200
-#define CONFIG_ENV_ADDR		(0xC0000000 + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE		0x4200
-#define CONFIG_ENV_SECT_SIZE		0x10000
-#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
-#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
-				"root=/dev/mtdblock0 " \
-				"mtdparts=atmel_nand:-(root) "\
-				"rw rootfstype=jffs2"
-
-#else /* CONFIG_SYS_USE_NANDFLASH */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END		0x23e00000
 
 /* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_IS_IN_NAND	1
+#define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_OFFSET		0x60000
 #define CONFIG_ENV_OFFSET_REDUND	0x80000
-#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
-#define CONFIG_BOOTCOMMAND	"nand read 0x72000000 0x200000 0x200000; bootm"
-#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
-				"root=/dev/mtdblock5 " \
-				"mtdparts=atmel_nand:128k(bootstrap)ro, \
-				256k(uboot)ro,128k(env1)ro,128k(env2)ro, \
-				2M(linux),-(root) " \
-				"rw rootfstype=jffs2"
+#define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_BOOTCOMMAND	"nand read 0x70000000 0x100000 0x200000;" \
+	"bootm 0x70000000"
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 "						\
+	"root=/dev/mtdblock5 "						\
+	"mtdparts=atmel_nand:128k(bootstrap)ro,"			\
+	"256k(uboot)ro,128k(env1)ro,128k(env2)ro,"			\
+	"2M at 1M(linux),-(root) "						\
+	"rw rootfstype=jffs2"
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
 
-#endif
+/*
+ * Extra environment variables.
+ */
+#define UPDATE_BOOTSTRAP				\
+	"update_bootstrap="				\
+	"tftpboot 0x70000000 ${_bootstrap}; "		\
+	"nand erase 0x0 0x20000; "			\
+	"nand write 0x70000000 0x0 0x20000\0"
+#define UPDATE_UBOOT					\
+	"update_uboot="					\
+	"tftpboot 0x70000000 ${_uboot}; "		\
+	"nand erase 0x20000 0x40000; "			\
+	"nand write 0x70000000 0x20000 0x40000\0"
+#define UPDATE_KERNEL					\
+	"update_kernel="				\
+	"tftpboot 0x70000000 ${_kernel}; "		\
+	"nand erase 0x100000 0x200000; "		\
+	"nand write 0x70000000 0x100000 0x200000\0"
+#define UPDATE_FS					\
+	"update_fs="					\
+	"tftpboot 0x70000000 ${_rootfs}; "		\
+	"nand erase 0x300000 0xfd00000; "		\
+	"nand write 0x70000000 0x300000 ${filesize}\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS			\
+	UPDATE_BOOTSTRAP				\
+	UPDATE_UBOOT					\
+	UPDATE_KERNEL					\
+	UPDATE_FS					\
+	"_bootstrap=arm/at91bootstrap.bin\0"		\
+	"_uboot=arm/u-boot.bin\0"			\
+	"_kernel=arm/linux-kernel.bin\0"		\
+	"_rootfs=arm/atmel_fs.bin\0"
 
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
 
 #define CONFIG_SYS_PROMPT		"U-Boot> "
 #define CONFIG_SYS_CBSIZE		256
@@ -216,7 +253,8 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
+				GENERATED_GBL_DATA_SIZE)
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
 #ifdef CONFIG_USE_IRQ
-- 
1.7.4.4

[U-Boot] [PATCH 8/8] Updates the boards.cfg file

[Alex.Waterman.awaterman at dawning.com]

From: Alex Waterman <awaterman@dawning.com>

Add the default generic at91sam9m10g45ek_config target to the new
config system. Not all possible configurations of u-boot for the
at91sam9m10g45ek are included yet. Add them as needed.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
---
 boards.cfg |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/boards.cfg b/boards.cfg
index dfefc3f..470bc18 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -72,6 +72,7 @@ netstar                      arm         arm925t
 voiceblue                    arm         arm925t
 omap1510inn                  arm         arm925t     -                   ti
 aspenite                     arm         arm926ejs   -                   Marvell        armada100
+at91sam9m10g45ek             arm         arm926ejs   at91sam9m10g45ek	 atmel          at91
 afeb9260                     arm         arm926ejs   -                   -              at91
 at91cap9adk                  arm         arm926ejs   -                   atmel          at91
 at91sam9260ek_nandflash      arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH
-- 
1.7.4.4

[U-Boot] Is somebody workin on getting the AT91SAM9G45EKES working on the latest build?

[Alex Waterman]

Bill,

On 06/30/2011 02:10 PM, William C. Landolina wrote:
> Alex - If there is anything I can do to help please let me know.  I've been roughly patching the various builds for a while and really would like to see this get back in the mainline.

I will send my patch set in a few moments; just a few more things and it
should be a good start. I have a few questions...

1 What boot strapper are you using? The default at91bootstrapper that you
  can download from the linux4sam web site?

2 Are you booting from NAND?

3 How far have you gotten with your patching? Does everything work? For me, I
  have all of my hardware up and running (including the second bank of RAM
  which seemed like it was not supported before).

4 I presume your booting into Linux after U-Boot?

Best regards,
Alex

-- 
Alex Waterman
Computer Engineer
Phone: 215-896-4920
Email: awaterman at dawning.com

[U-Boot] [PATCH 0/8] Fixes compilation for the at91sam9m10g45ek

[Alex Waterman]

This patch set fixes the at91sam9mg45ek build for my set up. I have
only been able to test this patch on my own NAND booting 
at91sam9m10g45ek. Dataflash and norflash are untested. Anyway,
this is a rough approximation of a patch; I would need more input
from people with nor-flash, working at91bootstrapers, dataflash,
etc before I can get truely generic working at91sam9m10g45ek board
support.

Also, some notes:

I wrote my own boot strapper because I could not find a working
boot strapper. The boot strappers I found on the web either had their
own issues or did not enable the second bank of RAM. Thus I wrote my
own that works and enables the second bank of RAM. The patch here
expects that the second bank works. If you are using a working
at91bootstrapper or the like, I don't think that should cause this
u-boot patch to not work; just set the number of banks back to 1 in
the config file.

If I am not alone in having trouble with the existing at91bootstrap
projects, maybe we could merge my bootstrapper into (or the preexisting
at91bootstrapper proejcts) into the NAND SPL (for NAND booting boards)
section of U-Boot?

Alex Waterman (8):
  Remove old config stuff from Makefile
  Update at91sam9m10g45_devices.c to fix compile errors.
  Fix compile problem for some boards in the clock code.
  Updates the at91sam9mg45_matrix.h header to new defines.
  Updates the board specific files for the at91sam9mg45ek.
  Adds wait to atmel_usart serial_init function
  Updates the at91sam9m10g45ek.h config file.
  Updates the boards.cfg file

 Makefile                                           |   21 ---
 .../cpu/arm926ejs/at91/at91sam9m10g45_devices.c    |   26 ++--
 arch/arm/cpu/arm926ejs/at91/clock.c                |    4 +
 .../arm/include/asm/arch-at91/at91sam9g45_matrix.h |   84 +++++-----
 board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c    |  128 +++++++-------
 board/atmel/at91sam9m10g45ek/led.c                 |    6 +-
 boards.cfg                                         |    1 +
 drivers/serial/atmel_usart.c                       |    6 +
 include/configs/at91sam9m10g45ek.h                 |  188 ++++++++++++--------
 9 files changed, 246 insertions(+), 218 deletions(-)

-- 
1.7.4.4

[U-Boot] [PATCH 1/8] Remove old config stuff from Makefile

[Alex Waterman]

Start the process of pushing the at91sam9m10g45ek* boards to
the new builds.cfg configuration style. At the moment just the
generic config is available, add the rest as necessary.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
---
 Makefile |   21 ---------------------
 1 files changed, 0 insertions(+), 21 deletions(-)

diff --git a/Makefile b/Makefile
index 3454db6..63acc94 100644
--- a/Makefile
+++ b/Makefile
@@ -850,27 +850,6 @@ at91sam9rlek_config	:	unconfig
 	fi;
 	@$(MKCONFIG) -n $@ -a at91sam9rlek arm arm926ejs at91sam9rlek atmel at91
 
-at91sam9m10g45ek_nandflash_config \
-at91sam9m10g45ek_dataflash_config \
-at91sam9m10g45ek_dataflash_cs0_config \
-at91sam9m10g45ek_config \
-at91sam9g45ekes_nandflash_config \
-at91sam9g45ekes_dataflash_config \
-at91sam9g45ekes_dataflash_cs0_config \
-at91sam9g45ekes_config	:	unconfig
-	@mkdir -p $(obj)include
-		@if [ "$(findstring 9m10,$@)" ] ; then \
-		echo "#define CONFIG_AT91SAM9M10G45EK 1"	>>$(obj)include/config.h ; \
-	else \
-		echo "#define CONFIG_AT91SAM9G45EKES 1"	>>$(obj)include/config.h ; \
-	fi;
-	@if [ "$(findstring _nandflash,$@)" ] ; then \
-		echo "#define CONFIG_SYS_USE_NANDFLASH 1"	>>$(obj)include/config.h ; \
-	else \
-		echo "#define CONFIG_ATMEL_SPI 1"	>>$(obj)include/config.h ; \
-	fi;
-	@$(MKCONFIG) -n $@ -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91
-
 pm9g45_config	:	unconfig
 	@mkdir -p $(obj)include
 	@$(MKCONFIG) -a pm9g45 arm arm926ejs pm9g45 ronetix at91
-- 
1.7.4.4

[U-Boot] [PATCH 2/8] Update at91sam9m10g45_devices.c to fix compile errors.

[Alex Waterman]

Move this file to the new ATMEL_BASE_* and ATMEL_ID_* defines.

Also fixed a problem appearing in the ethernet initialization where
the entire board was being reset, not just the ethernet controller.
This at least makes ethernet work on my board if the correct
environment (mac address, ip address, etc) is available on boot.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
---
 .../cpu/arm926ejs/at91/at91sam9m10g45_devices.c    |   26 ++++++++++----------
 1 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
index 4ad9b1f..9ef8966 100644
--- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
+++ b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
@@ -26,42 +26,42 @@
 #include <asm/arch/at91_common.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+#include <asm/io.h>
 
 void at91_serial0_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTB, 19, 1);	/* TXD0 */
 	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* RXD0 */
-	writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer);
+	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
 }
 
 void at91_serial1_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD1 */
 	at91_set_a_periph(AT91_PIO_PORTB, 5, 0);		/* RXD1 */
-	writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer);
+	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
 }
 
 void at91_serial2_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTD, 6, 1);		/* TXD2 */
 	at91_set_a_periph(AT91_PIO_PORTD, 7, 0);		/* RXD2 */
-	writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer);
+	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
 }
 
 void at91_serial3_hw_init(void)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* DRXD */
 	at91_set_a_periph(AT91_PIO_PORTB, 13, 1);	/* DTXD */
-	writel(1 << AT91_ID_SYS, &pmc->pcer);
+	writel(1 << ATMEL_ID_USART3, &pmc->pcer);
 }
 
 void at91_serial_hw_init(void)
@@ -86,14 +86,14 @@ void at91_serial_hw_init(void)
 #ifdef CONFIG_ATMEL_SPI
 void at91_spi0_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* SPI0_MISO */
 	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* SPI0_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* SPI0_SPCK */
 
 	/* Enable clock */
-	writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer);
+	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTB, 3, 0);
@@ -123,14 +123,14 @@ void at91_spi0_hw_init(unsigned long cs_mask)
 
 void at91_spi1_hw_init(unsigned long cs_mask)
 {
-	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
+	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
 
 	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_MISO */
 	at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* SPI1_MOSI */
 	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* SPI1_SPCK */
 
 	/* Enable clock */
-	writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer);
+	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
 
 	if (cs_mask & (1 << 0)) {
 		at91_set_a_periph(AT91_PIO_PORTB, 17, 0);
-- 
1.7.4.4

[U-Boot] [PATCH 3/8] Fix compile problem for some boards in the clock code.

[Alex Waterman]

Some boards use AT91_SLOW_CLOCK and other use
CONFIG_SYS_AT91_SLOW_CLOCK. This patch makes it so the arm926ejs
clock code will return which ever is set.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
---
 arch/arm/cpu/arm926ejs/at91/clock.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c
index 608af2c..0083bd2 100644
--- a/arch/arm/cpu/arm926ejs/at91/clock.c
+++ b/arch/arm/cpu/arm926ejs/at91/clock.c
@@ -57,7 +57,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
 {
 	switch (css) {
 	case AT91_PMC_MCKR_CSS_SLOW:
+#ifdef AT91_SLOW_CLOCK
+		return AT91_SLOW_CLOCK;
+#else
 		return CONFIG_SYS_AT91_SLOW_CLOCK;
+#endif
 	case AT91_PMC_MCKR_CSS_MAIN:
 		return gd->main_clk_rate_hz;
 	case AT91_PMC_MCKR_CSS_PLLA:
-- 
1.7.4.4

[U-Boot] [PATCH 4/8] Updates the at91sam9mg45_matrix.h header to new defines.

[Alex Waterman]

Moves the at91sam9g45_matrix.h header file to use the new
ATMEL_BASE_MATRIX define.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
---
 .../arm/include/asm/arch-at91/at91sam9g45_matrix.h |   84 ++++++++++----------
 1 files changed, 42 insertions(+), 42 deletions(-)

diff --git a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h b/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h
index 1620e1b..9808e38 100644
--- a/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h
+++ b/arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h
@@ -15,18 +15,18 @@
 #ifndef AT91SAM9G45_MATRIX_H
 #define AT91SAM9G45_MATRIX_H
 
-#define AT91_MATRIX_MCFG0	(AT91_MATRIX + 0x00)	/* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1	(AT91_MATRIX + 0x04)	/* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2	(AT91_MATRIX + 0x08)	/* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3	(AT91_MATRIX + 0x0C)	/* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4	(AT91_MATRIX + 0x10)	/* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5	(AT91_MATRIX + 0x14)	/* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6	(AT91_MATRIX + 0x18)	/* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7	(AT91_MATRIX + 0x1C)	/* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8	(AT91_MATRIX + 0x20)	/* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9	(AT91_MATRIX + 0x24)	/* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10	(AT91_MATRIX + 0x28)	/* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11	(AT91_MATRIX + 0x2C)	/* Master Configuration Register 11 */
+#define AT91_MATRIX_MCFG0	(ATMEL_BASE_MATRIX + 0x00)	/* Master Configuration Register 0 */
+#define AT91_MATRIX_MCFG1	(ATMEL_BASE_MATRIX + 0x04)	/* Master Configuration Register 1 */
+#define AT91_MATRIX_MCFG2	(ATMEL_BASE_MATRIX + 0x08)	/* Master Configuration Register 2 */
+#define AT91_MATRIX_MCFG3	(ATMEL_BASE_MATRIX + 0x0C)	/* Master Configuration Register 3 */
+#define AT91_MATRIX_MCFG4	(ATMEL_BASE_MATRIX + 0x10)	/* Master Configuration Register 4 */
+#define AT91_MATRIX_MCFG5	(ATMEL_BASE_MATRIX + 0x14)	/* Master Configuration Register 5 */
+#define AT91_MATRIX_MCFG6	(ATMEL_BASE_MATRIX + 0x18)	/* Master Configuration Register 6 */
+#define AT91_MATRIX_MCFG7	(ATMEL_BASE_MATRIX + 0x1C)	/* Master Configuration Register 7 */
+#define AT91_MATRIX_MCFG8	(ATMEL_BASE_MATRIX + 0x20)	/* Master Configuration Register 8 */
+#define AT91_MATRIX_MCFG9	(ATMEL_BASE_MATRIX + 0x24)	/* Master Configuration Register 9 */
+#define AT91_MATRIX_MCFG10	(ATMEL_BASE_MATRIX + 0x28)	/* Master Configuration Register 10 */
+#define AT91_MATRIX_MCFG11	(ATMEL_BASE_MATRIX + 0x2C)	/* Master Configuration Register 11 */
 #define		AT91_MATRIX_ULBT	(7 << 0)	/* Undefined Length Burst Type */
 #define			AT91_MATRIX_ULBT_INFINITE	(0 << 0)
 #define			AT91_MATRIX_ULBT_SINGLE		(1 << 0)
@@ -37,14 +37,14 @@
 #define			AT91_MATRIX_ULBT_SIXTYFOUR	(6 << 0)
 #define			AT91_MATRIX_ULBT_128		(7 << 0)
 
-#define AT91_MATRIX_SCFG0	(AT91_MATRIX + 0x40)	/* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1	(AT91_MATRIX + 0x44)	/* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2	(AT91_MATRIX + 0x48)	/* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3	(AT91_MATRIX + 0x4C)	/* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4	(AT91_MATRIX + 0x50)	/* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5	(AT91_MATRIX + 0x54)	/* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6	(AT91_MATRIX + 0x58)	/* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7	(AT91_MATRIX + 0x5C)	/* Slave Configuration Register 7 */
+#define AT91_MATRIX_SCFG0	(ATMEL_BASE_MATRIX + 0x40)	/* Slave Configuration Register 0 */
+#define AT91_MATRIX_SCFG1	(ATMEL_BASE_MATRIX + 0x44)	/* Slave Configuration Register 1 */
+#define AT91_MATRIX_SCFG2	(ATMEL_BASE_MATRIX + 0x48)	/* Slave Configuration Register 2 */
+#define AT91_MATRIX_SCFG3	(ATMEL_BASE_MATRIX + 0x4C)	/* Slave Configuration Register 3 */
+#define AT91_MATRIX_SCFG4	(ATMEL_BASE_MATRIX + 0x50)	/* Slave Configuration Register 4 */
+#define AT91_MATRIX_SCFG5	(ATMEL_BASE_MATRIX + 0x54)	/* Slave Configuration Register 5 */
+#define AT91_MATRIX_SCFG6	(ATMEL_BASE_MATRIX + 0x58)	/* Slave Configuration Register 6 */
+#define AT91_MATRIX_SCFG7	(ATMEL_BASE_MATRIX + 0x5C)	/* Slave Configuration Register 7 */
 #define		AT91_MATRIX_SLOT_CYCLE		(0x1ff << 0)	/* Maximum Number of Allowed Cycles for a Burst */
 #define		AT91_MATRIX_DEFMSTR_TYPE	(3    << 16)	/* Default Master Type */
 #define			AT91_MATRIX_DEFMSTR_TYPE_NONE	(0 << 16)
@@ -52,22 +52,22 @@
 #define			AT91_MATRIX_DEFMSTR_TYPE_FIXED	(2 << 16)
 #define		AT91_MATRIX_FIXED_DEFMSTR	(0xf  << 18)	/* Fixed Index of Default Master */
 
-#define AT91_MATRIX_PRAS0	(AT91_MATRIX + 0x80)	/* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0	(AT91_MATRIX + 0x84)	/* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1	(AT91_MATRIX + 0x88)	/* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1	(AT91_MATRIX + 0x8C)	/* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2	(AT91_MATRIX + 0x90)	/* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2	(AT91_MATRIX + 0x94)	/* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3	(AT91_MATRIX + 0x98)	/* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3	(AT91_MATRIX + 0x9C)	/* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4	(AT91_MATRIX + 0xA0)	/* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4	(AT91_MATRIX + 0xA4)	/* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5	(AT91_MATRIX + 0xA8)	/* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5	(AT91_MATRIX + 0xAC)	/* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6	(AT91_MATRIX + 0xB0)	/* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6	(AT91_MATRIX + 0xB4)	/* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7	(AT91_MATRIX + 0xB8)	/* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7	(AT91_MATRIX + 0xBC)	/* Priority Register B for Slave 7 */
+#define AT91_MATRIX_PRAS0	(ATMEL_BASE_MATRIX + 0x80)	/* Priority Register A for Slave 0 */
+#define AT91_MATRIX_PRBS0	(ATMEL_BASE_MATRIX + 0x84)	/* Priority Register B for Slave 0 */
+#define AT91_MATRIX_PRAS1	(ATMEL_BASE_MATRIX + 0x88)	/* Priority Register A for Slave 1 */
+#define AT91_MATRIX_PRBS1	(ATMEL_BASE_MATRIX + 0x8C)	/* Priority Register B for Slave 1 */
+#define AT91_MATRIX_PRAS2	(ATMEL_BASE_MATRIX + 0x90)	/* Priority Register A for Slave 2 */
+#define AT91_MATRIX_PRBS2	(ATMEL_BASE_MATRIX + 0x94)	/* Priority Register B for Slave 2 */
+#define AT91_MATRIX_PRAS3	(ATMEL_BASE_MATRIX + 0x98)	/* Priority Register A for Slave 3 */
+#define AT91_MATRIX_PRBS3	(ATMEL_BASE_MATRIX + 0x9C)	/* Priority Register B for Slave 3 */
+#define AT91_MATRIX_PRAS4	(ATMEL_BASE_MATRIX + 0xA0)	/* Priority Register A for Slave 4 */
+#define AT91_MATRIX_PRBS4	(ATMEL_BASE_MATRIX + 0xA4)	/* Priority Register B for Slave 4 */
+#define AT91_MATRIX_PRAS5	(ATMEL_BASE_MATRIX + 0xA8)	/* Priority Register A for Slave 5 */
+#define AT91_MATRIX_PRBS5	(ATMEL_BASE_MATRIX + 0xAC)	/* Priority Register B for Slave 5 */
+#define AT91_MATRIX_PRAS6	(ATMEL_BASE_MATRIX + 0xB0)	/* Priority Register A for Slave 6 */
+#define AT91_MATRIX_PRBS6	(ATMEL_BASE_MATRIX + 0xB4)	/* Priority Register B for Slave 6 */
+#define AT91_MATRIX_PRAS7	(ATMEL_BASE_MATRIX + 0xB8)	/* Priority Register A for Slave 7 */
+#define AT91_MATRIX_PRBS7	(ATMEL_BASE_MATRIX + 0xBC)	/* Priority Register B for Slave 7 */
 #define		AT91_MATRIX_M0PR		(3 << 0)	/* Master 0 Priority */
 #define		AT91_MATRIX_M1PR		(3 << 4)	/* Master 1 Priority */
 #define		AT91_MATRIX_M2PR		(3 << 8)	/* Master 2 Priority */
@@ -81,7 +81,7 @@
 #define		AT91_MATRIX_M10PR		(3 << 8)	/* Master 10 Priority (in Register B) */
 #define		AT91_MATRIX_M11PR		(3 << 12)	/* Master 11 Priority (in Register B) */
 
-#define AT91_MATRIX_MRCR	(AT91_MATRIX + 0x100)	/* Master Remap Control Register */
+#define AT91_MATRIX_MRCR	(ATMEL_BASE_MATRIX + 0x100)	/* Master Remap Control Register */
 #define		AT91_MATRIX_RCB0		(1 << 0)	/* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
 #define		AT91_MATRIX_RCB1		(1 << 1)	/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
 #define		AT91_MATRIX_RCB2		(1 << 2)
@@ -95,7 +95,7 @@
 #define		AT91_MATRIX_RCB10		(1 << 10)
 #define		AT91_MATRIX_RCB11		(1 << 11)
 
-#define AT91_MATRIX_TCMR	(AT91_MATRIX + 0x110)	/* TCM Configuration Register */
+#define AT91_MATRIX_TCMR	(ATMEL_BASE_MATRIX + 0x110)	/* TCM Configuration Register */
 #define		AT91_MATRIX_ITCM_SIZE		(0xf << 0)	/* Size of ITCM enabled memory block */
 #define			AT91_MATRIX_ITCM_0		(0 << 0)
 #define			AT91_MATRIX_ITCM_32		(6 << 0)
@@ -107,12 +107,12 @@
 #define			AT91_MATRIX_TCM_NO_WS		(0x0 << 11)
 #define			AT91_MATRIX_TCM_ONE_WS		(0x1 << 11)
 
-#define AT91_MATRIX_VIDEO	(AT91_MATRIX + 0x118)	/* Video Mode Configuration Register */
+#define AT91_MATRIX_VIDEO	(ATMEL_BASE_MATRIX + 0x118)	/* Video Mode Configuration Register */
 #define		AT91C_VDEC_SEL			(0x1 <<  0) /* Video Mode Selection */
 #define			AT91C_VDEC_SEL_OFF		(0 << 0)
 #define			AT91C_VDEC_SEL_ON		(1 << 0)
 
-#define AT91_MATRIX_EBICSA	(AT91_MATRIX + 0x128)	/* EBI Chip Select Assignment Register */
+#define AT91_MATRIX_EBICSA	(ATMEL_BASE_MATRIX + 0x128)	/* EBI Chip Select Assignment Register */
 #define		AT91_MATRIX_EBI_CS1A		(1 << 1)	/* Chip Select 1 Assignment */
 #define			AT91_MATRIX_EBI_CS1A_SMC		(0 << 1)
 #define			AT91_MATRIX_EBI_CS1A_SDRAMC		(1 << 1)
@@ -138,13 +138,13 @@
 #define			AT91_MATRIX_EBI_DDR_IOSR_REDUCED	(0 << 18)
 #define			AT91_MATRIX_EBI_DDR_IOSR_NORMAL		(1 << 18)
 
-#define AT91_MATRIX_WPMR	(AT91_MATRIX + 0x1E4)	/* Write Protect Mode Register */
+#define AT91_MATRIX_WPMR	(ATMEL_BASE_MATRIX + 0x1E4)	/* Write Protect Mode Register */
 #define		AT91_MATRIX_WPMR_WPEN		(1 << 0)	/* Write Protect ENable */
 #define			AT91_MATRIX_WPMR_WP_WPDIS		(0 << 0)
 #define			AT91_MATRIX_WPMR_WP_WPEN		(1 << 0)
 #define		AT91_MATRIX_WPMR_WPKEY		(0xFFFFFF << 8)	/* Write Protect KEY */
 
-#define AT91_MATRIX_WPSR	(AT91_MATRIX + 0x1E8)	/* Write Protect Status Register */
+#define AT91_MATRIX_WPSR	(ATMEL_BASE_MATRIX + 0x1E8)	/* Write Protect Status Register */
 #define		AT91_MATRIX_WPSR_WPVS		(1 << 0)	/* Write Protect Violation Status */
 #define			AT91_MATRIX_WPSR_NO_WPV		(0 << 0)
 #define			AT91_MATRIX_WPSR_WPV		(1 << 0)
-- 
1.7.4.4

[U-Boot] [PATCH 5/8] Updates the board specific files for the at91sam9mg45ek.

[Alex Waterman]

Fixes the compile errors in the board specific initializations for
the at91sam9m10g45ek specific files.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
---
 board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c |  128 +++++++++++------------
 board/atmel/at91sam9m10g45ek/led.c              |    6 +-
 2 files changed, 67 insertions(+), 67 deletions(-)

diff --git a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
index f92b20f..f8e687e 100644
--- a/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
+++ b/board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
@@ -23,6 +23,7 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/sizes.h>
 #include <asm/arch/at91sam9g45.h>
 #include <asm/arch/at91sam9_matrix.h>
@@ -32,7 +33,6 @@
 #include <asm/arch/at91_rstc.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
 #include <asm/arch/hardware.h>
 #include <lcd.h>
 #include <atmel_lcdc.h>
@@ -41,6 +41,14 @@
 #endif
 #include <netdev.h>
 
+/*
+ * arch/arm/include/asm/arch-at91/at91sam9g45.h defines ATMEL_BASE_SCM;
+ * however, other code still wants AT91_SMC instead. Likewise for the AT91_PMC
+ * definition.
+ */
+#define AT91_SMC		ATMEL_BASE_SMC
+#define AT91_PMC		ATMEL_BASE_PMC
+
 DECLARE_GLOBAL_DATA_PTR;
 
 /* ------------------------------------------------------------------------- */
@@ -49,35 +57,35 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 
 #ifdef CONFIG_CMD_NAND
-static void at91sam9m10g45ek_nand_hw_init(void)
+void at91sam9m10g45ek_nand_hw_init(void)
 {
 	unsigned long csa;
 
 	/* Enable CS3 */
-	csa = at91_sys_read(AT91_MATRIX_EBICSA);
-	at91_sys_write(AT91_MATRIX_EBICSA,
-		       csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+	csa = readl(AT91_MATRIX_EBICSA);
+	writel(csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA, AT91_MATRIX_EBICSA);
 
 	/* Configure SMC CS3 for NAND/SmartMedia */
-	at91_sys_write(AT91_SMC_SETUP(3),
-		       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
-		       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
-	at91_sys_write(AT91_SMC_PULSE(3),
-		       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
-		       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2));
-	at91_sys_write(AT91_SMC_CYCLE(3),
-		       AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4));
-	at91_sys_write(AT91_SMC_MODE(3),
-		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
-		       AT91_SMC_EXNWMODE_DISABLE |
+	writel(AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+	       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0),
+	       AT91_SMC_SETUP(3));
+	writel(AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(3) |
+	       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(2),
+	       AT91_SMC_PULSE(3));
+
+	writel(AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(4),
+	       AT91_SMC_CYCLE(3));
+	writel(AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+	       AT91_SMC_EXNWMODE_DISABLE |
 #ifdef CONFIG_SYS_NAND_DBW_16
 		       AT91_SMC_DBW_16 |
 #else /* CONFIG_SYS_NAND_DBW_8 */
 		       AT91_SMC_DBW_8 |
 #endif
-		       AT91_SMC_TDF_(3));
+	       AT91_SMC_TDF_(3),
+	       AT91_SMC_MODE(3));
 
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIOC);
+	writel(1 << ATMEL_ID_PIOC, AT91_PMC_PCER);
 
 	/* Configure RDY/BSY */
 	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
@@ -90,7 +98,7 @@ static void at91sam9m10g45ek_nand_hw_init(void)
 #ifdef CONFIG_CMD_USB
 static void at91sam9m10g45ek_usb_hw_init(void)
 {
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE);
+	writel(1 << ATMEL_ID_PIODE, AT91_PMC_PCER);
 
 	at91_set_gpio_output(AT91_PIN_PD1, 0);
 	at91_set_gpio_output(AT91_PIN_PD3, 0);
@@ -100,48 +108,13 @@ static void at91sam9m10g45ek_usb_hw_init(void)
 #ifdef CONFIG_MACB
 static void at91sam9m10g45ek_macb_hw_init(void)
 {
-	unsigned long rstc;
 
 	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_EMAC);
-
-	/*
-	 * Disable pull-up on:
-	 *	RXDV (PA15) => PHY normal mode (not Test mode)
-	 * 	ERX0 (PA12) => PHY ADDR0
-	 *	ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
-	 *
-	 * PHY has internal pull-down
-	 */
-	writel(pin_to_mask(AT91_PIN_PA15) |
-	       pin_to_mask(AT91_PIN_PA12) |
-	       pin_to_mask(AT91_PIN_PA13),
-	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
-
-	rstc = at91_sys_read(AT91_RSTC_MR);
-
-	/* Need to reset PHY -> 500ms reset */
-	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     (AT91_RSTC_ERSTL & (0x0D << 8)) |
-				     AT91_RSTC_URSTEN);
-
-	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
-
-	/* Wait for end hardware reset */
-	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
-
-	/* Restore NRST value */
-	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
-				     (rstc) |
-				     AT91_RSTC_URSTEN);
-
-	/* Re-enable pull-up */
-	writel(pin_to_mask(AT91_PIN_PA15) |
-	       pin_to_mask(AT91_PIN_PA12) |
-	       pin_to_mask(AT91_PIN_PA13),
-	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
+	writel(1 << ATMEL_ID_EMAC, AT91_PMC_PCER);
 
+	/* And the pins. */
 	at91_macb_hw_init();
+
 }
 #endif
 
@@ -161,7 +134,7 @@ vidinfo_t panel_info = {
 	vl_vsync_len:	1,
 	vl_upper_margin:40,
 	vl_lower_margin:1,
-	mmio:		AT91SAM9G45_LCDC_BASE,
+	mmio :		 ATMEL_BASE_LCDC,
 };
 
 
@@ -208,7 +181,7 @@ static void at91sam9m10g45ek_lcd_hw_init(void)
 	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
 	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */
 
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_LCDC);
+	writel(1 << ATMEL_ID_LCDC, AT91_PMC_PCER);
 
 	gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
 }
@@ -227,7 +200,7 @@ void lcd_show_board_info(void)
 	lcd_printf ("(C) 2008 ATMEL Corp\n");
 	lcd_printf ("at91support at atmel.com\n");
 	lcd_printf ("%s CPU at %s MHz\n",
-		CONFIG_SYS_AT91_CPU_NAME,
+		ATMEL_CPU_NAME,
 		strmhz(temp, get_cpu_clk_rate()));
 
 	dram_size = 0;
@@ -257,7 +230,8 @@ int board_init(void)
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
-	at91_serial_hw_init();
+
+
 #ifdef CONFIG_CMD_NAND
 	at91sam9m10g45ek_nand_hw_init();
 #endif
@@ -270,11 +244,9 @@ int board_init(void)
 #ifdef CONFIG_ATMEL_SPI
 	at91_spi0_hw_init(1 << 4);
 #endif
-
 #ifdef CONFIG_MACB
 	at91sam9m10g45ek_macb_hw_init();
 #endif
-
 #ifdef CONFIG_LCD
 	at91sam9m10g45ek_lcd_hw_init();
 #endif
@@ -283,9 +255,23 @@ int board_init(void)
 
 int dram_init(void)
 {
+	gd->ram_size = PHYS_SDRAM_SIZE;
+	return 0;
+}
+
+void dram_init_banksize()
+{
+
+	/* Bank 1. */
 	gd->bd->bi_dram[0].start = PHYS_SDRAM;
 	gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
-	return 0;
+
+	/* Bank 2. */
+#if (CONFIG_NR_DRAM_BANKS == 2)
+	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+	gd->bd->bi_dram[1].size = PHYS_SDRAM_SIZE_2;
+#endif
+
 }
 
 #ifdef CONFIG_RESET_PHY_R
@@ -298,7 +284,7 @@ int board_eth_init(bd_t *bis)
 {
 	int rc = 0;
 #ifdef CONFIG_MACB
-	rc = macb_eth_initialize(0, (void *)AT91SAM9G45_BASE_EMAC, 0x00);
+	rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
 #endif
 	return rc;
 }
@@ -338,3 +324,15 @@ void spi_cs_deactivate(struct spi_slave *slave)
 	}
 }
 #endif /* CONFIG_ATMEL_SPI */
+
+extern void at91_serial_hw_init(void);
+/*
+ * (re)Initialize the serial hardware.
+ */
+int board_early_init_f(void)
+{
+
+	at91_serial_hw_init();
+	return 0;
+
+}
diff --git a/board/atmel/at91sam9m10g45ek/led.c b/board/atmel/at91sam9m10g45ek/led.c
index ff59a2d..b939c5b 100644
--- a/board/atmel/at91sam9m10g45ek/led.c
+++ b/board/atmel/at91sam9m10g45ek/led.c
@@ -23,15 +23,17 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/at91sam9g45.h>
 #include <asm/arch/at91_pmc.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/io.h>
+
+#define AT91_PMC		ATMEL_BASE_PMC
 
 void coloured_LED_init(void)
 {
 	/* Enable clock */
-	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_PIODE);
+	writel(AT91_PMC_PCER, 1 << ATMEL_ID_PIODE);
 
 	at91_set_gpio_output(CONFIG_RED_LED, 1);
 	at91_set_gpio_output(CONFIG_GREEN_LED, 1);
-- 
1.7.4.4

[U-Boot] [PATCH 6/8] Adds wait to atmel_usart serial_init function

[Alex Waterman]

Adds a short busy loop wait to the atmel_usart.c serial_init()
function.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
---
 drivers/serial/atmel_usart.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
index e326b2b..e355706 100644
--- a/drivers/serial/atmel_usart.c
+++ b/drivers/serial/atmel_usart.c
@@ -47,6 +47,8 @@ void serial_setbrg(void)
 
 int serial_init(void)
 {
+
+	volatile int i = 0;
 	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
 
 	writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
@@ -61,6 +63,10 @@ int serial_init(void)
 			   | USART3_BF(NBSTOP, USART3_NBSTOP_1)),
 			   &usart->mr);
 
+	/* Short wait to let the serial port init. */
+	for (; i < 10000; i++)
+		;
+
 	return 0;
 }
 
-- 
1.7.4.4

[U-Boot] [PATCH 7/8] Updates the at91sam9m10g45ek.h config file.

[Alex Waterman]

Moves to using newer defines and adds possible support for the
second bank of RAM (if so desired).

Also, some coding clean up: removed the needless define to 1s for
defines that just act as flags.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
---
 include/configs/at91sam9m10g45ek.h |  188 +++++++++++++++++++++--------------
 1 files changed, 113 insertions(+), 75 deletions(-)

diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
index de74dcf..5e02dde 100644
--- a/include/configs/at91sam9m10g45ek.h
+++ b/include/configs/at91sam9m10g45ek.h
@@ -27,48 +27,65 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+/*#define DEBUG*/
+
 #define CONFIG_AT91_LEGACY
+#define CONFIG_ATMEL_LEGACY
 
 /* ARM asynchronous clock */
-#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* from 12 MHz crystal */
+#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000 /* from 12 MHz crystal */
+#define AT91_SLOW_CLOCK		32768
 #define CONFIG_SYS_HZ		1000
 
-#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
-#ifdef CONFIG_AT91SAM9M10G45EK
-#define CONFIG_AT91SAM9M10G45	1	/* It's an Atmel AT91SAM9M10G45 SoC*/
-#else
-#define CONFIG_AT91SAM9G45	1	/* It's an Atmel AT91SAM9G45 SoC*/
-#endif
+#define CONFIG_AT91SAM9M10G45
+#define CONFIG_AT91FAMILY
 #define CONFIG_ARCH_CPU_INIT
+#define CONFIG_BOARD_EARLY_INIT_F
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
 
-#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
-#define CONFIG_SETUP_MEMORY_TAGS 1
-#define CONFIG_INITRD_TAG	1
+#define CONFIGMDLINE_TAG		/* enable passing of ATAGs	*/
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
+#define ATMEL_PIO_PORTS		5 /* 5 PIO ports. */
+#define CONFIG_SYS_SDRAM_BASE   0x70000000
+
 /*
  * Hardware drivers
  */
-#define CONFIG_AT91_GPIO	1
-#define CONFIG_ATMEL_USART	1
+#define CONFIG_AT91_GPIO
+#define CONFIG_ATMEL_USART
 #undef CONFIG_USART0
 #undef CONFIG_USART1
 #undef CONFIG_USART2
-#define CONFIG_USART3		1	/* USART 3 is DBGU */
+#define CONFIG_USART3		/* USART 3 is DBGU */
+#define CONFIG_USART_BASE	0xffffee00 /* Use the DBGU hardware. */
+#define CONFIG_USART_ID		10
+
+/*
+ * This needs to be defined for the OHCI code to work but it is defined as
+ * ATMEL_ID_UHPHS in the CPU specific header files.
+ */
+#define ATMEL_ID_UHP		ATMEL_ID_UHPHS
+
+/*
+ * Specify the clock enable bit in the PMC_SCER register.
+ */
+#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
 
 /* LCD */
-#define CONFIG_LCD			1
+#define CONFIG_LCD
 #define LCD_BPP				LCD_COLOR8
-#define CONFIG_LCD_LOGO			1
+#define CONFIG_LCD_LOGO
 #undef LCD_TEST_PATTERN
-#define CONFIG_LCD_INFO			1
-#define CONFIG_LCD_INFO_BELOW_LOGO	1
-#define CONFIG_SYS_WHITE_ON_BLACK		1
-#define CONFIG_ATMEL_LCD		1
-#define CONFIG_ATMEL_LCD_RGB565		1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
+#define CONFIG_LCD_INFO
+#define CONFIG_LCD_INFO_BELOW_LOGO
+#define CONFIG_SYS_WHITE_ON_BLACK
+#define CONFIG_ATMEL_LCD
+#define CONFIG_ATMEL_LCD_RGB565
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
 /* board specific(not enough SRAM) */
 #define CONFIG_AT91SAM9G45_LCD_BASE		0x73E00000
 
@@ -82,10 +99,10 @@
 /*
  * BOOTP options
  */
-#define CONFIG_BOOTP_BOOTFILESIZE	1
-#define CONFIG_BOOTP_BOOTPATH		1
-#define CONFIG_BOOTP_GATEWAY		1
-#define CONFIG_BOOTP_HOSTNAME		1
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
 
 /*
  * Command line configuration.
@@ -98,35 +115,37 @@
 #undef CONFIG_CMD_AUTOSCRIPT
 #undef CONFIG_CMD_LOADS
 
-#define CONFIG_CMD_PING		1
-#define CONFIG_CMD_DHCP		1
-#define CONFIG_CMD_NAND		1
-#define CONFIG_CMD_USB		1
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_USB
 
 /* SDRAM */
-#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_NR_DRAM_BANKS		2
 #define PHYS_SDRAM			0x70000000
 #define PHYS_SDRAM_SIZE			0x08000000	/* 128 megs */
+#define PHYS_SDRAM_2			0x20000000
+#define PHYS_SDRAM_SIZE_2		0x08000000	/* 128 megs */
 
 /* DataFlash */
 #ifdef CONFIG_ATMEL_SPI
 #define CONFIG_CMD_SF
 #define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH		1
-#define CONFIG_SPI_FLASH_ATMEL		1
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_ATMEL
 #define CONFIG_SYS_MAX_DATAFLASH_BANKS	1
 #endif
 
 /* NOR flash, if populated */
-#ifndef CONFIG_CMD_NAND
-#define CONFIG_SYS_NO_FLASH		1
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_SYS_NO_FLASH
 #else
-#define CONFIG_SYS_FLASH_CFI		1
-#define CONFIG_FLASH_CFI_DRIVER		1
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
 #define PHYS_FLASH_1			0x10000000
-#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
-#define CONFIG_SYS_MAX_FLASH_SECT		256
-#define CONFIG_SYS_MAX_FLASH_BANKS		1
+#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
+#define CONFIG_SYS_MAX_FLASH_SECT	256
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
 #endif
 
 /* NAND flash */
@@ -156,51 +175,69 @@
 #define CONFIG_USB_ATMEL
 #define CONFIG_USB_OHCI_NEW		1
 #define CONFIG_DOS_PARTITION		1
-#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
-#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00700000	/* AT91SAM9G45_UHP_OHCI_BASE */
-#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9g45"
+#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x00700000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9g45"
 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
 #define CONFIG_USB_STORAGE		1
 
-#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
-
-#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
-#define CONFIG_SYS_MEMTEST_END			0x23e00000
-
-#ifdef CONFIG_SYS_USE_DATAFLASH
+#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
 
-/* bootstrap + u-boot + env + linux in dataflash on CS0 */
-#define CONFIG_ENV_IS_IN_SPI_FLASH	1
-#define CONFIG_SYS_MONITOR_BASE	(0xC0000000 + 0x8400)
-#define CONFIG_ENV_OFFSET		0x4200
-#define CONFIG_ENV_ADDR		(0xC0000000 + CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_SIZE		0x4200
-#define CONFIG_ENV_SECT_SIZE		0x10000
-#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
-#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
-				"root=/dev/mtdblock0 " \
-				"mtdparts=atmel_nand:-(root) "\
-				"rw rootfstype=jffs2"
-
-#else /* CONFIG_SYS_USE_NANDFLASH */
+#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END		0x23e00000
 
 /* bootstrap + u-boot + env + linux in nandflash */
-#define CONFIG_ENV_IS_IN_NAND	1
+#define CONFIG_ENV_IS_IN_NAND
 #define CONFIG_ENV_OFFSET		0x60000
 #define CONFIG_ENV_OFFSET_REDUND	0x80000
-#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
-#define CONFIG_BOOTCOMMAND	"nand read 0x72000000 0x200000 0x200000; bootm"
-#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
-				"root=/dev/mtdblock5 " \
-				"mtdparts=atmel_nand:128k(bootstrap)ro, \
-				256k(uboot)ro,128k(env1)ro,128k(env2)ro, \
-				2M(linux),-(root) " \
-				"rw rootfstype=jffs2"
+#define CONFIG_ENV_SIZE			0x20000
+#define CONFIG_BOOTCOMMAND	"nand read 0x70000000 0x100000 0x200000;" \
+	"bootm 0x70000000"
+#define CONFIG_BOOTARGS							\
+	"console=ttyS0,115200 "						\
+	"root=/dev/mtdblock5 "						\
+	"mtdparts=atmel_nand:128k(bootstrap)ro,"			\
+	"256k(uboot)ro,128k(env1)ro,128k(env2)ro,"			\
+	"2M at 1M(linux),-(root) "						\
+	"rw rootfstype=jffs2"
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
 
-#endif
+/*
+ * Extra environment variables.
+ */
+#define UPDATE_BOOTSTRAP				\
+	"update_bootstrap="				\
+	"tftpboot 0x70000000 ${_bootstrap}; "		\
+	"nand erase 0x0 0x20000; "			\
+	"nand write 0x70000000 0x0 0x20000\0"
+#define UPDATE_UBOOT					\
+	"update_uboot="					\
+	"tftpboot 0x70000000 ${_uboot}; "		\
+	"nand erase 0x20000 0x40000; "			\
+	"nand write 0x70000000 0x20000 0x40000\0"
+#define UPDATE_KERNEL					\
+	"update_kernel="				\
+	"tftpboot 0x70000000 ${_kernel}; "		\
+	"nand erase 0x100000 0x200000; "		\
+	"nand write 0x70000000 0x100000 0x200000\0"
+#define UPDATE_FS					\
+	"update_fs="					\
+	"tftpboot 0x70000000 ${_rootfs}; "		\
+	"nand erase 0x300000 0xfd00000; "		\
+	"nand write 0x70000000 0x300000 ${filesize}\0"
+
+#define CONFIG_EXTRA_ENV_SETTINGS			\
+	UPDATE_BOOTSTRAP				\
+	UPDATE_UBOOT					\
+	UPDATE_KERNEL					\
+	UPDATE_FS					\
+	"_bootstrap=arm/at91bootstrap.bin\0"		\
+	"_uboot=arm/u-boot.bin\0"			\
+	"_kernel=arm/linux-kernel.bin\0"		\
+	"_rootfs=arm/atmel_fs.bin\0"
 
-#define CONFIG_BAUDRATE		115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
 
 #define CONFIG_SYS_PROMPT		"U-Boot> "
 #define CONFIG_SYS_CBSIZE		256
@@ -216,7 +253,8 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
-
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
+				GENERATED_GBL_DATA_SIZE)
 #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
 
 #ifdef CONFIG_USE_IRQ
-- 
1.7.4.4

[U-Boot] [PATCH 8/8] Updates the boards.cfg file

[Alex Waterman]

Add the default generic at91sam9m10g45ek_config target to the new
config system. Not all possible configurations of u-boot for the
at91sam9m10g45ek are included yet. Add them as needed.

Signed-off-by: Alex Waterman <awaterman@dawning.com>
---
 boards.cfg |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/boards.cfg b/boards.cfg
index dfefc3f..470bc18 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -72,6 +72,7 @@ netstar                      arm         arm925t
 voiceblue                    arm         arm925t
 omap1510inn                  arm         arm925t     -                   ti
 aspenite                     arm         arm926ejs   -                   Marvell        armada100
+at91sam9m10g45ek             arm         arm926ejs   at91sam9m10g45ek	 atmel          at91
 afeb9260                     arm         arm926ejs   -                   -              at91
 at91cap9adk                  arm         arm926ejs   -                   atmel          at91
 at91sam9260ek_nandflash      arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH
-- 
1.7.4.4

[U-Boot] Is somebody workin on getting the AT91SAM9G45EKES working on the latest build?

[Alex Waterman]

Albert,

On 06/30/2011 09:12 AM, Albert ARIBAUD wrote:
> In this case please first, make sure it does apply cleanly, and second, add the board maintainer and the Atmel custodian as Cc: when you post it.

I sent my patch to the u-boot mailing list and the patch appears in patchwork but
it has yet to actually get to the mailing list. Is a delay normal or should I try
and email it again or something else entirely?

Best regards,
Alex

-- 
Alex Waterman
Computer Engineer
Phone: 215-896-4920
Email: awaterman at dawning.com

[U-Boot] Is somebody workin on getting the AT91SAM9G45EKES working on the latest build?

[William C. Landolina]

> Bill,
> 
> On 06/30/2011 02:10 PM, William C. Landolina wrote:
> > Alex - If there is anything I can do to help please let me know.  I've been
> roughly patching the various builds for a while and really would like to see
> this get back in the mainline.
> 
> I will send my patch set in a few moments; just a few more things and it
> should be a good start. I have a few questions...
> 
> 1 What boot strapper are you using? The default at91bootstrapper that you
>   can download from the linux4sam web site?

I start with Atmel's vanilla first stage boot from NAND.  I have a much hacked SDCard boot that works as well and that is where I want to head.  My target systems do not have NAND or Dataflash.  (I can put NAND on my boards for development but I do not want to ship with NAND.)

> 2 Are you booting from NAND?

I currently boot from NAND - the features I want to get from the current version is booting from, and environment on, SDCard.  I hacked that into the December release but it was a hack - the environment was at fixed sector offsets on the SDCard which required building the partition table by hand.  Long term I want to get the environment in a file on the SDCard.

> 3 How far have you gotten with your patching? Does everything work? For
> me, I
>   have all of my hardware up and running (including the second bank of RAM
>   which seemed like it was not supported before).

I hacked the December release to work, but I know I did some things in the wrong places and in a style that is not Wolfgang-compatible.  I stopped working on improving the December release because it was clear that a lot of good things were happening to the MMC framework and the underlying AT91 framework was in flux so it seemed like a good idea to wait until that stabilized before I revisit putting a modern U-Boot on my boards "the right way".

I only have one bank of RAM on my custom target so I didn't test the second bank.  On my targets the other EBI interface runs a bunch of slow peripherals.

> 4 I presume your booting into Linux after U-Boot?

Yes, I'm booting Linux 2.6.30 or so. 

> Best regards,
> Alex
> 
> --
> Alex Waterman
> Computer Engineer
> Phone: 215-896-4920
> Email: awaterman at dawning.com

Enjoy,
Bill.

[U-Boot] [PATCH 6/8] Adds wait to atmel_usart serial_init function

[Sergei Shtylyov]

Hello.

On 30-06-2011 23:33, Alex Waterman wrote:

> Adds a short busy loop wait to the atmel_usart.c serial_init()
> function.

> Signed-off-by: Alex Waterman<awaterman@dawning.com>

> diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
> index e326b2b..e355706 100644
> --- a/drivers/serial/atmel_usart.c
> +++ b/drivers/serial/atmel_usart.c
> @@ -47,6 +47,8 @@ void serial_setbrg(void)
>
>   int serial_init(void)
>   {
> +
> +	volatile int i = 0;

    Why 'volatile'? Also, there shouldn't be an empty line before it but there 
should be one after it...

>   	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
>
>   	writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX),&usart->cr);
> @@ -61,6 +63,10 @@ int serial_init(void)
>   			   | USART3_BF(NBSTOP, USART3_NBSTOP_1)),
>   			&usart->mr);
>
> +	/* Short wait to let the serial port init. */
> +	for (; i < 10000; i++)
> +		;
> +
>   	return 0;
>   }

WBR, Sergei

[U-Boot] [PATCH 6/8] Adds wait to atmel_usart serial_init function

[Alex Waterman]

>    Why 'volatile'? Also, there shouldn't be an empty line before it but there should be one after it...
I used a volatile to prevent the compiler from optimizing out the (normally) useless loop. Is there a cleaner way to do this?

Best regards,
Alex

-- 
Alex Waterman
Computer Engineer
Phone: 215-896-4920
Email: awaterman at dawning.com

[U-Boot] Is somebody workin on getting the AT91SAM9G45EKES working on the latest build?

[Alex Waterman]

Bill,

On 06/30/2011 04:54 PM, William C. Landolina wrote:
> I start with Atmel's vanilla first stage boot from NAND.  I have a much hacked SDCard boot that works as well and that is where I want to head.  My target systems do not have NAND or Dataflash.  (I can put NAND on my boards for development but I do not want to ship with NAND.)
I see. I have not tried any of the MMC u-boot stuff for my board (a 
sam9m10g45ek).

> I hacked the December release to work, but I know I did some things in the wrong places and in a style that is not Wolfgang-compatible.  I stopped working on improving the December release because it was clear that a lot of good things were happening to the MMC framework and the underlying AT91 framework was in flux so it seemed like a good idea to wait until that stabilized before I revisit putting a modern U-Boot on my boards "the right way".
Ahh, Wolfgang compatible :). I still haven't really figured out exactly what is
actually correct with the AT91 framework code yet. I just started playing with
this a few weeks ago. There was a patch a little which back which was the
reference implementation for the AT91 framework, but I could not find it when I
searched my mail box. 

> I only have one bank of RAM on my custom target so I didn't test the second bank.  On my targets the other EBI interface runs a bunch of slow peripherals.
Ah, so dual RAM is no matter for you.

Which config header are you using? Naturally, I am using the sam9m10g45ek
header, but since you have a slightly different board, which doesn't
appear to have a header, how did you proceed?

Best regards,
Alex

-- 
Alex Waterman
Computer Engineer
Phone: 215-896-4920
Email: awaterman at dawning.com

[U-Boot] [PATCH 6/8] Adds wait to atmel_usart serial_init function

[Albert ARIBAUD]

Hi Alex,

Le 01/07/2011 14:37, Alex Waterman a ?crit :
>
>>     Why 'volatile'? Also, there shouldn't be an empty line before it but there should be one after it...
> I used a volatile to prevent the compiler from optimizing out the (normally) useless loop. Is there a cleaner way to do this?

If the board supports udelay(), you should use that instead of a loop.

> Best regards,
> Alex

Amicalement,
-- 
Albert.

[U-Boot] Is somebody workin on getting the AT91SAM9G45EKES working on the latest build?

[William C. Landolina]

> Bill,
> 
> On 06/30/2011 04:54 PM, William C. Landolina wrote:
> > I start with Atmel's vanilla first stage boot from NAND.  I have a
> > much hacked SDCard boot that works as well and that is where I want to
> > head.  My target systems do not have NAND or Dataflash.  (I can put
> > NAND on my boards for development but I do not want to ship with
> > NAND.)
> I see. I have not tried any of the MMC u-boot stuff for my board (a
> sam9m10g45ek).
> 
> > I hacked the December release to work, but I know I did some things in the
> wrong places and in a style that is not Wolfgang-compatible.  I stopped
> working on improving the December release because it was clear that a lot of
> good things were happening to the MMC framework and the underlying
> AT91 framework was in flux so it seemed like a good idea to wait until that
> stabilized before I revisit putting a modern U-Boot on my boards "the right
> way".
> Ahh, Wolfgang compatible :). I still haven't really figured out exactly what is
> actually correct with the AT91 framework code yet. I just started playing with
> this a few weeks ago. There was a patch a little which back which was the
> reference implementation for the AT91 framework, but I could not find it
> when I searched my mail box.
> 
> > I only have one bank of RAM on my custom target so I didn't test the
> second bank.  On my targets the other EBI interface runs a bunch of slow
> peripherals.
> Ah, so dual RAM is no matter for you.
> 
> Which config header are you using? Naturally, I am using the sam9m10g45ek
> header, but since you have a slightly different board, which doesn't appear
> to have a header, how did you proceed?

I start with the 9G45EKES headers and throw things out.  My board is an EKES minus a lot of things - It is just a 9G45 with single bank RAM, SDCard and serial ports.  No display, dataflash, codec, or NAND.  I have USB ports on the board but don't need or want it in U-Boot.  I do have some interesting peripherals hanging off the second EBI but they don't come into play at U-Boot time.

Using a stock EKES U-Boot on my board will work - nothing bad happens on my board if U-Boot turns on the display controller for example.

I do have an official Atmel AT91SAM9G45-EKES for testing as well.  [And 9260 and 9G20 versions in the closet as well].  When testing U-Boot I get the Atmel board working then I start whittling down the configuration to fit my board.

> Best regards,
> Alex

Thanks,
Bill.

[U-Boot] [PATCH 2/8] Update at91sam9m10g45_devices.c to fix compile errors.

[Reinhard Meyer]

Dear Alex Waterman,
> Move this file to the new ATMEL_BASE_* and ATMEL_ID_* defines.
> 
> Also fixed a problem appearing in the ethernet initialization where
> the entire board was being reset, not just the ethernet controller.
> This at least makes ethernet work on my board if the correct
> environment (mac address, ip address, etc) is available on boot.
> 
> Signed-off-by: Alex Waterman <awaterman@dawning.com>
> ---
>  .../cpu/arm926ejs/at91/at91sam9m10g45_devices.c    |   26 ++++++++++----------
>  1 files changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
> index 4ad9b1f..9ef8966 100644
> --- a/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
> +++ b/arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
> @@ -26,42 +26,42 @@
>  #include <asm/arch/at91_common.h>
>  #include <asm/arch/at91_pmc.h>
>  #include <asm/arch/gpio.h>
> -#include <asm/arch/io.h>
> +#include <asm/io.h>
>  
>  void at91_serial0_hw_init(void)
>  {
> -	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
> +	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
>  
>  	at91_set_a_periph(AT91_PIO_PORTB, 19, 1);	/* TXD0 */
>  	at91_set_a_periph(AT91_PIO_PORTB, 18, 0);	/* RXD0 */
> -	writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer);
> +	writel(1 << ATMEL_ID_USART0, &pmc->pcer);
>  }
>  
>  void at91_serial1_hw_init(void)
>  {
> -	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
> +	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
>  
>  	at91_set_a_periph(AT91_PIO_PORTB, 4, 1);		/* TXD1 */
>  	at91_set_a_periph(AT91_PIO_PORTB, 5, 0);		/* RXD1 */
> -	writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer);
> +	writel(1 << ATMEL_ID_USART1, &pmc->pcer);
>  }
>  
>  void at91_serial2_hw_init(void)
>  {
> -	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
> +	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
>  
>  	at91_set_a_periph(AT91_PIO_PORTD, 6, 1);		/* TXD2 */
>  	at91_set_a_periph(AT91_PIO_PORTD, 7, 0);		/* RXD2 */
> -	writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer);
> +	writel(1 << ATMEL_ID_USART2, &pmc->pcer);
>  }
>  
>  void at91_serial3_hw_init(void)
>  {
> -	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
> +	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
>  
>  	at91_set_a_periph(AT91_PIO_PORTB, 12, 0);	/* DRXD */
>  	at91_set_a_periph(AT91_PIO_PORTB, 13, 1);	/* DTXD */
> -	writel(1 << AT91_ID_SYS, &pmc->pcer);
> +	writel(1 << ATMEL_ID_USART3, &pmc->pcer);
>  }

If this is the debug UART, ID_USART3 is definitely wrong here. Also
following the example set up by at91sam9260_devives.c, this function
should be named "at91_seriald_hw_init".

>  
>  void at91_serial_hw_init(void)

There should be no such function left after rework.


> @@ -86,14 +86,14 @@ void at91_serial_hw_init(void)
>  #ifdef CONFIG_ATMEL_SPI
>  void at91_spi0_hw_init(unsigned long cs_mask)
>  {
> -	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
> +	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
>  
>  	at91_set_a_periph(AT91_PIO_PORTB, 0, 0);	/* SPI0_MISO */
>  	at91_set_a_periph(AT91_PIO_PORTB, 1, 0);	/* SPI0_MOSI */
>  	at91_set_a_periph(AT91_PIO_PORTB, 2, 0);	/* SPI0_SPCK */
>  
>  	/* Enable clock */
> -	writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer);
> +	writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
>  
>  	if (cs_mask & (1 << 0)) {
>  		at91_set_a_periph(AT91_PIO_PORTB, 3, 0);
> @@ -123,14 +123,14 @@ void at91_spi0_hw_init(unsigned long cs_mask)
>  
>  void at91_spi1_hw_init(unsigned long cs_mask)
>  {
> -	at91_pmc_t	*pmc	= (at91_pmc_t *) AT91_PMC_BASE;
> +	at91_pmc_t	*pmc	= (at91_pmc_t *) ATMEL_BASE_PMC;
>  
>  	at91_set_a_periph(AT91_PIO_PORTB, 14, 0);	/* SPI1_MISO */
>  	at91_set_a_periph(AT91_PIO_PORTB, 15, 0);	/* SPI1_MOSI */
>  	at91_set_a_periph(AT91_PIO_PORTB, 16, 0);	/* SPI1_SPCK */
>  
>  	/* Enable clock */
> -	writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer);
> +	writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
>  
>  	if (cs_mask & (1 << 0)) {
>  		at91_set_a_periph(AT91_PIO_PORTB, 17, 0);

Those also miss the pull-up option like in at91sam9260_devices.c.


Please fix this file in the style done by at91sam9260_devices.c or
wait until I have done so.

Best Regards,
Reinhard

[U-Boot] [PATCH 3/8] Fix compile problem for some boards in the clock code.

[Reinhard Meyer]

Dear Alex Waterman,
> Some boards use AT91_SLOW_CLOCK and other use
> CONFIG_SYS_AT91_SLOW_CLOCK. This patch makes it so the arm926ejs
> clock code will return which ever is set.
> 
> Signed-off-by: Alex Waterman <awaterman@dawning.com>
> ---
>  arch/arm/cpu/arm926ejs/at91/clock.c |    4 ++++
>  1 files changed, 4 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/cpu/arm926ejs/at91/clock.c b/arch/arm/cpu/arm926ejs/at91/clock.c
> index 608af2c..0083bd2 100644
> --- a/arch/arm/cpu/arm926ejs/at91/clock.c
> +++ b/arch/arm/cpu/arm926ejs/at91/clock.c
> @@ -57,7 +57,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
>  {
>  	switch (css) {
>  	case AT91_PMC_MCKR_CSS_SLOW:
> +#ifdef AT91_SLOW_CLOCK
> +		return AT91_SLOW_CLOCK;
> +#else
>  		return CONFIG_SYS_AT91_SLOW_CLOCK;
> +#endif
>  	case AT91_PMC_MCKR_CSS_MAIN:
>  		return gd->main_clk_rate_hz;
>  	case AT91_PMC_MCKR_CSS_PLLA:

NAK. "Compile problems" for some boards shall not be fixed by hacks
into common source. Fix the board's definition file instead.

Best Regards,
Reinhard

[U-Boot] [PATCH 6/8] Adds wait to atmel_usart serial_init function

[Reinhard Meyer]

Dear Alex Waterman,
> Adds a short busy loop wait to the atmel_usart.c serial_init()
> function.
> 
> Signed-off-by: Alex Waterman <awaterman@dawning.com>
> ---
>  drivers/serial/atmel_usart.c |    6 ++++++
>  1 files changed, 6 insertions(+), 0 deletions(-)
> 
> diff --git a/drivers/serial/atmel_usart.c b/drivers/serial/atmel_usart.c
> index e326b2b..e355706 100644
> --- a/drivers/serial/atmel_usart.c
> +++ b/drivers/serial/atmel_usart.c
> @@ -47,6 +47,8 @@ void serial_setbrg(void)
>  
>  int serial_init(void)
>  {
> +
> +	volatile int i = 0;
>  	atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
>  
>  	writel(USART3_BIT(RSTRX) | USART3_BIT(RSTTX), &usart->cr);
> @@ -61,6 +63,10 @@ int serial_init(void)
>  			   | USART3_BF(NBSTOP, USART3_NBSTOP_1)),
>  			   &usart->mr);
>  
> +	/* Short wait to let the serial port init. */
> +	for (; i < 10000; i++)
> +		;
> +
>  	return 0;
>  }

1. Why is this delay needed in the first place?
Apparently it has not been required before.

2. Such a delay loop is highly dependant on toolchain,
cache and page situation and processor speed. It can not be
accepted as a solution. If a delay is really required here
and cannot be substituting by reading the UARTs status
register, udelay() must be used.

Best Regards,
Reinhard

[U-Boot] [PATCH 7/8] Updates the at91sam9m10g45ek.h config file.

[Reinhard Meyer]

Dear Alex Waterman,
> Moves to using newer defines and adds possible support for the
> second bank of RAM (if so desired).
> 
> Also, some coding clean up: removed the needless define to 1s for
> defines that just act as flags.
> 
> Signed-off-by: Alex Waterman <awaterman@dawning.com>
> ---
>  include/configs/at91sam9m10g45ek.h |  188 +++++++++++++++++++++--------------
>  1 files changed, 113 insertions(+), 75 deletions(-)
> 
> diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h
> index de74dcf..5e02dde 100644
> --- a/include/configs/at91sam9m10g45ek.h
> +++ b/include/configs/at91sam9m10g45ek.h
> @@ -27,48 +27,65 @@
>  #ifndef __CONFIG_H
>  #define __CONFIG_H
>  
> +/*#define DEBUG*/
> +
>  #define CONFIG_AT91_LEGACY
> +#define CONFIG_ATMEL_LEGACY
>  
>  /* ARM asynchronous clock */
> -#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* from 12 MHz crystal */
> +#define CONFIG_SYS_AT91_MAIN_CLOCK	12000000 /* from 12 MHz crystal */
> +#define AT91_SLOW_CLOCK		32768

Must be CONFIG_SYS_AT91_SLOW_CLOCK here.

>  #define CONFIG_SYS_HZ		1000
>  
> -#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
> -#ifdef CONFIG_AT91SAM9M10G45EK
> -#define CONFIG_AT91SAM9M10G45	1	/* It's an Atmel AT91SAM9M10G45 SoC*/
> -#else
> -#define CONFIG_AT91SAM9G45	1	/* It's an Atmel AT91SAM9G45 SoC*/
> -#endif
> +#define CONFIG_AT91SAM9M10G45
> +#define CONFIG_AT91FAMILY
>  #define CONFIG_ARCH_CPU_INIT
> +#define CONFIG_BOARD_EARLY_INIT_F
>  #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
>  
> -#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
> -#define CONFIG_SETUP_MEMORY_TAGS 1
> -#define CONFIG_INITRD_TAG	1
> +#define CONFIGMDLINE_TAG		/* enable passing of ATAGs	*/
> +#define CONFIG_SETUP_MEMORY_TAGS
> +#define CONFIG_INITRD_TAG
>  
>  #define CONFIG_SKIP_LOWLEVEL_INIT
>  
> +#define ATMEL_PIO_PORTS		5 /* 5 PIO ports. */
> +#define CONFIG_SYS_SDRAM_BASE   0x70000000
> +
>  /*
>   * Hardware drivers
>   */
> -#define CONFIG_AT91_GPIO	1
> -#define CONFIG_ATMEL_USART	1
> +#define CONFIG_AT91_GPIO
> +#define CONFIG_ATMEL_USART
>  #undef CONFIG_USART0
>  #undef CONFIG_USART1
>  #undef CONFIG_USART2
> -#define CONFIG_USART3		1	/* USART 3 is DBGU */
> +#define CONFIG_USART3		/* USART 3 is DBGU */
> +#define CONFIG_USART_BASE	0xffffee00 /* Use the DBGU hardware. */
> +#define CONFIG_USART_ID		10

Please follow the examples in at91sam9260ek.h
There is no CONFIG_USARTx anymore. Just defining
BASE and ID is sufficient.

> +
> +/*
> + * This needs to be defined for the OHCI code to work but it is defined as
> + * ATMEL_ID_UHPHS in the CPU specific header files.
> + */
> +#define ATMEL_ID_UHP		ATMEL_ID_UHPHS
> +
> +/*
> + * Specify the clock enable bit in the PMC_SCER register.
> + */
> +#define ATMEL_PMC_UHP		AT91SAM926x_PMC_UHP
>  
>  /* LCD */
> -#define CONFIG_LCD			1
> +#define CONFIG_LCD
>  #define LCD_BPP				LCD_COLOR8
> -#define CONFIG_LCD_LOGO			1
> +#define CONFIG_LCD_LOGO
>  #undef LCD_TEST_PATTERN
> -#define CONFIG_LCD_INFO			1
> -#define CONFIG_LCD_INFO_BELOW_LOGO	1
> -#define CONFIG_SYS_WHITE_ON_BLACK		1
> -#define CONFIG_ATMEL_LCD		1
> -#define CONFIG_ATMEL_LCD_RGB565		1
> -#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
> +#define CONFIG_LCD_INFO
> +#define CONFIG_LCD_INFO_BELOW_LOGO
> +#define CONFIG_SYS_WHITE_ON_BLACK
> +#define CONFIG_ATMEL_LCD
> +#define CONFIG_ATMEL_LCD_RGB565
> +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
>  /* board specific(not enough SRAM) */
>  #define CONFIG_AT91SAM9G45_LCD_BASE		0x73E00000
>  
> @@ -82,10 +99,10 @@
>  /*
>   * BOOTP options
>   */
> -#define CONFIG_BOOTP_BOOTFILESIZE	1
> -#define CONFIG_BOOTP_BOOTPATH		1
> -#define CONFIG_BOOTP_GATEWAY		1
> -#define CONFIG_BOOTP_HOSTNAME		1
> +#define CONFIG_BOOTP_BOOTFILESIZE
> +#define CONFIG_BOOTP_BOOTPATH
> +#define CONFIG_BOOTP_GATEWAY
> +#define CONFIG_BOOTP_HOSTNAME

Thanks for removing the "1"s !

>  
>  /*
>   * Command line configuration.
> @@ -98,35 +115,37 @@
>  #undef CONFIG_CMD_AUTOSCRIPT
>  #undef CONFIG_CMD_LOADS
>  
> -#define CONFIG_CMD_PING		1
> -#define CONFIG_CMD_DHCP		1
> -#define CONFIG_CMD_NAND		1
> -#define CONFIG_CMD_USB		1
> +#define CONFIG_CMD_PING
> +#define CONFIG_CMD_DHCP
> +#define CONFIG_CMD_NAND
> +#define CONFIG_CMD_USB
>  
>  /* SDRAM */
> -#define CONFIG_NR_DRAM_BANKS		1
> +#define CONFIG_NR_DRAM_BANKS		2
>  #define PHYS_SDRAM			0x70000000
>  #define PHYS_SDRAM_SIZE			0x08000000	/* 128 megs */
> +#define PHYS_SDRAM_2			0x20000000
> +#define PHYS_SDRAM_SIZE_2		0x08000000	/* 128 megs */

Preferably those numeric constants should be replaced by defines from a
proper at91sam10g45.h....

>  
>  /* DataFlash */
>  #ifdef CONFIG_ATMEL_SPI
>  #define CONFIG_CMD_SF
>  #define CONFIG_CMD_SPI
> -#define CONFIG_SPI_FLASH		1
> -#define CONFIG_SPI_FLASH_ATMEL		1
> +#define CONFIG_SPI_FLASH
> +#define CONFIG_SPI_FLASH_ATMEL
>  #define CONFIG_SYS_MAX_DATAFLASH_BANKS	1
>  #endif
>  
>  /* NOR flash, if populated */
> -#ifndef CONFIG_CMD_NAND
> -#define CONFIG_SYS_NO_FLASH		1
> +#ifdef CONFIG_CMD_NAND
> +#define CONFIG_SYS_NO_FLASH
>  #else
> -#define CONFIG_SYS_FLASH_CFI		1
> -#define CONFIG_FLASH_CFI_DRIVER		1
> +#define CONFIG_SYS_FLASH_CFI
> +#define CONFIG_FLASH_CFI_DRIVER
>  #define PHYS_FLASH_1			0x10000000
> -#define CONFIG_SYS_FLASH_BASE			PHYS_FLASH_1
> -#define CONFIG_SYS_MAX_FLASH_SECT		256
> -#define CONFIG_SYS_MAX_FLASH_BANKS		1
> +#define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
> +#define CONFIG_SYS_MAX_FLASH_SECT	256
> +#define CONFIG_SYS_MAX_FLASH_BANKS	1
>  #endif
>  
>  /* NAND flash */
> @@ -156,51 +175,69 @@
>  #define CONFIG_USB_ATMEL
>  #define CONFIG_USB_OHCI_NEW		1
>  #define CONFIG_DOS_PARTITION		1
> -#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
> -#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00700000	/* AT91SAM9G45_UHP_OHCI_BASE */
> -#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9g45"
> +#define CONFIG_SYS_USB_OHCI_CPU_INIT	1
> +#define CONFIG_SYS_USB_OHCI_REGS_BASE	0x00700000
> +#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9g45"
>  #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
>  #define CONFIG_USB_STORAGE		1

Preferably those numeric constants should be replaced by defines from a
proper at91sam10g45.h....

>  
> -#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
> -
> -#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
> -#define CONFIG_SYS_MEMTEST_END			0x23e00000
> -
> -#ifdef CONFIG_SYS_USE_DATAFLASH
> +#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
>  
> -/* bootstrap + u-boot + env + linux in dataflash on CS0 */
> -#define CONFIG_ENV_IS_IN_SPI_FLASH	1
> -#define CONFIG_SYS_MONITOR_BASE	(0xC0000000 + 0x8400)
> -#define CONFIG_ENV_OFFSET		0x4200
> -#define CONFIG_ENV_ADDR		(0xC0000000 + CONFIG_ENV_OFFSET)
> -#define CONFIG_ENV_SIZE		0x4200
> -#define CONFIG_ENV_SECT_SIZE		0x10000
> -#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
> -#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
> -				"root=/dev/mtdblock0 " \
> -				"mtdparts=atmel_nand:-(root) "\
> -				"rw rootfstype=jffs2"
> -
> -#else /* CONFIG_SYS_USE_NANDFLASH */
> +#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
> +#define CONFIG_SYS_MEMTEST_END		0x23e00000
>  
>  /* bootstrap + u-boot + env + linux in nandflash */
> -#define CONFIG_ENV_IS_IN_NAND	1
> +#define CONFIG_ENV_IS_IN_NAND
>  #define CONFIG_ENV_OFFSET		0x60000
>  #define CONFIG_ENV_OFFSET_REDUND	0x80000
> -#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
> -#define CONFIG_BOOTCOMMAND	"nand read 0x72000000 0x200000 0x200000; bootm"
> -#define CONFIG_BOOTARGS		"console=ttyS0,115200 " \
> -				"root=/dev/mtdblock5 " \
> -				"mtdparts=atmel_nand:128k(bootstrap)ro, \
> -				256k(uboot)ro,128k(env1)ro,128k(env2)ro, \
> -				2M(linux),-(root) " \
> -				"rw rootfstype=jffs2"
> +#define CONFIG_ENV_SIZE			0x20000
> +#define CONFIG_BOOTCOMMAND	"nand read 0x70000000 0x100000 0x200000;" \
> +	"bootm 0x70000000"
> +#define CONFIG_BOOTARGS							\
> +	"console=ttyS0,115200 "						\
> +	"root=/dev/mtdblock5 "						\
> +	"mtdparts=atmel_nand:128k(bootstrap)ro,"			\
> +	"256k(uboot)ro,128k(env1)ro,128k(env2)ro,"			\
> +	"2M at 1M(linux),-(root) "						\
> +	"rw rootfstype=jffs2"
> +
> +#define CONFIG_BAUDRATE			115200
> +#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
>  
> -#endif
> +/*
> + * Extra environment variables.
> + */
> +#define UPDATE_BOOTSTRAP				\
> +	"update_bootstrap="				\
> +	"tftpboot 0x70000000 ${_bootstrap}; "		\
> +	"nand erase 0x0 0x20000; "			\
> +	"nand write 0x70000000 0x0 0x20000\0"
> +#define UPDATE_UBOOT					\
> +	"update_uboot="					\
> +	"tftpboot 0x70000000 ${_uboot}; "		\
> +	"nand erase 0x20000 0x40000; "			\
> +	"nand write 0x70000000 0x20000 0x40000\0"
> +#define UPDATE_KERNEL					\
> +	"update_kernel="				\
> +	"tftpboot 0x70000000 ${_kernel}; "		\
> +	"nand erase 0x100000 0x200000; "		\
> +	"nand write 0x70000000 0x100000 0x200000\0"
> +#define UPDATE_FS					\
> +	"update_fs="					\
> +	"tftpboot 0x70000000 ${_rootfs}; "		\
> +	"nand erase 0x300000 0xfd00000; "		\
> +	"nand write 0x70000000 0x300000 ${filesize}\0"
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS			\
> +	UPDATE_BOOTSTRAP				\
> +	UPDATE_UBOOT					\
> +	UPDATE_KERNEL					\
> +	UPDATE_FS					\
> +	"_bootstrap=arm/at91bootstrap.bin\0"		\
> +	"_uboot=arm/u-boot.bin\0"			\
> +	"_kernel=arm/linux-kernel.bin\0"		\
> +	"_rootfs=arm/atmel_fs.bin\0"
>  
> -#define CONFIG_BAUDRATE		115200
> -#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
>  
>  #define CONFIG_SYS_PROMPT		"U-Boot> "
>  #define CONFIG_SYS_CBSIZE		256
> @@ -216,7 +253,8 @@
>   * Size of malloc() pool
>   */
>  #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
> -
> +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - \
> +				GENERATED_GBL_DATA_SIZE)
>  #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
>  
>  #ifdef CONFIG_USE_IRQ

Best Regards,
Reinhard

[U-Boot] [PATCH 8/8] Updates the boards.cfg file

[Reinhard Meyer]

Dear Alex Waterman,
> Add the default generic at91sam9m10g45ek_config target to the new
> config system. Not all possible configurations of u-boot for the
> at91sam9m10g45ek are included yet. Add them as needed.
> 
> Signed-off-by: Alex Waterman <awaterman@dawning.com>
> ---
>  boards.cfg |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/boards.cfg b/boards.cfg
> index dfefc3f..470bc18 100644
> --- a/boards.cfg
> +++ b/boards.cfg
> @@ -72,6 +72,7 @@ netstar                      arm         arm925t
>  voiceblue                    arm         arm925t
>  omap1510inn                  arm         arm925t     -                   ti
>  aspenite                     arm         arm926ejs   -                   Marvell        armada100
> +at91sam9m10g45ek             arm         arm926ejs   at91sam9m10g45ek	 atmel          at91
>  afeb9260                     arm         arm926ejs   -                   -              at91
>  at91cap9adk                  arm         arm926ejs   -                   atmel          at91
>  at91sam9260ek_nandflash      arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH

Please sort by manufacturer. The at91sam9m10 would be behind any atmel at91sam926x boards.

Best Regards,
Reinhard

[U-Boot] [PATCH 0/8] Fixes compilation for the at91sam9m10g45ek

[Thomas Petazzoni]

Hello Alex,

I am interested in seeing this work merged into U-Boot. Will you have
the time to fix the issues pointed out by Reinhard Meyer and post an
updated version, or would you accept if somebody else takes over your
patch set and posts an updated version ?

Thanks,

Thomas

Le Thu, 30 Jun 2011 15:32:59 -0400,
Alex Waterman <awaterman@dawning.com> a ?crit :

> This patch set fixes the at91sam9mg45ek build for my set up. I have
> only been able to test this patch on my own NAND booting 
> at91sam9m10g45ek. Dataflash and norflash are untested. Anyway,
> this is a rough approximation of a patch; I would need more input
> from people with nor-flash, working at91bootstrapers, dataflash,
> etc before I can get truely generic working at91sam9m10g45ek board
> support.
> 
> Also, some notes:
> 
> I wrote my own boot strapper because I could not find a working
> boot strapper. The boot strappers I found on the web either had their
> own issues or did not enable the second bank of RAM. Thus I wrote my
> own that works and enables the second bank of RAM. The patch here
> expects that the second bank works. If you are using a working
> at91bootstrapper or the like, I don't think that should cause this
> u-boot patch to not work; just set the number of banks back to 1 in
> the config file.
> 
> If I am not alone in having trouble with the existing at91bootstrap
> projects, maybe we could merge my bootstrapper into (or the
> preexisting at91bootstrapper proejcts) into the NAND SPL (for NAND
> booting boards) section of U-Boot?
> 
> Alex Waterman (8):
>   Remove old config stuff from Makefile
>   Update at91sam9m10g45_devices.c to fix compile errors.
>   Fix compile problem for some boards in the clock code.
>   Updates the at91sam9mg45_matrix.h header to new defines.
>   Updates the board specific files for the at91sam9mg45ek.
>   Adds wait to atmel_usart serial_init function
>   Updates the at91sam9m10g45ek.h config file.
>   Updates the boards.cfg file
> 
>  Makefile                                           |   21 ---
>  .../cpu/arm926ejs/at91/at91sam9m10g45_devices.c    |   26 ++--
>  arch/arm/cpu/arm926ejs/at91/clock.c                |    4 +
>  .../arm/include/asm/arch-at91/at91sam9g45_matrix.h |   84 +++++-----
>  board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c    |  128
> +++++++------- board/atmel/at91sam9m10g45ek/led.c
> |    6 +- boards.cfg                                         |    1 +
>  drivers/serial/atmel_usart.c                       |    6 +
>  include/configs/at91sam9m10g45ek.h                 |  188
> ++++++++++++-------- 9 files changed, 246 insertions(+), 218
> deletions(-)
> 



-- 
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com