From: Issa Gorissen <flop.m@usa.net>
To: Oliver Endriss <o.endriss@gmx.de>
Cc: linux-media@vger.kernel.org,
Mauro Carvalho Chehab <mchehab@redhat.com>,
Ralph Metzler <rmetzler@digitaldevices.de>
Subject: Re: [PATCH 13/16] cxd2099: Update to latest version
Date: Mon, 04 Jul 2011 14:17:49 +0200 [thread overview]
Message-ID: <4E11AF6D.4070502@usa.net> (raw)
In-Reply-To: <201107031900.59010@orion.escape-edv.de>
On 03/07/2011 19:00, Oliver Endriss wrote:
> @@ -284,53 +313,84 @@ static int init(struct cxd *ci)
> CHK_ERROR(write_reg(ci, 0x08, 0x28));
> CHK_ERROR(write_reg(ci, 0x14, 0x20));
>
> - CHK_ERROR(write_reg(ci, 0x09, 0x4D)); /* Input Mode C, BYPass Serial, TIVAL = low, MSB */
> + /* CHK_ERROR(write_reg(ci, 0x09, 0x4D));*/ /* Input Mode C, BYPass Serial, TIVAL = low, MSB */
> CHK_ERROR(write_reg(ci, 0x0A, 0xA7)); /* TOSTRT = 8, Mode B (gated clock), falling Edge, Serial, POL=HIGH, MSB */
>
> - /* Sync detector */
> CHK_ERROR(write_reg(ci, 0x0B, 0x33));
> CHK_ERROR(write_reg(ci, 0x0C, 0x33));
>
> CHK_ERROR(write_regm(ci, 0x14, 0x00, 0x0F));
> CHK_ERROR(write_reg(ci, 0x15, ci->clk_reg_b));
> CHK_ERROR(write_regm(ci, 0x16, 0x00, 0x0F));
> - CHK_ERROR(write_reg(ci, 0x17, ci->clk_reg_f));
> + CHK_ERROR(write_reg(ci, 0x17,ci->clk_reg_f));
>
> - CHK_ERROR(write_reg(ci, 0x20, 0x28)); /* Integer Divider, Falling Edge, Internal Sync, */
> - CHK_ERROR(write_reg(ci, 0x21, 0x00)); /* MCLKI = TICLK/8 */
> - CHK_ERROR(write_reg(ci, 0x22, 0x07)); /* MCLKI = TICLK/8 */
> + if (ci->cfg.clock_mode) {
> + if (ci->cfg.polarity) {
> + CHK_ERROR(write_reg(ci, 0x09, 0x6f));
> + } else {
> + CHK_ERROR(write_reg(ci, 0x09, 0x6d));
> + }
> + CHK_ERROR(write_reg(ci, 0x20, 0x68));
> + CHK_ERROR(write_reg(ci, 0x21, 0x00));
> + CHK_ERROR(write_reg(ci, 0x22, 0x02));
When clock_mode = 1, you set MKCLI to 9MHz. Comments in this code would
be really nice. Used by ddbrige it seems.
> + } else {
> + if (ci->cfg.polarity) {
> + CHK_ERROR(write_reg(ci, 0x09, 0x4f));
> + } else {
> + CHK_ERROR(write_reg(ci, 0x09, 0x4d));
> + }
>
> + CHK_ERROR(write_reg(ci, 0x20, 0x28));
> + CHK_ERROR(write_reg(ci, 0x21, 0x00));
> + CHK_ERROR(write_reg(ci, 0x22, 0x07));
> + }
When clock_mode = 0, input ts is in serial mode C, MCLKI = TICLK / 8 ;
why not set register 0x20 to 0x8 only ? Also, no need to set 0x21 nor
0x22 which are only for serial input mode D. And only used by ngene it
seems. Is TICLK equal to the bitrate variable (62000000) ? If yes, then
MCLKI can only reach a value of ~7,8MHz, which is not the maximum speed
of CAMs. Is this on purpose ? Ngene chip limitation ?
next prev parent reply other threads:[~2011-07-04 12:18 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-07-03 16:31 [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Oliver Endriss
2011-07-03 16:36 ` [PATCH 01/16] tda18271c2dd: Initial check-in Oliver Endriss
2011-07-03 16:37 ` [PATCH 02/16] tda18271c2dd: Lots of coding-style fixes Oliver Endriss
2011-07-03 16:49 ` [PATCH 05/16] DRX-K: Tons " Oliver Endriss
2011-07-03 16:51 ` [PATCH 06/16] DRX-K, TDA18271c2: Add build support Oliver Endriss
2011-07-03 16:53 ` [PATCH 07/16] get_dvb_firmware: Get DRX-K firmware for Digital Devices DVB-CT cards Oliver Endriss
2011-07-03 16:55 ` [PATCH 08/16] ngene: Support Digital Devices DuoFlex CT Oliver Endriss
2011-07-03 16:56 ` [PATCH 09/16] ngene: Codingstyle fixes Oliver Endriss
2011-07-03 16:57 ` [PATCH 10/16] ngene: Fix return code if no demux was found Oliver Endriss
2011-07-03 16:58 ` [PATCH 11/16] ngene: Fix name of Digital Devices PCIe/miniPCIe Oliver Endriss
2011-07-03 16:59 ` [PATCH 12/16] ngene: Support DuoFlex CT attached to CineS2 and SaTiX-S2 Oliver Endriss
2011-07-03 17:00 ` [PATCH 13/16] cxd2099: Update to latest version Oliver Endriss
2011-07-04 12:17 ` Issa Gorissen [this message]
2011-07-03 17:02 ` [PATCH 14/16] cxd2099: Codingstyle fixes Oliver Endriss
2011-07-03 17:03 ` [PATCH 15/16] ngene: Update for latest cxd2099 Oliver Endriss
2011-07-03 17:04 ` [PATCH 16/16] ngene: Strip dummy packets inserted by the driver Oliver Endriss
2011-07-03 17:54 ` [PATCH 04/16] DRX-K: Shrink size of drxk_map.h Oliver Endriss
2011-07-03 17:55 ` [PATCH 03/16] DRX-K: Initial check-in Oliver Endriss
2011-07-04 16:41 ` [PATCH 00/16] New drivers: DRX-K, TDA18271c2, Updates: CXD2099 and ngene Hans von Marwijk
2011-07-07 23:39 ` Oliver Endriss
2011-07-11 11:57 ` Devin Heitmueller
2011-07-11 16:18 ` Ralph Metzler
2011-07-11 16:27 ` Devin Heitmueller
2011-07-11 17:15 ` Ralph Metzler
2011-07-11 17:32 ` Devin Heitmueller
2011-07-11 17:19 ` Mauro Carvalho Chehab
2011-07-12 18:21 ` Michael Krufky
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