From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:45391) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QmAIb-0007su-Of for qemu-devel@nongnu.org; Wed, 27 Jul 2011 16:01:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QmAIa-00017Q-Of for qemu-devel@nongnu.org; Wed, 27 Jul 2011 16:01:45 -0400 Received: from mail-gy0-f173.google.com ([209.85.160.173]:45537) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QmAIa-00016r-M9 for qemu-devel@nongnu.org; Wed, 27 Jul 2011 16:01:44 -0400 Received: by gyg8 with SMTP id 8so1591372gyg.4 for ; Wed, 27 Jul 2011 13:01:43 -0700 (PDT) Message-ID: <4E306EA5.5020207@codemonkey.ws> Date: Wed, 27 Jul 2011 15:01:41 -0500 From: Anthony Liguori MIME-Version: 1.0 References: <1311558293-5855-1-git-send-email-aliguori@us.ibm.com> <4E2EBA1E.90006@redhat.com> <4E2EC90E.8090409@codemonkey.ws> <4E2ED0AA.3020101@redhat.com> <4E2EDE86.7020807@codemonkey.ws> <4E2F06C8.30403@redhat.com> <4E2F1448.3040106@codemonkey.ws> <4E2FD28F.2070206@redhat.com> <4E30091C.3070404@codemonkey.ws> <4E302FBF.4040500@redhat.com> <4E303CBF.8070801@codemonkey.ws> <4E305E3F.2050405@redhat.com> In-Reply-To: <4E305E3F.2050405@redhat.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC][PATCH 0/21] QEMU Object Model List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini Cc: Peter Maydell , qemu-devel@nongnu.org On 07/27/2011 01:51 PM, Paolo Bonzini wrote: > On 07/27/2011 06:28 PM, Anthony Liguori wrote: >> On 07/27/2011 10:33 AM, Paolo Bonzini wrote: >>> On 07/27/2011 02:48 PM, Anthony Liguori wrote: >>>> >>>> So the idea here is that the PIC will multiplex a bunch of interrupts >>>> into a single line? >>> >>> Yes, but the device needs to know the interrupt number so it can expose >>> it through the enumerator interface. So the configuration cannot be >>> simply >>> >>> pic->irq[n] = tty->irq; >>> >>> Logically, it's more similar to the ISA case, but I doubt the PIC >>> distributes all interrupts to everyone in real hardware. >>> >>>> Is the enumerator something that has an interface to devices where >>>> the devices hold this info? Or is the enumerator just a bank of >>>> flash that's preprogrammed with fixed info? >>> >>> The former, at least in theory. Not sure if it also works that way in >>> real hardware, but that's the model it exposes and the way the Android >>> guys implemented it. >> >> I can't really find what you're describing. I think all the specs are on >> http://www.milkymist.org/mmsoc.html > > That's milkymist, not GoldFish. Oh, Goldfish is fake. It's not real hardware. The enumerator device is not a real device. It's weird because it's imaginary and was designed specifically within QEMU. It's not a good example for discussing modelling. Regards, Anthony Liguori > > You can see the code at > https://github.com/patricksjackson/qemu/blob/android/hw/goldfish_device.c (see > also > https://github.com/patricksjackson/qemu/blob/android/hw/goldfish_device.h for > the structs composing the list). > > Paolo >