[U-Boot] Moving mx3fb.c to CONFIG_VIDEO

[U-Boot] Moving mx3fb.c to CONFIG_VIDEO

[Helmut Raiger]

The following patch partly rewrites mx3fb.c to be used along with
cfb_console.c. It was using CONFIG_LCD and now needs CONFIG_VIDEO.
The defines for some displays have been removed from the driver,
instead one may specify displays using the videmode env variable.

For what I could see, it breaks support for qong and the phycore
board. I'd appreciate, if someone (Stefano?) could test on these boards
(using the correct videomode setting).

The phycore board specifies 8bit colors in the setup, the driver
was only tested for a 565 set-up. Either the board setup is changed
to 16bits or the driver needs some extra care.



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[U-Boot] [PATCH 1/2] mx31: make HSP clock for mx3fb driver available

[Helmut Raiger]

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
---
 arch/arm/cpu/arm1136/mx31/generic.c    |   14 ++++++++++++++
 arch/arm/include/asm/arch-mx31/clock.h |    1 +
 2 files changed, 15 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index 248431b..b077d29 100644
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -72,6 +72,18 @@ static u32 mx31_get_ipg_clk(void)
 	return freq;
 }
 
+/* hsp is the clock for the ipu */
+static u32 mx31_get_hsp_clk(void)
+{
+	u32 freq = mx31_get_mcu_main_clk();
+	u32 pdr0 = __REG(CCM_PDR0);
+
+	/* divided by HSP_PODF in PDR0 */
+	freq /= ((pdr0 >> 11) & 0x7) + 1;
+
+	return freq;
+}
+
 void mx31_dump_clocks(void)
 {
 	u32 cpufreq = mx31_get_mcu_main_clk();
@@ -88,6 +100,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	case MXC_CSPI_CLK:
 	case MXC_UART_CLK:
 		return mx31_get_ipg_clk();
+	case MXC_IPU_CLK:
+		return mx31_get_hsp_clk();
 	}
 	return -1;
 }
diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h
index fb035c4..b0aa1ce 100644
--- a/arch/arm/include/asm/arch-mx31/clock.h
+++ b/arch/arm/include/asm/arch-mx31/clock.h
@@ -29,6 +29,7 @@ enum mxc_clock {
 	MXC_IPG_CLK,
 	MXC_CSPI_CLK,
 	MXC_UART_CLK,
+	MXC_IPU_CLK
 };
 
 unsigned int mxc_get_clock(enum mxc_clock clk);
-- 
1.7.4.4



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[U-Boot] [PATCH 2/2] mx3fb: move to CONFIG_VIDEO to support videomodes

[Helmut Raiger]

mx3fb.c was based on CONFIG_LCD and is moved by this patch to
CONFIG_VIDEO, which has greater freedom in selecting videomodes
even at runtime.

This renders the accumulating list of display defines
(CONFIG_DISPLAY_VBEST..., CONFIG_DISPLAY_C057...) obsolete as
these may be setup through env variables:

setenv mydisplay "video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,
	le:9,ri:17,up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0"
setenv videomode mydisplay

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
---
 drivers/video/Makefile      |    2 +-
 drivers/video/cfb_console.c |    7 +
 drivers/video/mx3fb.c       |  353 +++++++++++++++++++++++++------------------
 3 files changed, 213 insertions(+), 149 deletions(-)

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 086dc05..2c0e500 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -34,7 +34,7 @@ COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
 COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
-COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o
+COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MX5) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
 COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
 COBJS-$(CONFIG_SED156X) += sed156x.o
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 3a93b64..4e653b8 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -161,6 +161,13 @@
 #endif
 
 /*
+ * Defines for the i.MX31 driver (mx3fb.c)
+ */
+#ifdef CONFIG_VIDEO_MX3
+#define VIDEO_FB_16BPP_WORD_SWAP
+#endif
+
+/*
  * Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc.
  */
 #include <video_fb.h>
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c
index 0c925a0..1808ec3 100644
--- a/drivers/video/mx3fb.c
+++ b/drivers/video/mx3fb.c
@@ -1,6 +1,8 @@
 /*
  * Copyright (C) 2009
  * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ * Copyright (C) 2011
+ * HALE electronic GmbH, <helmut.raiger@hale.at>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -21,100 +23,19 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
-#include <lcd.h>
-#include <asm/arch/clock.h>
+#include <malloc.h>
+#include <video_fb.h>
+
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
-void *lcd_base;			/* Start of framebuffer memory	*/
-void *lcd_console_address;	/* Start of console buffer	*/
-
-int lcd_line_length;
-int lcd_color_fg;
-int lcd_color_bg;
-
-short console_col;
-short console_row;
-
-void lcd_initcolregs(void)
-{
-}
-
-void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
-{
-}
-
-void lcd_disable(void)
-{
-}
-
-void lcd_panel_disable(void)
-{
-}
+#include "videomodes.h"
 
-#define msleep(a) udelay(a * 1000)
-
-#if defined(CONFIG_DISPLAY_VBEST_VGG322403)
-#define XRES		320
-#define YRES		240
-#define PANEL_TYPE	IPU_PANEL_TFT
-#define PIXEL_CLK	156000
-#define PIXEL_FMT	IPU_PIX_FMT_RGB666
-#define H_START_WIDTH	20		/* left_margin */
-#define H_SYNC_WIDTH	30		/* hsync_len */
-#define H_END_WIDTH	(38 + 30)	/* right_margin + hsync_len */
-#define V_START_WIDTH	7		/* upper_margin */
-#define V_SYNC_WIDTH	3		/* vsync_len */
-#define V_END_WIDTH	(26 + 3)	/* lower_margin + vsync_len */
-#define SIG_POL		(DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
-#define IF_CONF		0
-#define IF_CLK_DIV	0x175
-#elif defined(CONFIG_DISPLAY_COM57H5M10XRC)
-#define XRES		640
-#define YRES		480
-#define PANEL_TYPE	IPU_PANEL_TFT
-#define PIXEL_CLK	40000
-#define PIXEL_FMT	IPU_PIX_FMT_RGB666
-#define H_START_WIDTH	120		/* left_margin */
-#define H_SYNC_WIDTH	30		/* hsync_len */
-#define H_END_WIDTH	(10 + 30)	/* right_margin + hsync_len */
-#define V_START_WIDTH	35		/* upper_margin */
-#define V_SYNC_WIDTH	3		/* vsync_len */
-#define V_END_WIDTH	(7 + 3)	/* lower_margin + vsync_len */
-#define SIG_POL		(DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
-#define IF_CONF		0
-#define IF_CLK_DIV	0x55
-#else
-#define XRES		240
-#define YRES		320
-#define PANEL_TYPE	IPU_PANEL_TFT
-#define PIXEL_CLK	185925
-#define PIXEL_FMT	IPU_PIX_FMT_RGB666
-#define H_START_WIDTH	9		/* left_margin */
-#define H_SYNC_WIDTH	1		/* hsync_len */
-#define H_END_WIDTH	(16 + 1)	/* right_margin + hsync_len */
-#define V_START_WIDTH	7		/* upper_margin */
-#define V_SYNC_WIDTH	1		/* vsync_len */
-#define V_END_WIDTH	(9 + 1)		/* lower_margin + vsync_len */
-#define SIG_POL		(DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
+/* this might need panel specific set-up as-well */
 #define IF_CONF		0
-#define IF_CLK_DIV	0x175
-#endif
 
-#define LCD_COLOR_IPU	LCD_COLOR16
-
-static ushort colormap[256];
-
-vidinfo_t panel_info = {
-	.vl_col		= XRES,
-	.vl_row		= YRES,
-	.vl_bpix	= LCD_COLOR_IPU,
-	.cmap		= colormap,
-};
-
-#define BIT_PER_PIXEL	NBITS(LCD_COLOR_IPU)
+/* -------------- controller specific stuff -------------- */
 
 /* IPU DMA Controller channel definitions. */
 enum ipu_channel {
@@ -438,6 +359,14 @@ union chan_param_mem {
 	struct chan_param_mem_interleaved	ip;
 };
 
+DECLARE_GLOBAL_DATA_PTR;
+
+/* graphics setup */
+static GraphicDevice panel;
+static struct ctfb_res_modes *mode;
+static struct ctfb_res_modes var_mode;
+
+
 static inline u32 reg_read(unsigned long reg)
 {
 	return __REG(reg);
@@ -452,28 +381,39 @@ static inline void reg_write(u32 value, unsigned long reg)
  * sdc_init_panel() - initialize a synchronous LCD panel.
  * @width:		width of panel in pixels.
  * @height:		height of panel in pixels.
- * @pixel_fmt:		pixel format of buffer as FOURCC ASCII code.
  * @return:		0 on success or negative error code on failure.
  */
-static int sdc_init_panel(u16 width, u16 height, enum pixel_fmt pixel_fmt)
+static int sdc_init_panel(u16 width, u16 height,
+		enum pixel_fmt di_setup, enum ipu_panel di_panel)
 {
-	u32 reg;
+	u32 reg, div;
 	uint32_t old_conf;
 
+	debug("%s(width=%d, height=%d)\n", __func__, width, height);
+
 	/* Init panel size and blanking periods */
-	reg = ((H_SYNC_WIDTH - 1) << 26) |
-		((u32)(width + H_START_WIDTH + H_END_WIDTH - 1) << 16);
+	reg = width + mode->left_margin + mode->right_margin - 1;
+	if (reg > 1023) {
+		debug("display width too large, coerced to 1023!");
+		reg = 1023;
+	}
+	reg = ((mode->hsync_len - 1) << 26) | (reg << 16);
 	reg_write(reg, SDC_HOR_CONF);
 
-	reg = ((V_SYNC_WIDTH - 1) << 26) | SDC_V_SYNC_WIDTH_L |
-		((u32)(height + V_START_WIDTH + V_END_WIDTH - 1) << 16);
+	reg = height + mode->upper_margin + mode->lower_margin - 1;
+	if (reg > 1023) {
+		debug("display height too large, coerced to 1023!");
+		reg = 1023;
+	}
+	reg = ((mode->vsync_len - 1) << 26) | SDC_V_SYNC_WIDTH_L | (reg << 16);
 	reg_write(reg, SDC_VER_CONF);
 
-	switch (PANEL_TYPE) {
+	switch (di_panel) {
 	case IPU_PANEL_SHARP_TFT:
 		reg_write(0x00FD0102L, SDC_SHARP_CONF_1);
 		reg_write(0x00F500F4L, SDC_SHARP_CONF_2);
 		reg_write(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
+		/* TODO: probably IF_CONF must be adapted (see below)! */
 		break;
 	case IPU_PANEL_TFT:
 		reg_write(SDC_COM_TFT_COLOR, SDC_COM_CONF);
@@ -484,43 +424,62 @@ static int sdc_init_panel(u16 width, u16 height, enum pixel_fmt pixel_fmt)
 
 	/* Init clocking */
 
-	/*
-	 * Calculate divider: fractional part is 4 bits so simply multiple by
-	 * 2^4 to get fractional part, as long as we stay under ~250MHz and on
-	 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
+	/* Calculate divider: the IPU receives its clock from the hsp divder */
+	/* fractional part is 4 bits so simply multiple by 2^4 to get it
+	 * but make sure we avoid overflows, pixclock is given in pico seconds
+	 *   16*1024*128*476837 =  0.9999996682e12
 	 */
+	div = ((mxc_get_clock(MXC_IPU_CLK)/1024)*(mode->pixclock/128))/476837;
+	debug("hsp_clk is %d, div=%d\n", mxc_get_clock(MXC_IPU_CLK), div);
+	/* coerce to not less than 4.0, not more than 255.9375 */
+	if (div < 0x40)
+		div = 0x40;
+	else if (div > 0xFFF)
+		div = 0xFFF;
+	/* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less
+	 * fraction bits. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR
+	 * based on timing debug DISP3_IF_CLK_UP_WR is 0
+	 */
+	reg_write((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
 
-	reg_write((((IF_CLK_DIV / 8) - 1) << 22) |
-			IF_CLK_DIV, DI_DISP3_TIME_CONF);
-
-	/* DI settings */
+	/* DI settings for display 3: clock idle (bit 26) during vsync */
 	old_conf = reg_read(DI_DISP_IF_CONF) & 0x78FFFFFF;
 	reg_write(old_conf | IF_CONF, DI_DISP_IF_CONF);
 
+	/* only set display 3 polarity bits */
 	old_conf = reg_read(DI_DISP_SIG_POL) & 0xE0FFFFFF;
-	reg_write(old_conf | SIG_POL, DI_DISP_SIG_POL);
+	reg_write(old_conf | mode->sync, DI_DISP_SIG_POL);
 
-	reg_write(fmt_cfg[pixel_fmt].b0, DI_DISP3_B0_MAP);
-	reg_write(fmt_cfg[pixel_fmt].b1, DI_DISP3_B1_MAP);
-	reg_write(fmt_cfg[pixel_fmt].b2, DI_DISP3_B2_MAP);
+	reg_write(fmt_cfg[di_setup].b0, DI_DISP3_B0_MAP);
+	reg_write(fmt_cfg[di_setup].b1, DI_DISP3_B1_MAP);
+	reg_write(fmt_cfg[di_setup].b2, DI_DISP3_B2_MAP);
 	reg_write(reg_read(DI_DISP_ACC_CC) |
-		  ((fmt_cfg[pixel_fmt].acc - 1) << 12), DI_DISP_ACC_CC);
+		  ((fmt_cfg[di_setup].acc - 1) << 12), DI_DISP_ACC_CC);
+
+	debug("DI_DISP_IF_CONF = 0x%08X\n",	reg_read(DI_DISP_IF_CONF));
+	debug("DI_DISP_SIG_POL = 0x%08X\n", reg_read(DI_DISP_SIG_POL));
+	debug("DI_DISP3_TIME_CONF = 0x%08X\n", reg_read(DI_DISP3_TIME_CONF));
+	debug("SDC_HOR_CONF = 0x%08X\n", reg_read(SDC_HOR_CONF));
+	debug("SDC_VER_CONF = 0x%08X\n", reg_read(SDC_VER_CONF));
 
 	return 0;
 }
 
 static void ipu_ch_param_set_size(union chan_param_mem *params,
-				  uint32_t pixel_fmt, uint16_t width,
+				  uint pixelfmt, uint16_t width,
 				  uint16_t height, uint16_t stride)
 {
+	debug("%s(pixelfmt=%d, width=%d, height=%d, stride=%d)\n",
+			__func__, pixelfmt, width, height, stride);
+
 	params->pp.fw		= width - 1;
 	params->pp.fh_l		= height - 1;
 	params->pp.fh_h		= (height - 1) >> 8;
 	params->pp.sl		= stride - 1;
 
 	/* See above, for further formats see the Linux driver */
-	switch (pixel_fmt) {
-	case IPU_PIX_FMT_RGB565:
+	switch (pixelfmt) {
+	case GDF_16BIT_565RGB:
 		params->ip.bpp	= 2;
 		params->ip.pfs	= 4;
 		params->ip.npb	= 7;
@@ -533,7 +492,7 @@ static void ipu_ch_param_set_size(union chan_param_mem *params,
 		params->ip.wid1	= 5;		/* Green bit width - 1 */
 		params->ip.wid2	= 4;		/* Blue bit width - 1 */
 		break;
-	case IPU_PIX_FMT_RGB24:
+	case GDF_32BIT_X888RGB:
 		params->ip.bpp	= 1;		/* 24 BPP & RGB PFS */
 		params->ip.pfs	= 4;
 		params->ip.npb	= 7;
@@ -547,6 +506,7 @@ static void ipu_ch_param_set_size(union chan_param_mem *params,
 		params->ip.wid2	= 7;		/* Blue bit width - 1 */
 		break;
 	default:
+		printf("pixel format not supported!\n");
 		break;
 	}
 
@@ -574,16 +534,6 @@ static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
 	}
 }
 
-static uint32_t bpp_to_pixfmt(int bpp)
-{
-	switch (bpp) {
-	case 16:
-		return IPU_PIX_FMT_RGB565;
-	default:
-		return 0;
-	}
-}
-
 static uint32_t dma_param_addr(enum ipu_channel channel)
 {
 	/* Channel Parameter Memory */
@@ -596,11 +546,13 @@ static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem)
 	uint32_t reg;
 	uint32_t stride_bytes;
 
-	stride_bytes = (XRES * ((BIT_PER_PIXEL + 7) / 8) + 3) & ~3;
+	stride_bytes = (panel.plnSizeX * panel.gdfBytesPP + 3) & ~3;
+
+	debug("%s(channel=%d, fbmem=0x%x)\n", __func__, channel, fbmem);
 
 	/* Build parameter memory data for DMA channel */
-	ipu_ch_param_set_size(&params, bpp_to_pixfmt(BIT_PER_PIXEL),
-			      XRES, YRES, stride_bytes);
+	ipu_ch_param_set_size(&params, panel.gdfIndex,
+			      panel.plnSizeX, panel.plnSizeY, stride_bytes);
 	ipu_ch_param_set_buffer(&params, fbmem, NULL);
 	params.pp.bam = 0;
 	/* Some channels (rotation) have restriction on burst length */
@@ -715,31 +667,33 @@ static void sdc_enable_channel(void *fbmem)
 	 * interrupts. Next sdc_set_brightness() is going to be called
 	 * from mx3fb_blank().
 	 */
-	msleep(2);
+	udelay(2000);
 }
 
 /*
  * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
  * @return:	0 on success or negative error code on failure.
+ *  TODO: currently only 666 and TFT as DI setup supported
  */
 static int mx3fb_set_par(void)
 {
 	int ret;
 
-	ret = sdc_init_panel(XRES, YRES, PIXEL_FMT);
+	ret = sdc_init_panel(panel.plnSizeX, panel.plnSizeY,
+			IPU_PIX_FMT_RGB666, IPU_PANEL_TFT);
 	if (ret < 0)
 		return ret;
 
-	reg_write((H_START_WIDTH << 16) | V_START_WIDTH, SDC_BG_POS);
+	reg_write((mode->left_margin << 16) | mode->upper_margin, SDC_BG_POS);
 
 	return 0;
 }
 
-/* References in this function refer to respective Linux kernel sources */
-void lcd_enable(void)
+static void ll_disp3_enable(void *base)
 {
 	u32 reg;
 
+	debug("%s(base=0x%x)\n", __func__, (u32) base);
 	/* pcm037.c::mxc_board_init() */
 
 	/* Display Interface #3 */
@@ -823,35 +777,138 @@ void lcd_enable(void)
 
 	mx3fb_set_par();
 
-	sdc_enable_channel(lcd_base);
+	sdc_enable_channel(base);
 
 	/*
 	 * Linux driver calls sdc_set_brightness() here again,
 	 * once is enough for us
 	 */
+	debug("%s() done\n", __func__);
 }
 
-void lcd_ctrl_init(void *lcdbase)
+/* ------------------------ public part ------------------- */
+ulong calc_fbsize(void)
 {
-	u32 mem_len = XRES * YRES * BIT_PER_PIXEL / 8;
-	/*
-	 * We rely on lcdbase being a physical address, i.e., either MMU off,
-	 * or 1-to-1 mapping. Might want to add some virt2phys here.
-	 */
-	if (!lcdbase)
-		return;
-
-	memset(lcdbase, 0, mem_len);
+	return panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP;
 }
 
-ulong calc_fbsize(void)
+/*
+ * The current implementation is only tested for GDF_16BIT_565RGB!
+ * It was switched from the original CONFIG_LCD setup to CONFIG_VIDEO,
+ * because the lcd code seemed loaded with color table stuff, that
+ * does not relate to most modern TFTs. cfb_console.c looks more
+ * straight forward.
+ * This is the environment setting for the original setup
+     "unknown=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17,
+		up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0"
+     "videomode=unknown"
+*/
+void *video_hw_init(void)
 {
-	return ((panel_info.vl_col * panel_info.vl_row *
-		NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
+	char *penv;
+	u32 memsize;
+	unsigned long t1, hsynch, vsynch;
+	int bits_per_pixel, i, tmp, vesa_idx = 0, videomode;
+
+	tmp = 0;
+
+	videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
+	/* get video mode via environment */
+	penv = getenv("videomode");
+	if (penv) {
+		/* decide if it is a string */
+		if (penv[0] <= '9') {
+			videomode = (int) simple_strtoul(penv, NULL, 16);
+			tmp = 1;
+		}
+	} else {
+		tmp = 1;
+	}
+	if (tmp) {
+		/* parameter are vesa modes */
+		/* search params */
+		for (i = 0; i < VESA_MODES_COUNT; i++) {
+			if (vesa_modes[i].vesanr == videomode)
+				break;
+		}
+		if (i == VESA_MODES_COUNT) {
+			printf("no VESA Mode found, switching to mode 0x%x ",
+					CONFIG_SYS_DEFAULT_VIDEO_MODE);
+			i = 0;
+		}
+		mode = (struct ctfb_res_modes *)
+				&res_mode_init[vesa_modes[i].resindex];
+		bits_per_pixel = vesa_modes[i].bits_per_pixel;
+		vesa_idx = vesa_modes[i].resindex;
+	} else {
+		mode = (struct ctfb_res_modes *) &var_mode;
+		bits_per_pixel = video_get_params(mode, penv);
+	}
+
+	/* calculate hsynch and vsynch freq (info only) */
+	t1 = (mode->left_margin + mode->xres +
+	      mode->right_margin + mode->hsync_len) / 8;
+	t1 *= 8;
+	t1 *= mode->pixclock;
+	t1 /= 1000;
+	hsynch = 1000000000L / t1;
+	t1 *= (mode->upper_margin + mode->yres +
+	       mode->lower_margin + mode->vsync_len);
+	t1 /= 1000;
+	vsynch = 1000000000L / t1;
+
+	/* fill in Graphic device struct */
+	sprintf(panel.modeIdent, "%dx%dx%d %ldkHz %ldHz",
+			mode->xres, mode->yres,
+			bits_per_pixel, (hsynch / 1000), (vsynch / 1000));
+	printf("%s\n", panel.modeIdent);
+	panel.winSizeX = mode->xres;
+	panel.winSizeY = mode->yres;
+	panel.plnSizeX = mode->xres;
+	panel.plnSizeY = mode->yres;
+
+	switch (bits_per_pixel) {
+	case 24:
+		panel.gdfBytesPP = 4;
+		panel.gdfIndex = GDF_32BIT_X888RGB;
+		break;
+	case 16:
+		panel.gdfBytesPP = 2;
+		panel.gdfIndex = GDF_16BIT_565RGB;
+		break;
+	default:
+		panel.gdfBytesPP = 1;
+		panel.gdfIndex = GDF__8BIT_INDEX;
+		break;
+	}
+
+	/* set up Hardware */
+	memsize = calc_fbsize();
+
+	debug("%s() allocating %d bytes\n", __func__, memsize);
+
+	/* fill in missing Graphic device struct */
+	panel.frameAdrs = (u32) malloc(memsize);
+	if (panel.frameAdrs == 0) {
+		printf("%s() malloc(%d) failed\n", __func__, memsize);
+		return 0;
+	}
+	panel.memSize = memsize;
+
+	ll_disp3_enable((void *) panel.frameAdrs);
+	memset((void *) panel.frameAdrs, 0, memsize);
+
+	debug("%s() done, framebuffer at 0x%x, size=%d cleared\n",
+			__func__, panel.frameAdrs, memsize);
+
+	return (void *) &panel;
 }
 
-int overwrite_console(void)
+void video_set_lut(unsigned int index,	/* color number */
+		    unsigned char r,	/* red */
+		    unsigned char g,	/* green */
+		    unsigned char b	/* blue */
+		    )
 {
-	/* Keep stdout / stderr on serial, our LCD is for splashscreen only */
-	return 1;
+	return;
 }
-- 
1.7.4.4



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[U-Boot] [PATCH 1/2] mx31: make HSP clock for mx3fb driver available

[Marek Vasut]

On Monday, August 22, 2011 03:41:36 PM Helmut Raiger wrote:
> Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
> ---
>  arch/arm/cpu/arm1136/mx31/generic.c    |   14 ++++++++++++++
>  arch/arm/include/asm/arch-mx31/clock.h |    1 +
>  2 files changed, 15 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/cpu/arm1136/mx31/generic.c
> b/arch/arm/cpu/arm1136/mx31/generic.c index 248431b..b077d29 100644
> --- a/arch/arm/cpu/arm1136/mx31/generic.c
> +++ b/arch/arm/cpu/arm1136/mx31/generic.c
> @@ -72,6 +72,18 @@ static u32 mx31_get_ipg_clk(void)
>  	return freq;
>  }
> 
> +/* hsp is the clock for the ipu */
> +static u32 mx31_get_hsp_clk(void)
> +{
> +	u32 freq = mx31_get_mcu_main_clk();
> +	u32 pdr0 = __REG(CCM_PDR0);

Can't we do readl() here?

> +
> +	/* divided by HSP_PODF in PDR0 */
> +	freq /= ((pdr0 >> 11) & 0x7) + 1;

Um, don't we have defined constants for those magic numbers already?

> +
> +	return freq;
> +}
> +
>  void mx31_dump_clocks(void)
>  {
>  	u32 cpufreq = mx31_get_mcu_main_clk();
> @@ -88,6 +100,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
>  	case MXC_CSPI_CLK:
>  	case MXC_UART_CLK:
>  		return mx31_get_ipg_clk();
> +	case MXC_IPU_CLK:
> +		return mx31_get_hsp_clk();
>  	}
>  	return -1;
>  }
> diff --git a/arch/arm/include/asm/arch-mx31/clock.h
> b/arch/arm/include/asm/arch-mx31/clock.h index fb035c4..b0aa1ce 100644
> --- a/arch/arm/include/asm/arch-mx31/clock.h
> +++ b/arch/arm/include/asm/arch-mx31/clock.h
> @@ -29,6 +29,7 @@ enum mxc_clock {
>  	MXC_IPG_CLK,
>  	MXC_CSPI_CLK,
>  	MXC_UART_CLK,
> +	MXC_IPU_CLK
>  };
> 
>  unsigned int mxc_get_clock(enum mxc_clock clk);

Cheers

[U-Boot] [PATCH 1/2] mx31: make HSP clock for mx3fb driver available

[Helmut Raiger]

On 08/22/2011 04:00 PM, Marek Vasut wrote:
> +	u32 pdr0 = __REG(CCM_PDR0);
> Can't we do readl() here?
>
>> +
>> +	/* divided by HSP_PODF in PDR0 */
>> +	freq /= ((pdr0>>  11)&  0x7) + 1;
> Um, don't we have defined constants for those magic numbers already?
Masks are not defined for i.MX31 (imx-regs.h), so I simply followed the 
code, which was in the file. The generic.c file for MX35 however is a 
different story.

To keep things simple, I suggest we leave it at that for now.

Helmut





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[U-Boot] [PATCH 1/2] mx31: make HSP clock for mx3fb driver available

[Marek Vasut]

On Monday, August 22, 2011 05:00:15 PM Helmut Raiger wrote:
> On 08/22/2011 04:00 PM, Marek Vasut wrote:
> > +	u32 pdr0 = __REG(CCM_PDR0);
> > Can't we do readl() here?
> > 
> >> +
> >> +	/* divided by HSP_PODF in PDR0 */
> >> +	freq /= ((pdr0>>  11)&  0x7) + 1;
> > 
> > Um, don't we have defined constants for those magic numbers already?
> 
> Masks are not defined for i.MX31 (imx-regs.h), so I simply followed the
> code, which was in the file. The generic.c file for MX35 however is a
> different story.
> 
> To keep things simple, I suggest we leave it at that for now.

And noone's gonna fix it later. No please, define the proper constants please.

Thanks in advance
> 
> Helmut
> 
> 
> 
> 
> 
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[U-Boot] [PATCH 1/2] mx31: make HSP clock for mx3fb driver available

[Helmut Raiger]

On 08/22/2011 05:02 PM, Marek Vasut wrote:
>
>> Masks are not defined for i.MX31 (imx-regs.h), so I simply followed the
>> code, which was in the file. The generic.c file for MX35 however is a
>> different story.
>>
>> To keep things simple, I suggest we leave it at that for now.
> And noone's gonna fix it later. No please, define the proper constants please.
>
Do you really expect me to fix code in all the arch/arm/cpu/arm1136/mx31 
files (2000+ lines) that use that kind of access, because I add 15 lines 
to one of them? There are some 50 other drivers and boards etc. that 
depend on imx-regs.h, which probably use these access methods as-well!

I'm not prepared to take this effort, sorry. After all this is 
_COSMETIC_, while this new mx3fb driver really works nicely ;-)
If anyone out there modifies these files, I'll definitely rebase the 
driver to it.

Helmut


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[U-Boot] [PATCH 1/2] mx31: make HSP clock for mx3fb driver available

[Marek Vasut]

On Monday, August 22, 2011 05:51:05 PM Helmut Raiger wrote:
> On 08/22/2011 05:02 PM, Marek Vasut wrote:
> >> Masks are not defined for i.MX31 (imx-regs.h), so I simply followed the
> >> code, which was in the file. The generic.c file for MX35 however is a
> >> different story.
> >> 
> >> To keep things simple, I suggest we leave it at that for now.
> > 
> > And noone's gonna fix it later. No please, define the proper constants
> > please.
> 
> Do you really expect me to fix code in all the arch/arm/cpu/arm1136/mx31
> files (2000+ lines) that use that kind of access, because I add 15 lines
> to one of them? There are some 50 other drivers and boards etc. that
> depend on imx-regs.h, which probably use these access methods as-well!

Hey, calm down, I didn't say anything about fixing gazilion of crap (even though 
that'd be nice of you !).

Actually, I did a quick look and see arch/arm/include/arch-mx35/crm_regs.h 
containing PDR0 definitions. Though they don't match your constants. It's either 
bug in the crm_regs.h or your code.

> 
> I'm not prepared to take this effort, sorry. After all this is
> _COSMETIC_, while this new mx3fb driver really works nicely ;-)

Oh my sense for metrosexuality of code really kicks in here ;-)

> If anyone out there modifies these files, I'll definitely rebase the
> driver to it.

It has nothing to do with your driver, the problem I have is with these few 
magic numbers you use in 1/2 (make HSP clock ...). You can use constants from 
crm_regs.h, see above.
> 
> Helmut

Cheers!
> 
> 
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[U-Boot] Moving mx3fb.c to CONFIG_VIDEO

[Stefano Babic]

On 08/22/2011 03:41 PM, Helmut Raiger wrote:
> The following patch partly rewrites mx3fb.c to be used along with
> cfb_console.c. It was using CONFIG_LCD and now needs CONFIG_VIDEO.
> The defines for some displays have been removed from the driver,
> instead one may specify displays using the videmode env variable.

Hi Helmut,

thanks to fix this point. It was also on my todo list, but really not on
the top, an I was waiting the occasion when I

The long list of hardcoded display configurations is very nasty, I am
happy to get rid of it.

Please add also Anatolij in CC, as maintainer of the video subsystem.

> For what I could see, it breaks support for qong and the phycore
> board. I'd appreciate, if someone (Stefano?) could test on these boards
> (using the correct videomode setting).

I am not sure I could test (I do not have now the board), but I will
try. Maybe in next days.

> The phycore board specifies 8bit colors in the setup, the driver
> was only tested for a 565 set-up. Either the board setup is changed
> to 16bits or the driver needs some extra care.

No chance to test the phycore on my side, maybe someone else....

Regards,
Stefano Babic

-- 
=====================================================================
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 1/2] mx31: make HSP clock for mx3fb driver available

[Stefano Babic]

On 08/22/2011 05:51 PM, Helmut Raiger wrote:
> On 08/22/2011 05:02 PM, Marek Vasut wrote:
>>
>>> Masks are not defined for i.MX31 (imx-regs.h), so I simply followed the
>>> code, which was in the file. The generic.c file for MX35 however is a
>>> different story.
>>>
>>> To keep things simple, I suggest we leave it at that for now.
>> And noone's gonna fix it later. No please, define the proper constants please.
>>

Hi Helmut,

> Do you really expect me to fix code in all the arch/arm/cpu/arm1136/mx31 
> files (2000+ lines) that use that kind of access, because I add 15 lines 
> to one of them? 

No, nobody thinks you should do this. However, should be not better to
fix it for the 15 lines of code you added ?

Agree that a lot of things in imx-regs.h for i.MX31 are missing. The
i.MX31 was the first i.MX processor added to u-boot, and there are still
some parts that are different from the rest of IMX code.

However, can you add a simple macro to get the HSP_PODF field ? I agree
it does not change the behavior, but it helps a bit to understand the
code without running to the i.MX31 manual...

Macro to set the PODR register are already defined in imx-regs.h. As you
pointed out, there is no macro to get values from the register.

>There are some 50 other drivers and boards etc. that 
> depend on imx-regs.h, which probably use these access methods as-well!

Yes, I know. I am trying to uniform the behavior between i.MX processors.

> I'm not prepared to take this effort, sorry.

Do not do it, it is not asked. We make always a step-by-step approach.
Add defines only for the part you added (as I can see, it is only
related to get the HSP_PODF field in podr register), and let the rest of
the 2000+ lines untouched.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 1/2] mx31: make HSP clock for mx3fb driver available

[Marek Vasut]

On Monday, August 22, 2011 06:02:10 PM Marek Vasut wrote:
> On Monday, August 22, 2011 05:51:05 PM Helmut Raiger wrote:
> > On 08/22/2011 05:02 PM, Marek Vasut wrote:
> > >> Masks are not defined for i.MX31 (imx-regs.h), so I simply followed
> > >> the code, which was in the file. The generic.c file for MX35 however
> > >> is a different story.
> > >> 
> > >> To keep things simple, I suggest we leave it at that for now.
> > > 
> > > And noone's gonna fix it later. No please, define the proper constants
> > > please.
> > 
> > Do you really expect me to fix code in all the arch/arm/cpu/arm1136/mx31
> > files (2000+ lines) that use that kind of access, because I add 15 lines
> > to one of them? There are some 50 other drivers and boards etc. that
> > depend on imx-regs.h, which probably use these access methods as-well!
> 
> Hey, calm down, I didn't say anything about fixing gazilion of crap (even
> though that'd be nice of you !).
> 
> Actually, I did a quick look and see arch/arm/include/arch-mx35/crm_regs.h
> containing PDR0 definitions. Though they don't match your constants. It's
> either bug in the crm_regs.h or your code.

Ah sorry, it's mx31. Right, the defines are missing. Do what Stefano said then. 
And really ... noone wants you to modify gazilions of lines, just your few :)

Cheers and sorry for misguiding you about mx35.

[U-Boot] [PATCH 2/2] mx3fb: move to CONFIG_VIDEO to support videomodes

[Stefano Babic]

On 08/22/2011 03:41 PM, Helmut Raiger wrote:

Hi Helmut,

> mx3fb.c was based on CONFIG_LCD and is moved by this patch to
> CONFIG_VIDEO, which has greater freedom in selecting videomodes
> even at runtime.
> 
> This renders the accumulating list of display defines
> (CONFIG_DISPLAY_VBEST..., CONFIG_DISPLAY_C057...) obsolete as
> these may be setup through env variables:
> 
> setenv mydisplay "video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,
> 	le:9,ri:17,up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0"
> setenv videomode mydisplay

Really betters as hard coded in driver...

I see you updated the code synchronizing it with the linux driver. Add
to the commit message the kernel version (better: the commit id) of the
kernel you used as base for your changes, so that everybody in future
can know where it comes from.

> +DECLARE_GLOBAL_DATA_PTR;
> +
> +/* graphics setup */
> +static GraphicDevice panel;
> +static struct ctfb_res_modes *mode;
> +static struct ctfb_res_modes var_mode;
> +
> +

One newline should be enough.

>  static inline u32 reg_read(unsigned long reg)
>  {
>  	return __REG(reg);
> @@ -452,28 +381,39 @@ static inline void reg_write(u32 value, unsigned long reg)
>   * sdc_init_panel() - initialize a synchronous LCD panel.
>   * @width:		width of panel in pixels.
>   * @height:		height of panel in pixels.
> - * @pixel_fmt:		pixel format of buffer as FOURCC ASCII code.

pixel_fmt is still in the parameter list, and di_panel should be added
to the description.

>   * @return:		0 on success or negative error code on failure.
>   */
> -static int sdc_init_panel(u16 width, u16 height, enum pixel_fmt pixel_fmt)
> +static int sdc_init_panel(u16 width, u16 height,
> +		enum pixel_fmt di_setup, enum ipu_panel di_panel)
>  {
> -	u32 reg;
> +	u32 reg, div;
>  	uint32_t old_conf;
>  
> +	debug("%s(width=%d, height=%d)\n", __func__, width, height);
> +
>  	/* Init panel size and blanking periods */
> -	reg = ((H_SYNC_WIDTH - 1) << 26) |
> -		((u32)(width + H_START_WIDTH + H_END_WIDTH - 1) << 16);
> +	reg = width + mode->left_margin + mode->right_margin - 1;
> +	if (reg > 1023) {
> +		debug("display width too large, coerced to 1023!");
> +		reg = 1023;

I do not if it is better to try to adapt the values if the caller pass
to the function wrong parameters. Probably it does not work. I think in
these case it is better to output an error (print instead of debug) and
return without with an error. What do you think ?

> -	switch (PANEL_TYPE) {
> +	switch (di_panel) {
>  	case IPU_PANEL_SHARP_TFT:
>  		reg_write(0x00FD0102L, SDC_SHARP_CONF_1);
>  		reg_write(0x00F500F4L, SDC_SHARP_CONF_2);
>  		reg_write(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
> +		/* TODO: probably IF_CONF must be adapted (see below)! */

I do not understand this comment.

>  	/* Init clocking */
>  
> -	/*
> -	 * Calculate divider: fractional part is 4 bits so simply multiple by
> -	 * 2^4 to get fractional part, as long as we stay under ~250MHz and on
> -	 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
> +	/* Calculate divider: the IPU receives its clock from the hsp divder */
> +	/* fractional part is 4 bits so simply multiple by 2^4 to get it

Multiline comments, you should use the same style as in the removed lines.

> +	div = ((mxc_get_clock(MXC_IPU_CLK)/1024)*(mode->pixclock/128))/476837;

I try to understand this line. pixclock is in ps, as in kernel. I am
missing something. I am expecting to have the same formula as in kernel,
where I can read:

div = clk_get_rate(ipu_clk) * 16 / pixel_clk;

Where does 476837 come from ?

> +	debug("hsp_clk is %d, div=%d\n", mxc_get_clock(MXC_IPU_CLK), div);
> +	/* coerce to not less than 4.0, not more than 255.9375 */
> +	if (div < 0x40)
> +		div = 0x40;
> +	else if (div > 0xFFF)
> +		div = 0xFFF;
> +	/* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less
> +	 * fraction bits. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR
> +	 * based on timing debug DISP3_IF_CLK_UP_WR is 0
> +	 */
> +	reg_write((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);

Right. This code is now with the linux driver synchronized. If I could
understand how div is computed and because it is different from the
linux driver...

> +/*
> + * The current implementation is only tested for GDF_16BIT_565RGB!
> + * It was switched from the original CONFIG_LCD setup to CONFIG_VIDEO,
> + * because the lcd code seemed loaded with color table stuff, that
> + * does not relate to most modern TFTs. cfb_console.c looks more
> + * straight forward.
> + * This is the environment setting for the original setup
> +     "unknown=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17,
> +		up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0"
> +     "videomode=unknown"

Multiline comment. As "original setup" you mean the setup if not
CONFIG_DISPLAY_* was set, right ?

> +void *video_hw_init(void)
>  {
> -	return ((panel_info.vl_col * panel_info.vl_row *
> -		NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
> +	char *penv;
> +	u32 memsize;
> +	unsigned long t1, hsynch, vsynch;
> +	int bits_per_pixel, i, tmp, vesa_idx = 0, videomode;
> +
> +	tmp = 0;
> +
> +	videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;

Ok. This is a way to fix qong/phycore after merging these patches, and
avoid that they do not work anymore if the videomode variable is not
set. I write it down...

> +	/* get video mode via environment */
> +	penv = getenv("videomode");
> +	if (penv) {
> +		/* decide if it is a string */
> +		if (penv[0] <= '9') {
> +			videomode = (int) simple_strtoul(penv, NULL, 16);
> +			tmp = 1;
> +		}
> +	} else {
> +		tmp = 1;
> +	}
> +	if (tmp) {
> +		/* parameter are vesa modes */
> +		/* search params */
> +		for (i = 0; i < VESA_MODES_COUNT; i++) {
> +			if (vesa_modes[i].vesanr == videomode)
> +				break;
> +		}
> +		if (i == VESA_MODES_COUNT) {
> +			printf("no VESA Mode found, switching to mode 0x%x ",
> +					CONFIG_SYS_DEFAULT_VIDEO_MODE);
> +			i = 0;
> +		}
> +		mode = (struct ctfb_res_modes *)
> +				&res_mode_init[vesa_modes[i].resindex];
> +		bits_per_pixel = vesa_modes[i].bits_per_pixel;
> +		vesa_idx = vesa_modes[i].resindex;
> +	} else {
> +		mode = (struct ctfb_res_modes *) &var_mode;
> +		bits_per_pixel = video_get_params(mode, penv);
> +	}

Anatolij, should be this code not general ? It is not strictly related
to the i.MX. Should we put it in another place ?

> +
> +	/* calculate hsynch and vsynch freq (info only) */
> +	t1 = (mode->left_margin + mode->xres +
> +	      mode->right_margin + mode->hsync_len) / 8;
> +	t1 *= 8;
> +	t1 *= mode->pixclock;
> +	t1 /= 1000;
> +	hsynch = 1000000000L / t1;
> +	t1 *= (mode->upper_margin + mode->yres +
> +	       mode->lower_margin + mode->vsync_len);
> +	t1 /= 1000;
> +	vsynch = 1000000000L / t1;
> +
> +	/* fill in Graphic device struct */
> +	sprintf(panel.modeIdent, "%dx%dx%d %ldkHz %ldHz",
> +			mode->xres, mode->yres,
> +			bits_per_pixel, (hsynch / 1000), (vsynch / 1000));
> +	printf("%s\n", panel.modeIdent);

Should we not use "debug" instead ?

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 1/2] mx31: make HSP clock for mx3fb driver available

[Helmut Raiger]

On 08/22/2011 06:02 PM, Marek Vasut wrote:
> ... _COSMETIC_, while this new mx3fb driver really works nicely ;-)
> Oh my sense for metrosexuality of code really kicks in here ;-)
Arousal was not my first objective, but deliberately endorsed :-P

I'll do what can be done easily concerning the bit accesses.
Helmut



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[U-Boot] [PATCH 2/2] mx3fb: move to CONFIG_VIDEO to support videomodes

[Helmut Raiger]

On 08/22/2011 07:13 PM, Stefano Babic wrote:
> I see you updated the code synchronizing it with the linux driver. Add
> to the commit message the kernel version (better: the commit id) of the
> kernel you used as base for your changes, so that everybody in future
> can know where it comes from.
Ok.

>> +static struct ctfb_res_modes *mode;
>> +static struct ctfb_res_modes var_mode;
>> +
>> +
> One newline should be enough.
Sure.

>> - * @pixel_fmt:		pixel format of buffer as FOURCC ASCII code.
> pixel_fmt is still in the parameter list, and di_panel should be added
> to the description.
I'll update it.

>> +	reg = width + mode->left_margin + mode->right_margin - 1;
>> +	if (reg>  1023) {
>> +		debug("display width too large, coerced to 1023!");
>> +		reg = 1023;
> I do not if it is better to try to adapt the values if the caller pass
> to the function wrong parameters. Probably it does not work. I think in
> these case it is better to output an error (print instead of debug) and
> return without with an error. What do you think ?
>
I put that code in as I tried to adjust the porches (left and right 
margin) for our display.
If it is coerced the way I did, you'll never overwrite other bits in the 
same register field, so
you can still see the effect it has. I preferred it during display 
configuration, so I left it in.
We could output an error (not only during debug builds) but write the 
registers anyway.

>> -	switch (PANEL_TYPE) {
>> +	switch (di_panel) {
>>   	case IPU_PANEL_SHARP_TFT:
>>   		reg_write(0x00FD0102L, SDC_SHARP_CONF_1);
>>   		reg_write(0x00F500F4L, SDC_SHARP_CONF_2);
>>   		reg_write(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
>> +		/* TODO: probably IF_CONF must be adapted (see below)! */
> I do not understand this comment.

Each display specific define found an equivalent in the ctfb_res_modes 
struct.
IF_CONF however is currently always 0, but might need adaption for SHARP 
TFT panels, which
I could not test.

>>   	/* Init clocking */
>>
>> -	/*
>> -	 * Calculate divider: fractional part is 4 bits so simply multiple by
>> -	 * 2^4 to get fractional part, as long as we stay under ~250MHz and on
>> -	 * i.MX31 it (HSP_CLK) is<= 178MHz. Currently 128.267MHz
>> +	/* Calculate divider: the IPU receives its clock from the hsp divder */
>> +	/* fractional part is 4 bits so simply multiple by 2^4 to get it
> Multiline comments, you should use the same style as in the removed lines.
Ok.

>> +	div = ((mxc_get_clock(MXC_IPU_CLK)/1024)*(mode->pixclock/128))/476837;
> I try to understand this line. pixclock is in ps, as in kernel. I am
> missing something. I am expecting to have the same formula as in kernel,
> where I can read:
>
> div = clk_get_rate(ipu_clk) * 16 / pixel_clk;
>
> Where does 476837 come from ?

Well I already thought that might need another line of comment. In the 
kernel the pixel_clk really
is a clock value, while it is a time (in pico seconds) in this driver. I 
could have calculated the
pixel clock from the pixel time value first:

pixel_clk = 1e12 / mode->pixclock;
div = ipu_clk * 16 / pixel_clk;

I simply put that into one calculation:

div = ipu_clk * 16 / (1e12 / mode->pixclock)

or

div = ipu_clk * mode->pixclock / ~60e6;

but this would provoke an overflow problem during the multiplication, so 
I split the division to
1024, 128 and 476837 which exactly gives 1e12 / 16 (~60e6). So I have 2 
shifts a multiplication and a division.

Probably I simply put the 2 code lines above into a comment. The name 
'pixel_clk' is actually misleading, but it sat there already. We could 
use 'pixel_ps' in ctfb_res_modes instead?

>> +/*
>> + * The current implementation is only tested for GDF_16BIT_565RGB!
>> + * It was switched from the original CONFIG_LCD setup to CONFIG_VIDEO,
>> + * because the lcd code seemed loaded with color table stuff, that
>> + * does not relate to most modern TFTs. cfb_console.c looks more
>> + * straight forward.
>> + * This is the environment setting for the original setup
>> +     "unknown=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17,
>> +		up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0"
>> +     "videomode=unknown"
> Multiline comment. As "original setup" you mean the setup if not
> CONFIG_DISPLAY_* was set, right ?

I'll fix the comment and yes you're right.

>> +void *video_hw_init(void)
>>   {
>> -	return ((panel_info.vl_col * panel_info.vl_row *
>> -		NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
>> +	char *penv;
>> +	u32 memsize;
>> +	unsigned long t1, hsynch, vsynch;
>> +	int bits_per_pixel, i, tmp, vesa_idx = 0, videomode;
>> +
>> +	tmp = 0;
>> +
>> +	videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
> Ok. This is a way to fix qong/phycore after merging these patches, and
> avoid that they do not work anymore if the videomode variable is not
> set. I write it down...
>
Perfect. I could have done that already, but lacking hardware to test 
with ...

> Anatolij, should be this code not general ? It is not strictly related
> to the i.MX. Should we put it in another place ?
>
I thought of that as-well.

>> +
>> +	/* fill in Graphic device struct */
>> +	sprintf(panel.modeIdent, "%dx%dx%d %ldkHz %ldHz",
>> +			mode->xres, mode->yres,
>> +			bits_per_pixel, (hsynch / 1000), (vsynch / 1000));
>> +	printf("%s\n", panel.modeIdent);
> Should we not use "debug" instead ?
The kernel driver also outputs this during probe, but debug is fine with me.

Thanks for the review, I'll give it a few more days to settle and 
deliver a V2 then.
Helmut



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[U-Boot] [PATCH 2/2] mx3fb: move to CONFIG_VIDEO to support videomodes

[Helmut Raiger]

Please ignore the 2 messages sent at 8:30, obviously the save and send 
buttons changed position.
Helmut


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[U-Boot] [PATCH 1/2] mx31: make HSP clock for mx3fb driver available

[Marek Vasut]

On Wednesday, August 24, 2011 08:55:03 AM Helmut Raiger wrote:
> On 08/22/2011 06:02 PM, Marek Vasut wrote:
> > ... _COSMETIC_, while this new mx3fb driver really works nicely ;-)
> > Oh my sense for metrosexuality of code really kicks in here ;-)
> 
> Arousal was not my first objective, but deliberately endorsed :-P

Hehe :-D
> 
> I'll do what can be done easily concerning the bit accesses.
> Helmut

Thanks!

> 
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[U-Boot] [PATCH 2/2] mx3fb: move to CONFIG_VIDEO to support videomodes

[Helmut Raiger]

I just found that the mx3fb driver uses:

static inline u32 reg_read(unsigned long reg)
{
        return __REG(reg);
}

static inline void reg_write(u32 value, unsigned long reg)
{
        __REG(reg) = value;
}

I am about to change this to readl() and writel(), should I do it in a 
separate 'cosmetic only' patch before the really thing?
As it is more or less a re-write anyway (350 of 900 lines changed), it 
think its probably ok to do it in one shot.

Helmut


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[U-Boot] [PATCH 2/2] mx3fb: move to CONFIG_VIDEO to support videomodes

[Stefano Babic]

On 08/24/2011 05:34 PM, Helmut Raiger wrote:
> 
> I just found that the mx3fb driver uses:
> 
> static inline u32 reg_read(unsigned long reg)
> {
>         return __REG(reg);
> }
> 
> static inline void reg_write(u32 value, unsigned long reg)
> {
>         __REG(reg) = value;
> }
> 

i.MX31 is quite old, and it was pushed before general ARM accessors were
introduced in u-boot. This is the reason. I appreciate you will fix this
point.

> I am about to change this to readl() and writel(), should I do it in a 
> separate 'cosmetic only' patch before the really thing?
> As it is more or less a re-write anyway (350 of 900 lines changed), it 
> think its probably ok to do it in one shot.

IMHO you can do in one shot - you can mention this change in the commit
message.

Best regards,
Stefano Babic

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] Version 2 of 'Moving mx3fb to CONFIG_VIDEO'

[Helmut Raiger]

For details of version 2, please consult the patch history of the individual patches.



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[U-Boot] [PATCH 1/2] mx31: make HSP clock for mx3fb driver available

[Helmut Raiger]

This additionally updates mx31/generic.c by
- replacing __REG() macro accesses with readl() and writel()
- providing macros for PDR0 and PLL bit accesses
It also fixes a warning about the prototype of imx_get_uartclk(void)

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
---
V2: uses macros and readl(), writel(), see commit message

 arch/arm/cpu/arm1136/mx31/generic.c       |   40 +++++++++++++++++++---------
 arch/arm/include/asm/arch-mx31/clock.h    |    3 +-
 arch/arm/include/asm/arch-mx31/imx-regs.h |   14 ++++++++++
 3 files changed, 43 insertions(+), 14 deletions(-)

diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index 248431b..9a7612b 100644
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -28,10 +28,10 @@
 
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
-	u32 mfi = (reg >> 10) & 0xf;
-	u32 mfn = reg & 0x3ff;
-	u32 mfd = (reg >> 16) & 0x3ff;
-	u32 pd =  (reg >> 26) & 0xf;
+	u32 mfi = GET_PLL_MFI(reg);
+	u32 mfn = GET_PLL_MFN(reg);
+	u32 mfd = GET_PLL_MFD(reg);
+	u32 pd =  GET_PLL_PD(reg);
 
 	mfi = mfi <= 5 ? 5 : mfi;
 	mfd += 1;
@@ -45,12 +45,12 @@ static u32 mx31_get_mpl_dpdgck_clk(void)
 {
 	u32 infreq;
 
-	if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
+	if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
 		infreq = CONFIG_MX31_CLK32 * 1024;
 	else
 		infreq = CONFIG_MX31_HCLK_FREQ;
 
-	return mx31_decode_pll(__REG(CCM_MPCTL), infreq);
+	return mx31_decode_pll(readl(CCM_MPCTL), infreq);
 }
 
 static u32 mx31_get_mcu_main_clk(void)
@@ -64,10 +64,21 @@ static u32 mx31_get_mcu_main_clk(void)
 static u32 mx31_get_ipg_clk(void)
 {
 	u32 freq = mx31_get_mcu_main_clk();
-	u32 pdr0 = __REG(CCM_PDR0);
+	u32 pdr0 = readl(CCM_PDR0);
 
-	freq /= ((pdr0 >> 3) & 0x7) + 1;
-	freq /= ((pdr0 >> 6) & 0x3) + 1;
+	freq /= GET_PDR0_MAX_PODF(pdr0) + 1;
+	freq /= GET_PDR0_IPG_PODF(pdr0) + 1;
+
+	return freq;
+}
+
+/* hsp is the clock for the ipu */
+static u32 mx31_get_hsp_clk(void)
+{
+	u32 freq = mx31_get_mcu_main_clk();
+	u32 pdr0 = readl(CCM_PDR0);
+
+	freq /= GET_PDR0_HSP_PODF(pdr0) + 1;
 
 	return freq;
 }
@@ -77,6 +88,7 @@ void mx31_dump_clocks(void)
 	u32 cpufreq = mx31_get_mcu_main_clk();
 	printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000);
 	printf("ipg clock     : %dHz\n", mx31_get_ipg_clk());
+	printf("hsp clock     : %dHz\n", mx31_get_hsp_clk());
 }
 
 unsigned int mxc_get_clock(enum mxc_clock clk)
@@ -88,6 +100,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	case MXC_CSPI_CLK:
 	case MXC_UART_CLK:
 		return mx31_get_ipg_clk();
+	case MXC_IPU_CLK:
+		return mx31_get_hsp_clk();
 	}
 	return -1;
 }
@@ -104,10 +118,10 @@ void mx31_gpio_mux(unsigned long mode)
 	reg = IOMUXC_BASE + (mode & 0x1fc);
 	shift = (~mode & 0x3) * 8;
 
-	tmp = __REG(reg);
+	tmp = readl(reg);
 	tmp &= ~(0xff << shift);
 	tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
-	__REG(reg) = tmp;
+	writel(tmp, reg);
 }
 
 void mx31_set_pad(enum iomux_pins pin, u32 config)
@@ -118,10 +132,10 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
 	reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
 	field = (pin + 2) % 3;
 
-	l = __REG(reg);
+	l = readl(reg);
 	l &= ~(0x1ff << (field * 10));
 	l |= config << (field * 10);
-	__REG(reg) = l;
+	writel(l, reg);
 
 }
 
diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h
index fb035c4..1ea5a47 100644
--- a/arch/arm/include/asm/arch-mx31/clock.h
+++ b/arch/arm/include/asm/arch-mx31/clock.h
@@ -29,10 +29,11 @@ enum mxc_clock {
 	MXC_IPG_CLK,
 	MXC_CSPI_CLK,
 	MXC_UART_CLK,
+	MXC_IPU_CLK
 };
 
 unsigned int mxc_get_clock(enum mxc_clock clk);
-extern u32 imx_get_uartclk();
+extern u32 imx_get_uartclk(void);
 extern void mx31_gpio_mux(unsigned long mode);
 extern void mx31_set_pad(enum iomux_pins pin, u32 config);
 
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 3c8d607..c24dae2 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -518,6 +518,20 @@ enum iomux_pins {
 #define PLL_MFI(x)		(((x) & 0xf) << 10)
 #define PLL_MFN(x)		(((x) & 0x3ff) << 0)
 
+#define GET_PDR0_CSI_PODF(x)	(((x) >> 23) & 0x1ff)
+#define GET_PDR0_PER_PODF(x)	(((x) >> 16) & 0x1f)
+#define GET_PDR0_HSP_PODF(x)	(((x) >> 11) & 0x7)
+#define GET_PDR0_NFC_PODF(x)	(((x) >> 8) & 0x7)
+#define GET_PDR0_IPG_PODF(x)	(((x) >> 6) & 0x3)
+#define GET_PDR0_MAX_PODF(x)	(((x) >> 3) & 0x7)
+#define GET_PDR0_MCU_PODF(x)	((x) & 0x7)
+
+#define GET_PLL_PD(x)		(((x) >> 26) & 0xf)
+#define GET_PLL_MFD(x)		(((x) >> 16) & 0x3ff)
+#define GET_PLL_MFI(x)		(((x) >> 10) & 0xf)
+#define GET_PLL_MFN(x)		(((x) >> 0) & 0x3ff)
+
+
 #define WEIM_ESDCTL0	0xB8001000
 #define WEIM_ESDCFG0	0xB8001004
 #define WEIM_ESDCTL1	0xB8001008
-- 
1.7.4.4



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[U-Boot] [PATCH 2/2] Moving mx3fb.c to CONFIG_VIDEO

[Helmut Raiger]

mx3fb.c was based on CONFIG_LCD and is moved by this patch to
CONFIG_VIDEO, which has greater freedom in selecting videomodes
even at runtime.

This renders the accumulating list of display defines
(CONFIG_DISPLAY_VBEST..., CONFIG_DISPLAY_C057...) obsolete as
these may be setup through env variables:

setenv mydisplay
  "video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,
        le:9,ri:17,up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0"
  setenv videomode mydisplay

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
---
V2:
 - replace __REG() in mx3fb.c by readl()/writel()
 - cosmetic changes (newlines, multiline comments)
 - clock init and divider setup clarified
 - printf() instead of debug() for width and height coerces

 drivers/video/Makefile      |    2 +-
 drivers/video/cfb_console.c |    7 +
 drivers/video/mx3fb.c       |  449 +++++++++++++++++++++++++------------------
 3 files changed, 265 insertions(+), 193 deletions(-)

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 086dc05..2c0e500 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -34,7 +34,7 @@ COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
 COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
-COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o
+COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MX5) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
 COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
 COBJS-$(CONFIG_SED156X) += sed156x.o
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 3a93b64..4e653b8 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -161,6 +161,13 @@
 #endif
 
 /*
+ * Defines for the i.MX31 driver (mx3fb.c)
+ */
+#ifdef CONFIG_VIDEO_MX3
+#define VIDEO_FB_16BPP_WORD_SWAP
+#endif
+
+/*
  * Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc.
  */
 #include <video_fb.h>
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c
index 0c925a0..0f33847 100644
--- a/drivers/video/mx3fb.c
+++ b/drivers/video/mx3fb.c
@@ -1,6 +1,8 @@
 /*
  * Copyright (C) 2009
  * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ * Copyright (C) 2011
+ * HALE electronic GmbH, <helmut.raiger@hale.at>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -21,100 +23,20 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
-#include <lcd.h>
-#include <asm/arch/clock.h>
+#include <malloc.h>
+#include <video_fb.h>
+
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
+#include <asm/io.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
-void *lcd_base;			/* Start of framebuffer memory	*/
-void *lcd_console_address;	/* Start of console buffer	*/
-
-int lcd_line_length;
-int lcd_color_fg;
-int lcd_color_bg;
-
-short console_col;
-short console_row;
-
-void lcd_initcolregs(void)
-{
-}
-
-void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
-{
-}
-
-void lcd_disable(void)
-{
-}
-
-void lcd_panel_disable(void)
-{
-}
+#include "videomodes.h"
 
-#define msleep(a) udelay(a * 1000)
-
-#if defined(CONFIG_DISPLAY_VBEST_VGG322403)
-#define XRES		320
-#define YRES		240
-#define PANEL_TYPE	IPU_PANEL_TFT
-#define PIXEL_CLK	156000
-#define PIXEL_FMT	IPU_PIX_FMT_RGB666
-#define H_START_WIDTH	20		/* left_margin */
-#define H_SYNC_WIDTH	30		/* hsync_len */
-#define H_END_WIDTH	(38 + 30)	/* right_margin + hsync_len */
-#define V_START_WIDTH	7		/* upper_margin */
-#define V_SYNC_WIDTH	3		/* vsync_len */
-#define V_END_WIDTH	(26 + 3)	/* lower_margin + vsync_len */
-#define SIG_POL		(DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
+/* this might need panel specific set-up as-well */
 #define IF_CONF		0
-#define IF_CLK_DIV	0x175
-#elif defined(CONFIG_DISPLAY_COM57H5M10XRC)
-#define XRES		640
-#define YRES		480
-#define PANEL_TYPE	IPU_PANEL_TFT
-#define PIXEL_CLK	40000
-#define PIXEL_FMT	IPU_PIX_FMT_RGB666
-#define H_START_WIDTH	120		/* left_margin */
-#define H_SYNC_WIDTH	30		/* hsync_len */
-#define H_END_WIDTH	(10 + 30)	/* right_margin + hsync_len */
-#define V_START_WIDTH	35		/* upper_margin */
-#define V_SYNC_WIDTH	3		/* vsync_len */
-#define V_END_WIDTH	(7 + 3)	/* lower_margin + vsync_len */
-#define SIG_POL		(DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
-#define IF_CONF		0
-#define IF_CLK_DIV	0x55
-#else
-#define XRES		240
-#define YRES		320
-#define PANEL_TYPE	IPU_PANEL_TFT
-#define PIXEL_CLK	185925
-#define PIXEL_FMT	IPU_PIX_FMT_RGB666
-#define H_START_WIDTH	9		/* left_margin */
-#define H_SYNC_WIDTH	1		/* hsync_len */
-#define H_END_WIDTH	(16 + 1)	/* right_margin + hsync_len */
-#define V_START_WIDTH	7		/* upper_margin */
-#define V_SYNC_WIDTH	1		/* vsync_len */
-#define V_END_WIDTH	(9 + 1)		/* lower_margin + vsync_len */
-#define SIG_POL		(DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
-#define IF_CONF		0
-#define IF_CLK_DIV	0x175
-#endif
-
-#define LCD_COLOR_IPU	LCD_COLOR16
 
-static ushort colormap[256];
-
-vidinfo_t panel_info = {
-	.vl_col		= XRES,
-	.vl_row		= YRES,
-	.vl_bpix	= LCD_COLOR_IPU,
-	.cmap		= colormap,
-};
-
-#define BIT_PER_PIXEL	NBITS(LCD_COLOR_IPU)
+/* -------------- controller specific stuff -------------- */
 
 /* IPU DMA Controller channel definitions. */
 enum ipu_channel {
@@ -438,89 +360,134 @@ union chan_param_mem {
 	struct chan_param_mem_interleaved	ip;
 };
 
-static inline u32 reg_read(unsigned long reg)
-{
-	return __REG(reg);
-}
+DECLARE_GLOBAL_DATA_PTR;
 
-static inline void reg_write(u32 value, unsigned long reg)
-{
-	__REG(reg) = value;
-}
+/* graphics setup */
+static GraphicDevice panel;
+static struct ctfb_res_modes *mode;
+static struct ctfb_res_modes var_mode;
 
 /*
  * sdc_init_panel() - initialize a synchronous LCD panel.
  * @width:		width of panel in pixels.
  * @height:		height of panel in pixels.
- * @pixel_fmt:		pixel format of buffer as FOURCC ASCII code.
+ * @di_setup:	pixel format of the frame buffer
+ * @di_panel:	either SHARP or normal TFT
  * @return:		0 on success or negative error code on failure.
  */
-static int sdc_init_panel(u16 width, u16 height, enum pixel_fmt pixel_fmt)
+static int sdc_init_panel(u16 width, u16 height,
+		enum pixel_fmt di_setup, enum ipu_panel di_panel)
 {
-	u32 reg;
+	u32 reg, div;
 	uint32_t old_conf;
+	int clock;
+
+	debug("%s(width=%d, height=%d)\n", __func__, width, height);
+
+	/* Init clocking, the IPU receives its clock from the hsp divder */
+	clock = mxc_get_clock(MXC_IPU_CLK);
+	if (clock < 0)
+		return -EACCES;
 
 	/* Init panel size and blanking periods */
-	reg = ((H_SYNC_WIDTH - 1) << 26) |
-		((u32)(width + H_START_WIDTH + H_END_WIDTH - 1) << 16);
-	reg_write(reg, SDC_HOR_CONF);
+	reg = width + mode->left_margin + mode->right_margin - 1;
+	if (reg > 1023) {
+		printf("mx3fb: Display width too large, coerced to 1023!");
+		reg = 1023;
+	}
+	reg = ((mode->hsync_len - 1) << 26) | (reg << 16);
+	writel(reg, SDC_HOR_CONF);
 
-	reg = ((V_SYNC_WIDTH - 1) << 26) | SDC_V_SYNC_WIDTH_L |
-		((u32)(height + V_START_WIDTH + V_END_WIDTH - 1) << 16);
-	reg_write(reg, SDC_VER_CONF);
+	reg = height + mode->upper_margin + mode->lower_margin - 1;
+	if (reg > 1023) {
+		printf("mx3fb: Display height too large, coerced to 1023!");
+		reg = 1023;
+	}
+	reg = ((mode->vsync_len - 1) << 26) | SDC_V_SYNC_WIDTH_L | (reg << 16);
+	writel(reg, SDC_VER_CONF);
 
-	switch (PANEL_TYPE) {
+	switch (di_panel) {
 	case IPU_PANEL_SHARP_TFT:
-		reg_write(0x00FD0102L, SDC_SHARP_CONF_1);
-		reg_write(0x00F500F4L, SDC_SHARP_CONF_2);
-		reg_write(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
+		writel(0x00FD0102L, SDC_SHARP_CONF_1);
+		writel(0x00F500F4L, SDC_SHARP_CONF_2);
+		writel(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
+		/* TODO: probably IF_CONF must be adapted (see below)! */
 		break;
 	case IPU_PANEL_TFT:
-		reg_write(SDC_COM_TFT_COLOR, SDC_COM_CONF);
+		writel(SDC_COM_TFT_COLOR, SDC_COM_CONF);
 		break;
 	default:
 		return -EINVAL;
 	}
 
-	/* Init clocking */
-
 	/*
-	 * Calculate divider: fractional part is 4 bits so simply multiple by
-	 * 2^4 to get fractional part, as long as we stay under ~250MHz and on
-	 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
+	 * Calculate divider: The fractional part is 4 bits so simply
+	 * multiple by 2^4 to get it.
+	 *
+	 * Opposed to the kernel driver mode->pixclock is the time of one
+	 * pixel in pico seconds, so:
+	 *		pixel_clk = 1e12 / mode->pixclock
+	 *		div = ipu_clk * 16 / pixel_clk
+	 * leads to:
+	 *		div = ipu_clk * 16 / (1e12 / mode->pixclock)
+	 * or:
+	 *		div = ipu_clk * 16 * mode->pixclock / 1e12
+	 *
+	 * To avoid integer overflows this is split into 2 shifts and
+	 * one divide with sufficient accuracy:
+	 *		16*1024*128*476837 =  0.9999996682e12
 	 */
+	div = ((clock/1024) * (mode->pixclock/128)) / 476837;
+	debug("hsp_clk is %d, div=%d\n", clock, div);
+	/* coerce to not less than 4.0, not more than 255.9375 */
+	if (div < 0x40)
+		div = 0x40;
+	else if (div > 0xFFF)
+		div = 0xFFF;
+	/* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less
+	 * fraction bits. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR
+	 * based on timing debug DISP3_IF_CLK_UP_WR is 0
+	 */
+	writel((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
 
-	reg_write((((IF_CLK_DIV / 8) - 1) << 22) |
-			IF_CLK_DIV, DI_DISP3_TIME_CONF);
+	/* DI settings for display 3: clock idle (bit 26) during vsync */
+	old_conf = readl(DI_DISP_IF_CONF) & 0x78FFFFFF;
+	writel(old_conf | IF_CONF, DI_DISP_IF_CONF);
 
-	/* DI settings */
-	old_conf = reg_read(DI_DISP_IF_CONF) & 0x78FFFFFF;
-	reg_write(old_conf | IF_CONF, DI_DISP_IF_CONF);
+	/* only set display 3 polarity bits */
+	old_conf = readl(DI_DISP_SIG_POL) & 0xE0FFFFFF;
+	writel(old_conf | mode->sync, DI_DISP_SIG_POL);
 
-	old_conf = reg_read(DI_DISP_SIG_POL) & 0xE0FFFFFF;
-	reg_write(old_conf | SIG_POL, DI_DISP_SIG_POL);
+	writel(fmt_cfg[di_setup].b0, DI_DISP3_B0_MAP);
+	writel(fmt_cfg[di_setup].b1, DI_DISP3_B1_MAP);
+	writel(fmt_cfg[di_setup].b2, DI_DISP3_B2_MAP);
+	writel(readl(DI_DISP_ACC_CC) |
+		  ((fmt_cfg[di_setup].acc - 1) << 12), DI_DISP_ACC_CC);
 
-	reg_write(fmt_cfg[pixel_fmt].b0, DI_DISP3_B0_MAP);
-	reg_write(fmt_cfg[pixel_fmt].b1, DI_DISP3_B1_MAP);
-	reg_write(fmt_cfg[pixel_fmt].b2, DI_DISP3_B2_MAP);
-	reg_write(reg_read(DI_DISP_ACC_CC) |
-		  ((fmt_cfg[pixel_fmt].acc - 1) << 12), DI_DISP_ACC_CC);
+	debug("DI_DISP_IF_CONF = 0x%08X\n",	readl(DI_DISP_IF_CONF));
+	debug("DI_DISP_SIG_POL = 0x%08X\n", readl(DI_DISP_SIG_POL));
+	debug("DI_DISP3_TIME_CONF = 0x%08X\n", readl(DI_DISP3_TIME_CONF));
+	debug("SDC_HOR_CONF = 0x%08X\n", readl(SDC_HOR_CONF));
+	debug("SDC_VER_CONF = 0x%08X\n", readl(SDC_VER_CONF));
 
 	return 0;
 }
 
 static void ipu_ch_param_set_size(union chan_param_mem *params,
-				  uint32_t pixel_fmt, uint16_t width,
+				  uint pixelfmt, uint16_t width,
 				  uint16_t height, uint16_t stride)
 {
+	debug("%s(pixelfmt=%d, width=%d, height=%d, stride=%d)\n",
+			__func__, pixelfmt, width, height, stride);
+
 	params->pp.fw		= width - 1;
 	params->pp.fh_l		= height - 1;
 	params->pp.fh_h		= (height - 1) >> 8;
 	params->pp.sl		= stride - 1;
 
 	/* See above, for further formats see the Linux driver */
-	switch (pixel_fmt) {
-	case IPU_PIX_FMT_RGB565:
+	switch (pixelfmt) {
+	case GDF_16BIT_565RGB:
 		params->ip.bpp	= 2;
 		params->ip.pfs	= 4;
 		params->ip.npb	= 7;
@@ -533,7 +500,7 @@ static void ipu_ch_param_set_size(union chan_param_mem *params,
 		params->ip.wid1	= 5;		/* Green bit width - 1 */
 		params->ip.wid2	= 4;		/* Blue bit width - 1 */
 		break;
-	case IPU_PIX_FMT_RGB24:
+	case GDF_32BIT_X888RGB:
 		params->ip.bpp	= 1;		/* 24 BPP & RGB PFS */
 		params->ip.pfs	= 4;
 		params->ip.npb	= 7;
@@ -547,6 +514,7 @@ static void ipu_ch_param_set_size(union chan_param_mem *params,
 		params->ip.wid2	= 7;		/* Blue bit width - 1 */
 		break;
 	default:
+		printf("mx3fb: Pixel format not supported!\n");
 		break;
 	}
 
@@ -564,8 +532,8 @@ static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
 				uint32_t num_words)
 {
 	for (; num_words > 0; num_words--) {
-		reg_write(addr, IPU_IMA_ADDR);
-		reg_write(*data++, IPU_IMA_DATA);
+		writel(addr, IPU_IMA_ADDR);
+		writel(*data++, IPU_IMA_DATA);
 		addr++;
 		if ((addr & 0x7) == 5) {
 			addr &= ~0x7;	/* set to word 0 */
@@ -574,16 +542,6 @@ static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
 	}
 }
 
-static uint32_t bpp_to_pixfmt(int bpp)
-{
-	switch (bpp) {
-	case 16:
-		return IPU_PIX_FMT_RGB565;
-	default:
-		return 0;
-	}
-}
-
 static uint32_t dma_param_addr(enum ipu_channel channel)
 {
 	/* Channel Parameter Memory */
@@ -596,11 +554,13 @@ static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem)
 	uint32_t reg;
 	uint32_t stride_bytes;
 
-	stride_bytes = (XRES * ((BIT_PER_PIXEL + 7) / 8) + 3) & ~3;
+	stride_bytes = (panel.plnSizeX * panel.gdfBytesPP + 3) & ~3;
+
+	debug("%s(channel=%d, fbmem=0x%x)\n", __func__, channel, fbmem);
 
 	/* Build parameter memory data for DMA channel */
-	ipu_ch_param_set_size(&params, bpp_to_pixfmt(BIT_PER_PIXEL),
-			      XRES, YRES, stride_bytes);
+	ipu_ch_param_set_size(&params, panel.gdfIndex,
+			      panel.plnSizeX, panel.plnSizeY, stride_bytes);
 	ipu_ch_param_set_buffer(&params, fbmem, NULL);
 	params.pp.bam = 0;
 	/* Some channels (rotation) have restriction on burst length */
@@ -617,22 +577,22 @@ static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem)
 	ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)&params, 10);
 
 	/* Disable double-buffering */
-	reg = reg_read(IPU_CHA_DB_MODE_SEL);
+	reg = readl(IPU_CHA_DB_MODE_SEL);
 	reg &= ~(1UL << channel);
-	reg_write(reg, IPU_CHA_DB_MODE_SEL);
+	writel(reg, IPU_CHA_DB_MODE_SEL);
 }
 
 static void ipu_channel_set_priority(enum ipu_channel channel,
 				     int prio)
 {
-	u32 reg = reg_read(IDMAC_CHA_PRI);
+	u32 reg = readl(IDMAC_CHA_PRI);
 
 	if (prio)
 		reg |= 1UL << channel;
 	else
 		reg &= ~(1UL << channel);
 
-	reg_write(reg, IDMAC_CHA_PRI);
+	writel(reg, IDMAC_CHA_PRI);
 }
 
 /*
@@ -645,7 +605,7 @@ static int ipu_enable_channel(enum ipu_channel channel)
 	uint32_t reg;
 
 	/* Reset to buffer 0 */
-	reg_write(1UL << channel, IPU_CHA_CUR_BUF);
+	writel(1UL << channel, IPU_CHA_CUR_BUF);
 
 	switch (channel) {
 	case IDMAC_SDC_0:
@@ -655,8 +615,8 @@ static int ipu_enable_channel(enum ipu_channel channel)
 		break;
 	}
 
-	reg = reg_read(IDMAC_CHA_EN);
-	reg_write(reg | (1UL << channel), IDMAC_CHA_EN);
+	reg = readl(IDMAC_CHA_EN);
+	writel(reg | (1UL << channel), IDMAC_CHA_EN);
 
 	return 0;
 }
@@ -665,13 +625,13 @@ static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf)
 {
 	uint32_t reg;
 
-	reg = reg_read(IPU_CHA_BUF0_RDY);
+	reg = readl(IPU_CHA_BUF0_RDY);
 	if (reg & (1UL << channel))
 		return -EACCES;
 
 	/* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
-	reg_write(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR);
-	reg_write((u32)buf, IPU_IMA_DATA);
+	writel(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR);
+	writel((u32)buf, IPU_IMA_DATA);
 
 	return 0;
 }
@@ -690,7 +650,7 @@ static int idmac_tx_submit(enum ipu_channel channel, void *buf)
 
 	/* ipu_idmac.c::ipu_select_buffer() */
 	/* Mark buffer 0 as ready. */
-	reg_write(1UL << channel, IPU_CHA_BUF0_RDY);
+	writel(1UL << channel, IPU_CHA_BUF0_RDY);
 
 
 	ret = ipu_enable_channel(channel);
@@ -706,8 +666,8 @@ static void sdc_enable_channel(void *fbmem)
 
 	/* mx3fb.c::sdc_fb_init() */
 	if (ret >= 0) {
-		reg = reg_read(SDC_COM_CONF);
-		reg_write(reg | SDC_COM_BG_EN, SDC_COM_CONF);
+		reg = readl(SDC_COM_CONF);
+		writel(reg | SDC_COM_BG_EN, SDC_COM_CONF);
 	}
 
 	/*
@@ -715,31 +675,33 @@ static void sdc_enable_channel(void *fbmem)
 	 * interrupts. Next sdc_set_brightness() is going to be called
 	 * from mx3fb_blank().
 	 */
-	msleep(2);
+	udelay(2000);
 }
 
 /*
  * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
  * @return:	0 on success or negative error code on failure.
+ *  TODO: currently only 666 and TFT as DI setup supported
  */
 static int mx3fb_set_par(void)
 {
 	int ret;
 
-	ret = sdc_init_panel(XRES, YRES, PIXEL_FMT);
+	ret = sdc_init_panel(panel.plnSizeX, panel.plnSizeY,
+			IPU_PIX_FMT_RGB666, IPU_PANEL_TFT);
 	if (ret < 0)
 		return ret;
 
-	reg_write((H_START_WIDTH << 16) | V_START_WIDTH, SDC_BG_POS);
+	writel((mode->left_margin << 16) | mode->upper_margin, SDC_BG_POS);
 
 	return 0;
 }
 
-/* References in this function refer to respective Linux kernel sources */
-void lcd_enable(void)
+static void ll_disp3_enable(void *base)
 {
 	u32 reg;
 
+	debug("%s(base=0x%x)\n", __func__, (u32) base);
 	/* pcm037.c::mxc_board_init() */
 
 	/* Display Interface #3 */
@@ -780,78 +742,181 @@ void lcd_enable(void)
 	/* ipu_idmac.c::ipu_idmac_init() */
 
 	/* Service request counter to maximum - shouldn't be needed */
-	reg_write(0x00000070, IDMAC_CONF);
+	writel(0x00000070, IDMAC_CONF);
 
 
 	/* ipu_idmac.c::ipu_init_channel() */
 
 	/* Enable IPU sub modules */
-	reg = reg_read(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
-	reg_write(reg, IPU_CONF);
+	reg = readl(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
+	writel(reg, IPU_CONF);
 
 
 	/* mx3fb.c::init_fb_chan() */
 
 	/* set Display Interface clock period */
-	reg_write(0x00100010L, DI_HSP_CLK_PER);
+	writel(0x00100010L, DI_HSP_CLK_PER);
 	/* Might need to trigger HSP clock change - see 44.3.3.8.5 */
 
 
 	/* mx3fb.c::sdc_set_brightness() */
 
 	/* This might be board-specific */
-	reg_write(0x03000000UL | 255 << 16, SDC_PWM_CTRL);
+	writel(0x03000000UL | 255 << 16, SDC_PWM_CTRL);
 
 
 	/* mx3fb.c::sdc_set_global_alpha() */
 
 	/* Use global - not per-pixel - Alpha-blending */
-	reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL;
-	reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL);
+	reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL;
+	writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL);
 
-	reg = reg_read(SDC_COM_CONF);
-	reg_write(reg | SDC_COM_GLB_A, SDC_COM_CONF);
+	reg = readl(SDC_COM_CONF);
+	writel(reg | SDC_COM_GLB_A, SDC_COM_CONF);
 
 
 	/* mx3fb.c::sdc_set_color_key() */
 
 	/* Disable colour-keying for background */
-	reg = reg_read(SDC_COM_CONF) &
+	reg = readl(SDC_COM_CONF) &
 		~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G);
-	reg_write(reg, SDC_COM_CONF);
+	writel(reg, SDC_COM_CONF);
 
 
 	mx3fb_set_par();
 
-	sdc_enable_channel(lcd_base);
+	sdc_enable_channel(base);
 
 	/*
 	 * Linux driver calls sdc_set_brightness() here again,
 	 * once is enough for us
 	 */
+	debug("%s() done\n", __func__);
 }
 
-void lcd_ctrl_init(void *lcdbase)
+/* ------------------------ public part ------------------- */
+ulong calc_fbsize(void)
 {
-	u32 mem_len = XRES * YRES * BIT_PER_PIXEL / 8;
-	/*
-	 * We rely on lcdbase being a physical address, i.e., either MMU off,
-	 * or 1-to-1 mapping. Might want to add some virt2phys here.
-	 */
-	if (!lcdbase)
-		return;
-
-	memset(lcdbase, 0, mem_len);
+	return panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP;
 }
 
-ulong calc_fbsize(void)
+/*
+ * The current implementation is only tested for GDF_16BIT_565RGB!
+ * It was switched from the original CONFIG_LCD setup to CONFIG_VIDEO,
+ * because the lcd code seemed loaded with color table stuff, that
+ * does not relate to most modern TFTs. cfb_console.c looks more
+ * straight forward.
+ * This is the environment setting for the original setup
+ *	"unknown=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17,
+ *		up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0"
+ *	"videomode=unknown"
+ */
+void *video_hw_init(void)
 {
-	return ((panel_info.vl_col * panel_info.vl_row *
-		NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
+	char *penv;
+	u32 memsize;
+	unsigned long t1, hsynch, vsynch;
+	int bits_per_pixel, i, tmp, vesa_idx = 0, videomode;
+
+	tmp = 0;
+
+	videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
+	/* get video mode via environment */
+	penv = getenv("videomode");
+	if (penv) {
+		/* decide if it is a string */
+		if (penv[0] <= '9') {
+			videomode = (int) simple_strtoul(penv, NULL, 16);
+			tmp = 1;
+		}
+	} else {
+		tmp = 1;
+	}
+	if (tmp) {
+		/* parameter are vesa modes */
+		/* search params */
+		for (i = 0; i < VESA_MODES_COUNT; i++) {
+			if (vesa_modes[i].vesanr == videomode)
+				break;
+		}
+		if (i == VESA_MODES_COUNT) {
+			printf("No VESA Mode found, switching to mode 0x%x ",
+					CONFIG_SYS_DEFAULT_VIDEO_MODE);
+			i = 0;
+		}
+		mode = (struct ctfb_res_modes *)
+				&res_mode_init[vesa_modes[i].resindex];
+		bits_per_pixel = vesa_modes[i].bits_per_pixel;
+		vesa_idx = vesa_modes[i].resindex;
+	} else {
+		mode = (struct ctfb_res_modes *) &var_mode;
+		bits_per_pixel = video_get_params(mode, penv);
+	}
+
+	/* calculate hsynch and vsynch freq (info only) */
+	t1 = (mode->left_margin + mode->xres +
+	      mode->right_margin + mode->hsync_len) / 8;
+	t1 *= 8;
+	t1 *= mode->pixclock;
+	t1 /= 1000;
+	hsynch = 1000000000L / t1;
+	t1 *= (mode->upper_margin + mode->yres +
+	       mode->lower_margin + mode->vsync_len);
+	t1 /= 1000;
+	vsynch = 1000000000L / t1;
+
+	/* fill in Graphic device struct */
+	sprintf(panel.modeIdent, "%dx%dx%d %ldkHz %ldHz",
+			mode->xres, mode->yres,
+			bits_per_pixel, (hsynch / 1000), (vsynch / 1000));
+	printf("%s\n", panel.modeIdent);
+	panel.winSizeX = mode->xres;
+	panel.winSizeY = mode->yres;
+	panel.plnSizeX = mode->xres;
+	panel.plnSizeY = mode->yres;
+
+	switch (bits_per_pixel) {
+	case 24:
+		panel.gdfBytesPP = 4;
+		panel.gdfIndex = GDF_32BIT_X888RGB;
+		break;
+	case 16:
+		panel.gdfBytesPP = 2;
+		panel.gdfIndex = GDF_16BIT_565RGB;
+		break;
+	default:
+		panel.gdfBytesPP = 1;
+		panel.gdfIndex = GDF__8BIT_INDEX;
+		break;
+	}
+
+	/* set up Hardware */
+	memsize = calc_fbsize();
+
+	debug("%s() allocating %d bytes\n", __func__, memsize);
+
+	/* fill in missing Graphic device struct */
+	panel.frameAdrs = (u32) malloc(memsize);
+	if (panel.frameAdrs == 0) {
+		printf("%s() malloc(%d) failed\n", __func__, memsize);
+		return 0;
+	}
+	panel.memSize = memsize;
+
+	ll_disp3_enable((void *) panel.frameAdrs);
+	memset((void *) panel.frameAdrs, 0, memsize);
+
+	debug("%s() done, framebuffer at 0x%x, size=%d cleared\n",
+			__func__, panel.frameAdrs, memsize);
+
+	return (void *) &panel;
 }
 
-int overwrite_console(void)
+void video_set_lut(unsigned int index,	/* color number */
+		    unsigned char r,	/* red */
+		    unsigned char g,	/* green */
+		    unsigned char b	/* blue */
+		    )
 {
-	/* Keep stdout / stderr on serial, our LCD is for splashscreen only */
-	return 1;
+	return;
 }
-- 
1.7.4.4



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[U-Boot] [PATCH 1/2] mx31: make HSP clock for mx3fb driver available

[Marek Vasut]

On Monday, September 05, 2011 01:47:06 PM Helmut Raiger wrote:
> This additionally updates mx31/generic.c by
> - replacing __REG() macro accesses with readl() and writel()
> - providing macros for PDR0 and PLL bit accesses
> It also fixes a warning about the prototype of imx_get_uartclk(void)
> 
> Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
> ---
> V2: uses macros and readl(), writel(), see commit message

This looks awesome. Please, when submitting V2, also add V2 to [PATCH 1/2] ... 
like [PATCH V2 1/2]. Minor thing though.

Acked-by: Marek Vasut <marek.vasut@gmail.com>

[U-Boot] [PATCH 2/2] Moving mx3fb.c to CONFIG_VIDEO

[Stefano Babic]

On 09/05/2011 01:47 PM, Helmut Raiger wrote:
> mx3fb.c was based on CONFIG_LCD and is moved by this patch to
> CONFIG_VIDEO, which has greater freedom in selecting videomodes
> even at runtime.
> 

Hi Anatolji,

do you have some comments about this patch ? Is it ok for you if I put
it in my IMX queue ? The driver is for iMX-only, and I would check if
everything remains consistent.

Thanks,
Stefano

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Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 2/2] Moving mx3fb.c to CONFIG_VIDEO

[Anatolij Gustschin]

Hi Stefano, Helmut,

On Tue, 20 Sep 2011 13:44:33 +0200
Stefano Babic <sbabic@denx.de> wrote:

> On 09/05/2011 01:47 PM, Helmut Raiger wrote:
> > mx3fb.c was based on CONFIG_LCD and is moved by this patch to
> > CONFIG_VIDEO, which has greater freedom in selecting videomodes
> > even at runtime.
> > 
> 
> Hi Anatolji,
> 
> do you have some comments about this patch ? Is it ok for you if I put
> it in my IMX queue ? The driver is for iMX-only, and I would check if
> everything remains consistent.

I'm not really ok with it as is. Currently we have video support for
two boards in the tree using the mx3fb driver. Applying this patch
as is will break the display support for qong and imx31_phycore.
I'd prefer a patch fixing this, also e.g. fixing the defines in the
affected board config files and adding the display configuration
environment variables to CONFIG_EXTRA_ENV_SETTINGS.

Currently I do not have access to the imx31 boards to test/fix this.
Stefano, can you test this patch on qong board to ensure that at
least on one board the display support is working with changed
mx3fb driver?

Best regards,
Anatolij

--
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH 2/2] Moving mx3fb.c to CONFIG_VIDEO

[Stefano Babic]

On 09/20/2011 02:36 PM, Anatolij Gustschin wrote:
> Hi Stefano, Helmut,
> 

Hi Anatolij,

> I'm not really ok with it as is. Currently we have video support for
> two boards in the tree using the mx3fb driver. Applying this patch
> as is will break the display support for qong and imx31_phycore.
> I'd prefer a patch fixing this, also e.g. fixing the defines in the
> affected board config files and adding the display configuration
> environment variables to CONFIG_EXTRA_ENV_SETTINGS.
> 
> Currently I do not have access to the imx31 boards to test/fix this.
> Stefano, can you test this patch on qong board to ensure that at
> least on one board the display support is working with changed
> mx3fb driver?

I tried, I cannot. We have not the LCD anymore for the QONG board ;-((
I have patched the QONG for fixing the build, but I cannot test it.

Best regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 2/2] Moving mx3fb.c to CONFIG_VIDEO

[Helmut Raiger]

On 09/20/2011 03:09 PM, Stefano Babic wrote:
> I tried, I cannot. We have not the LCD anymore for the QONG board ;-((
> I have patched the QONG for fixing the build, but I cannot test it.
>
> Best regards,
> Stefano

I don't really know how to address this, but what if we simply insert a 
compile time warning into these board supports, like: "warning: Display 
setup defined, but settings not tested!".

Helmut


--
Scanned by MailScanner.

[U-Boot] [PATCH 2/2] Moving mx3fb.c to CONFIG_VIDEO

[Stefano Babic]

On 09/21/2011 10:02 AM, Helmut Raiger wrote:
> On 09/20/2011 03:09 PM, Stefano Babic wrote:
>> I tried, I cannot. We have not the LCD anymore for the QONG board ;-((
>> I have patched the QONG for fixing the build, but I cannot test it.
>>
>> Best regards,
>> Stefano
> 
> I don't really know how to address this, but what if we simply insert a
> compile time warning into these board supports, like: "warning: Display
> setup defined, but settings not tested!".
> 

I have nothing against this...it seems at the moment your board is the
only one doing something with the framebuffer. We will not get a QONG
with display, and the other one (imx31_phycore) has no maintainer
anymore and is one of the orphaned boards.

Best regards,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH 2/2] Moving mx3fb.c to CONFIG_VIDEO

[Anatolij Gustschin]

On Tue, 20 Sep 2011 15:09:19 +0200
Stefano Babic <sbabic@denx.de> wrote:
> Hi Anatolij,

Hi Stefano,

> > I'm not really ok with it as is. Currently we have video support for
> > two boards in the tree using the mx3fb driver. Applying this patch
> > as is will break the display support for qong and imx31_phycore.
> > I'd prefer a patch fixing this, also e.g. fixing the defines in the
> > affected board config files and adding the display configuration
> > environment variables to CONFIG_EXTRA_ENV_SETTINGS.
> > 
> > Currently I do not have access to the imx31 boards to test/fix this.
> > Stefano, can you test this patch on qong board to ensure that at
> > least on one board the display support is working with changed
> > mx3fb driver?
> 
> I tried, I cannot. We have not the LCD anymore for the QONG board ;-((
> I have patched the QONG for fixing the build, but I cannot test it.

now I see that we have a 240x320 display for pcm037 board in the lab.
The display works in Linux, but doesn't seem to work in u-boot, still
do not know were the issue is, I've just tested it with v2011.09-rc2.
I'll try to test the patch on the imx31_phycore board with our
display this week.

Thanks,
Anatolij

--
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH v3 1/2] mx31: make HSP clock for mx3fb driver available

[Anatolij Gustschin]

From: Helmut Raiger <helmut.raiger@hale.at>

This additionally updates mx31/generic.c by
- replacing __REG() macro accesses with readl() and writel()
- providing macros for PDR0 and PLL bit accesses

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Acked-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes since v2:
 - rebased to apply on current top of tree

 arch/arm/cpu/arm1136/mx31/generic.c       |   40 +++++++++++++++++++---------
 arch/arm/include/asm/arch-mx31/clock.h    |    1 +
 arch/arm/include/asm/arch-mx31/imx-regs.h |   14 ++++++++++
 3 files changed, 42 insertions(+), 13 deletions(-)

diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index c6def5d..5524b23 100644
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -28,10 +28,10 @@
 
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
-	u32 mfi = (reg >> 10) & 0xf;
-	u32 mfn = reg & 0x3ff;
-	u32 mfd = (reg >> 16) & 0x3ff;
-	u32 pd =  (reg >> 26) & 0xf;
+	u32 mfi = GET_PLL_MFI(reg);
+	u32 mfn = GET_PLL_MFN(reg);
+	u32 mfd = GET_PLL_MFD(reg);
+	u32 pd =  GET_PLL_PD(reg);
 
 	mfi = mfi <= 5 ? 5 : mfi;
 	mfd += 1;
@@ -45,12 +45,12 @@ static u32 mx31_get_mpl_dpdgck_clk(void)
 {
 	u32 infreq;
 
-	if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
+	if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
 		infreq = CONFIG_MX31_CLK32 * 1024;
 	else
 		infreq = CONFIG_MX31_HCLK_FREQ;
 
-	return mx31_decode_pll(__REG(CCM_MPCTL), infreq);
+	return mx31_decode_pll(readl(CCM_MPCTL), infreq);
 }
 
 static u32 mx31_get_mcu_main_clk(void)
@@ -64,10 +64,21 @@ static u32 mx31_get_mcu_main_clk(void)
 static u32 mx31_get_ipg_clk(void)
 {
 	u32 freq = mx31_get_mcu_main_clk();
-	u32 pdr0 = __REG(CCM_PDR0);
+	u32 pdr0 = readl(CCM_PDR0);
 
-	freq /= ((pdr0 >> 3) & 0x7) + 1;
-	freq /= ((pdr0 >> 6) & 0x3) + 1;
+	freq /= GET_PDR0_MAX_PODF(pdr0) + 1;
+	freq /= GET_PDR0_IPG_PODF(pdr0) + 1;
+
+	return freq;
+}
+
+/* hsp is the clock for the ipu */
+static u32 mx31_get_hsp_clk(void)
+{
+	u32 freq = mx31_get_mcu_main_clk();
+	u32 pdr0 = readl(CCM_PDR0);
+
+	freq /= GET_PDR0_HSP_PODF(pdr0) + 1;
 
 	return freq;
 }
@@ -77,6 +88,7 @@ void mx31_dump_clocks(void)
 	u32 cpufreq = mx31_get_mcu_main_clk();
 	printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000);
 	printf("ipg clock     : %dHz\n", mx31_get_ipg_clk());
+	printf("hsp clock     : %dHz\n", mx31_get_hsp_clk());
 }
 
 unsigned int mxc_get_clock(enum mxc_clock clk)
@@ -89,6 +101,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk)
 	case MXC_CSPI_CLK:
 	case MXC_UART_CLK:
 		return mx31_get_ipg_clk();
+	case MXC_IPU_CLK:
+		return mx31_get_hsp_clk();
 	}
 	return -1;
 }
@@ -105,10 +119,10 @@ void mx31_gpio_mux(unsigned long mode)
 	reg = IOMUXC_BASE + (mode & 0x1fc);
 	shift = (~mode & 0x3) * 8;
 
-	tmp = __REG(reg);
+	tmp = readl(reg);
 	tmp &= ~(0xff << shift);
 	tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
-	__REG(reg) = tmp;
+	writel(tmp, reg);
 }
 
 void mx31_set_pad(enum iomux_pins pin, u32 config)
@@ -119,10 +133,10 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
 	reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
 	field = (pin + 2) % 3;
 
-	l = __REG(reg);
+	l = readl(reg);
 	l &= ~(0x1ff << (field * 10));
 	l |= config << (field * 10);
-	__REG(reg) = l;
+	writel(l, reg);
 
 }
 
diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h
index cc99a75..2e3bce2 100644
--- a/arch/arm/include/asm/arch-mx31/clock.h
+++ b/arch/arm/include/asm/arch-mx31/clock.h
@@ -30,6 +30,7 @@ enum mxc_clock {
 	MXC_IPG_PERCLK,
 	MXC_CSPI_CLK,
 	MXC_UART_CLK,
+	MXC_IPU_CLK
 };
 
 unsigned int mxc_get_clock(enum mxc_clock clk);
diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 0dcd9fe..f263e6b 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -513,6 +513,20 @@ enum iomux_pins {
 #define PLL_MFI(x)		(((x) & 0xf) << 10)
 #define PLL_MFN(x)		(((x) & 0x3ff) << 0)
 
+#define GET_PDR0_CSI_PODF(x)	(((x) >> 23) & 0x1ff)
+#define GET_PDR0_PER_PODF(x)	(((x) >> 16) & 0x1f)
+#define GET_PDR0_HSP_PODF(x)	(((x) >> 11) & 0x7)
+#define GET_PDR0_NFC_PODF(x)	(((x) >> 8) & 0x7)
+#define GET_PDR0_IPG_PODF(x)	(((x) >> 6) & 0x3)
+#define GET_PDR0_MAX_PODF(x)	(((x) >> 3) & 0x7)
+#define GET_PDR0_MCU_PODF(x)	((x) & 0x7)
+
+#define GET_PLL_PD(x)		(((x) >> 26) & 0xf)
+#define GET_PLL_MFD(x)		(((x) >> 16) & 0x3ff)
+#define GET_PLL_MFI(x)		(((x) >> 10) & 0xf)
+#define GET_PLL_MFN(x)		(((x) >> 0) & 0x3ff)
+
+
 #define WEIM_ESDCTL0	0xB8001000
 #define WEIM_ESDCFG0	0xB8001004
 #define WEIM_ESDCTL1	0xB8001008
-- 
1.7.1

[U-Boot] [PATCH v3 2/2] video: Moving mx3fb.c to CONFIG_VIDEO

[Anatolij Gustschin]

From: Helmut Raiger <helmut.raiger@hale.at>

mx3fb.c was based on CONFIG_LCD and is moved by this patch to
CONFIG_VIDEO, which has greater freedom in selecting videomodes
even at runtime.

This renders the accumulating list of display defines
(CONFIG_DISPLAY_VBEST..., CONFIG_DISPLAY_C057...) obsolete as
these may be setup through env variables:

uboot> setenv mydisplay 'video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,
	le:9,ri:17,up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0'
uboot> setenv videomode ${mydisplay}

This commit also fixes the board config files for qong and
imx31_phycore boards as needed. The videomode settings of
previously supported displays are added to CONFIG_EXTRA_ENV_SETTINGS
now. CONFIG_SYS_MALLOC_LEN for imx31_phycore board is increased
to make the frame buffer allocation working with the changed
driver.

Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
Signed-off-by: Anatolij Gustschin <agust@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
---
Changes since v2:
 - fixed commit message
 - added display info for removed display timings of
   previously supported displays (in a comment)
 - fixed compiler warning showed when compiling with debug
   enabled
 - added "Video: " prefix before display info output (as
   we usually do it in U-Boot)
 - fixed board config files for 'qong' and 'imx31_phycore' boards
   so that this commit doesn't break compiling (bisectable now)
 - added videomode settings for previously supported displays on
   'qong' and 'imx31_phycore' to CONFIG_EXTRA_ENV_SETTINGS
 - increased CONFIG_SYS_MALLOC_LEN for 'imx31_phycore' so that
   the frame buffer can be allocated now (this is required to make
   the display support working with the changed mx3fb driver)

 drivers/video/Makefile          |    2 +-
 drivers/video/cfb_console.c     |    7 +
 drivers/video/mx3fb.c           |  459 +++++++++++++++++++++++----------------
 include/configs/imx31_phycore.h |   24 +-
 include/configs/qong.h          |   14 +-
 5 files changed, 297 insertions(+), 209 deletions(-)

diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 3790f91..ecc1896 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -35,7 +35,7 @@ COBJS-$(CONFIG_VIDEO_AMBA) += amba.o
 COBJS-$(CONFIG_VIDEO_CT69000) += ct69000.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o
-COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o
+COBJS-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
 COBJS-$(CONFIG_VIDEO_MX5) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o
 COBJS-$(CONFIG_VIDEO_OMAP3) += omap3_dss.o videomodes.o
 COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c
index 3a93b64..4e653b8 100644
--- a/drivers/video/cfb_console.c
+++ b/drivers/video/cfb_console.c
@@ -161,6 +161,13 @@
 #endif
 
 /*
+ * Defines for the i.MX31 driver (mx3fb.c)
+ */
+#ifdef CONFIG_VIDEO_MX3
+#define VIDEO_FB_16BPP_WORD_SWAP
+#endif
+
+/*
  * Include video_fb.h after definitions of VIDEO_HW_RECTFILL etc.
  */
 #include <video_fb.h>
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c
index 0c925a0..f30deb3 100644
--- a/drivers/video/mx3fb.c
+++ b/drivers/video/mx3fb.c
@@ -1,6 +1,8 @@
 /*
  * Copyright (C) 2009
  * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ * Copyright (C) 2011
+ * HALE electronic GmbH, <helmut.raiger@hale.at>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -21,100 +23,20 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
-#include <lcd.h>
-#include <asm/arch/clock.h>
+#include <malloc.h>
+#include <video_fb.h>
+
 #include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
 #include <asm/errno.h>
+#include <asm/io.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
-void *lcd_base;			/* Start of framebuffer memory	*/
-void *lcd_console_address;	/* Start of console buffer	*/
-
-int lcd_line_length;
-int lcd_color_fg;
-int lcd_color_bg;
-
-short console_col;
-short console_row;
-
-void lcd_initcolregs(void)
-{
-}
-
-void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue)
-{
-}
-
-void lcd_disable(void)
-{
-}
-
-void lcd_panel_disable(void)
-{
-}
+#include "videomodes.h"
 
-#define msleep(a) udelay(a * 1000)
-
-#if defined(CONFIG_DISPLAY_VBEST_VGG322403)
-#define XRES		320
-#define YRES		240
-#define PANEL_TYPE	IPU_PANEL_TFT
-#define PIXEL_CLK	156000
-#define PIXEL_FMT	IPU_PIX_FMT_RGB666
-#define H_START_WIDTH	20		/* left_margin */
-#define H_SYNC_WIDTH	30		/* hsync_len */
-#define H_END_WIDTH	(38 + 30)	/* right_margin + hsync_len */
-#define V_START_WIDTH	7		/* upper_margin */
-#define V_SYNC_WIDTH	3		/* vsync_len */
-#define V_END_WIDTH	(26 + 3)	/* lower_margin + vsync_len */
-#define SIG_POL		(DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
+/* this might need panel specific set-up as-well */
 #define IF_CONF		0
-#define IF_CLK_DIV	0x175
-#elif defined(CONFIG_DISPLAY_COM57H5M10XRC)
-#define XRES		640
-#define YRES		480
-#define PANEL_TYPE	IPU_PANEL_TFT
-#define PIXEL_CLK	40000
-#define PIXEL_FMT	IPU_PIX_FMT_RGB666
-#define H_START_WIDTH	120		/* left_margin */
-#define H_SYNC_WIDTH	30		/* hsync_len */
-#define H_END_WIDTH	(10 + 30)	/* right_margin + hsync_len */
-#define V_START_WIDTH	35		/* upper_margin */
-#define V_SYNC_WIDTH	3		/* vsync_len */
-#define V_END_WIDTH	(7 + 3)	/* lower_margin + vsync_len */
-#define SIG_POL		(DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
-#define IF_CONF		0
-#define IF_CLK_DIV	0x55
-#else
-#define XRES		240
-#define YRES		320
-#define PANEL_TYPE	IPU_PANEL_TFT
-#define PIXEL_CLK	185925
-#define PIXEL_FMT	IPU_PIX_FMT_RGB666
-#define H_START_WIDTH	9		/* left_margin */
-#define H_SYNC_WIDTH	1		/* hsync_len */
-#define H_END_WIDTH	(16 + 1)	/* right_margin + hsync_len */
-#define V_START_WIDTH	7		/* upper_margin */
-#define V_SYNC_WIDTH	1		/* vsync_len */
-#define V_END_WIDTH	(9 + 1)		/* lower_margin + vsync_len */
-#define SIG_POL		(DI_D3_DRDY_SHARP_POL | DI_D3_CLK_POL)
-#define IF_CONF		0
-#define IF_CLK_DIV	0x175
-#endif
-
-#define LCD_COLOR_IPU	LCD_COLOR16
-
-static ushort colormap[256];
-
-vidinfo_t panel_info = {
-	.vl_col		= XRES,
-	.vl_row		= YRES,
-	.vl_bpix	= LCD_COLOR_IPU,
-	.cmap		= colormap,
-};
 
-#define BIT_PER_PIXEL	NBITS(LCD_COLOR_IPU)
+/* -------------- controller specific stuff -------------- */
 
 /* IPU DMA Controller channel definitions. */
 enum ipu_channel {
@@ -438,89 +360,134 @@ union chan_param_mem {
 	struct chan_param_mem_interleaved	ip;
 };
 
-static inline u32 reg_read(unsigned long reg)
-{
-	return __REG(reg);
-}
+DECLARE_GLOBAL_DATA_PTR;
 
-static inline void reg_write(u32 value, unsigned long reg)
-{
-	__REG(reg) = value;
-}
+/* graphics setup */
+static GraphicDevice panel;
+static struct ctfb_res_modes *mode;
+static struct ctfb_res_modes var_mode;
 
 /*
  * sdc_init_panel() - initialize a synchronous LCD panel.
  * @width:		width of panel in pixels.
  * @height:		height of panel in pixels.
- * @pixel_fmt:		pixel format of buffer as FOURCC ASCII code.
+ * @di_setup:	pixel format of the frame buffer
+ * @di_panel:	either SHARP or normal TFT
  * @return:		0 on success or negative error code on failure.
  */
-static int sdc_init_panel(u16 width, u16 height, enum pixel_fmt pixel_fmt)
+static int sdc_init_panel(u16 width, u16 height,
+		enum pixel_fmt di_setup, enum ipu_panel di_panel)
 {
-	u32 reg;
+	u32 reg, div;
 	uint32_t old_conf;
+	int clock;
+
+	debug("%s(width=%d, height=%d)\n", __func__, width, height);
+
+	/* Init clocking, the IPU receives its clock from the hsp divder */
+	clock = mxc_get_clock(MXC_IPU_CLK);
+	if (clock < 0)
+		return -EACCES;
 
 	/* Init panel size and blanking periods */
-	reg = ((H_SYNC_WIDTH - 1) << 26) |
-		((u32)(width + H_START_WIDTH + H_END_WIDTH - 1) << 16);
-	reg_write(reg, SDC_HOR_CONF);
+	reg = width + mode->left_margin + mode->right_margin - 1;
+	if (reg > 1023) {
+		printf("mx3fb: Display width too large, coerced to 1023!");
+		reg = 1023;
+	}
+	reg = ((mode->hsync_len - 1) << 26) | (reg << 16);
+	writel(reg, SDC_HOR_CONF);
 
-	reg = ((V_SYNC_WIDTH - 1) << 26) | SDC_V_SYNC_WIDTH_L |
-		((u32)(height + V_START_WIDTH + V_END_WIDTH - 1) << 16);
-	reg_write(reg, SDC_VER_CONF);
+	reg = height + mode->upper_margin + mode->lower_margin - 1;
+	if (reg > 1023) {
+		printf("mx3fb: Display height too large, coerced to 1023!");
+		reg = 1023;
+	}
+	reg = ((mode->vsync_len - 1) << 26) | SDC_V_SYNC_WIDTH_L | (reg << 16);
+	writel(reg, SDC_VER_CONF);
 
-	switch (PANEL_TYPE) {
+	switch (di_panel) {
 	case IPU_PANEL_SHARP_TFT:
-		reg_write(0x00FD0102L, SDC_SHARP_CONF_1);
-		reg_write(0x00F500F4L, SDC_SHARP_CONF_2);
-		reg_write(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
+		writel(0x00FD0102L, SDC_SHARP_CONF_1);
+		writel(0x00F500F4L, SDC_SHARP_CONF_2);
+		writel(SDC_COM_SHARP | SDC_COM_TFT_COLOR, SDC_COM_CONF);
+		/* TODO: probably IF_CONF must be adapted (see below)! */
 		break;
 	case IPU_PANEL_TFT:
-		reg_write(SDC_COM_TFT_COLOR, SDC_COM_CONF);
+		writel(SDC_COM_TFT_COLOR, SDC_COM_CONF);
 		break;
 	default:
 		return -EINVAL;
 	}
 
-	/* Init clocking */
-
 	/*
-	 * Calculate divider: fractional part is 4 bits so simply multiple by
-	 * 2^4 to get fractional part, as long as we stay under ~250MHz and on
-	 * i.MX31 it (HSP_CLK) is <= 178MHz. Currently 128.267MHz
+	 * Calculate divider: The fractional part is 4 bits so simply
+	 * multiple by 2^4 to get it.
+	 *
+	 * Opposed to the kernel driver mode->pixclock is the time of one
+	 * pixel in pico seconds, so:
+	 *		pixel_clk = 1e12 / mode->pixclock
+	 *		div = ipu_clk * 16 / pixel_clk
+	 * leads to:
+	 *		div = ipu_clk * 16 / (1e12 / mode->pixclock)
+	 * or:
+	 *		div = ipu_clk * 16 * mode->pixclock / 1e12
+	 *
+	 * To avoid integer overflows this is split into 2 shifts and
+	 * one divide with sufficient accuracy:
+	 *		16*1024*128*476837 =  0.9999996682e12
+	 */
+	div = ((clock/1024) * (mode->pixclock/128)) / 476837;
+	debug("hsp_clk is %d, div=%d\n", clock, div);
+	/* coerce to not less than 4.0, not more than 255.9375 */
+	if (div < 0x40)
+		div = 0x40;
+	else if (div > 0xFFF)
+		div = 0xFFF;
+	/* DISP3_IF_CLK_DOWN_WR is half the divider value and 2 less
+	 * fraction bits. Subtract 1 extra from DISP3_IF_CLK_DOWN_WR
+	 * based on timing debug DISP3_IF_CLK_UP_WR is 0
 	 */
+	writel((((div / 8) - 1) << 22) | div, DI_DISP3_TIME_CONF);
 
-	reg_write((((IF_CLK_DIV / 8) - 1) << 22) |
-			IF_CLK_DIV, DI_DISP3_TIME_CONF);
+	/* DI settings for display 3: clock idle (bit 26) during vsync */
+	old_conf = readl(DI_DISP_IF_CONF) & 0x78FFFFFF;
+	writel(old_conf | IF_CONF, DI_DISP_IF_CONF);
 
-	/* DI settings */
-	old_conf = reg_read(DI_DISP_IF_CONF) & 0x78FFFFFF;
-	reg_write(old_conf | IF_CONF, DI_DISP_IF_CONF);
+	/* only set display 3 polarity bits */
+	old_conf = readl(DI_DISP_SIG_POL) & 0xE0FFFFFF;
+	writel(old_conf | mode->sync, DI_DISP_SIG_POL);
 
-	old_conf = reg_read(DI_DISP_SIG_POL) & 0xE0FFFFFF;
-	reg_write(old_conf | SIG_POL, DI_DISP_SIG_POL);
+	writel(fmt_cfg[di_setup].b0, DI_DISP3_B0_MAP);
+	writel(fmt_cfg[di_setup].b1, DI_DISP3_B1_MAP);
+	writel(fmt_cfg[di_setup].b2, DI_DISP3_B2_MAP);
+	writel(readl(DI_DISP_ACC_CC) |
+		  ((fmt_cfg[di_setup].acc - 1) << 12), DI_DISP_ACC_CC);
 
-	reg_write(fmt_cfg[pixel_fmt].b0, DI_DISP3_B0_MAP);
-	reg_write(fmt_cfg[pixel_fmt].b1, DI_DISP3_B1_MAP);
-	reg_write(fmt_cfg[pixel_fmt].b2, DI_DISP3_B2_MAP);
-	reg_write(reg_read(DI_DISP_ACC_CC) |
-		  ((fmt_cfg[pixel_fmt].acc - 1) << 12), DI_DISP_ACC_CC);
+	debug("DI_DISP_IF_CONF = 0x%08X\n",	readl(DI_DISP_IF_CONF));
+	debug("DI_DISP_SIG_POL = 0x%08X\n", readl(DI_DISP_SIG_POL));
+	debug("DI_DISP3_TIME_CONF = 0x%08X\n", readl(DI_DISP3_TIME_CONF));
+	debug("SDC_HOR_CONF = 0x%08X\n", readl(SDC_HOR_CONF));
+	debug("SDC_VER_CONF = 0x%08X\n", readl(SDC_VER_CONF));
 
 	return 0;
 }
 
 static void ipu_ch_param_set_size(union chan_param_mem *params,
-				  uint32_t pixel_fmt, uint16_t width,
+				  uint pixelfmt, uint16_t width,
 				  uint16_t height, uint16_t stride)
 {
+	debug("%s(pixelfmt=%d, width=%d, height=%d, stride=%d)\n",
+			__func__, pixelfmt, width, height, stride);
+
 	params->pp.fw		= width - 1;
 	params->pp.fh_l		= height - 1;
 	params->pp.fh_h		= (height - 1) >> 8;
 	params->pp.sl		= stride - 1;
 
 	/* See above, for further formats see the Linux driver */
-	switch (pixel_fmt) {
-	case IPU_PIX_FMT_RGB565:
+	switch (pixelfmt) {
+	case GDF_16BIT_565RGB:
 		params->ip.bpp	= 2;
 		params->ip.pfs	= 4;
 		params->ip.npb	= 7;
@@ -533,7 +500,7 @@ static void ipu_ch_param_set_size(union chan_param_mem *params,
 		params->ip.wid1	= 5;		/* Green bit width - 1 */
 		params->ip.wid2	= 4;		/* Blue bit width - 1 */
 		break;
-	case IPU_PIX_FMT_RGB24:
+	case GDF_32BIT_X888RGB:
 		params->ip.bpp	= 1;		/* 24 BPP & RGB PFS */
 		params->ip.pfs	= 4;
 		params->ip.npb	= 7;
@@ -547,6 +514,7 @@ static void ipu_ch_param_set_size(union chan_param_mem *params,
 		params->ip.wid2	= 7;		/* Blue bit width - 1 */
 		break;
 	default:
+		printf("mx3fb: Pixel format not supported!\n");
 		break;
 	}
 
@@ -564,8 +532,8 @@ static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
 				uint32_t num_words)
 {
 	for (; num_words > 0; num_words--) {
-		reg_write(addr, IPU_IMA_ADDR);
-		reg_write(*data++, IPU_IMA_DATA);
+		writel(addr, IPU_IMA_ADDR);
+		writel(*data++, IPU_IMA_DATA);
 		addr++;
 		if ((addr & 0x7) == 5) {
 			addr &= ~0x7;	/* set to word 0 */
@@ -574,16 +542,6 @@ static void ipu_write_param_mem(uint32_t addr, uint32_t *data,
 	}
 }
 
-static uint32_t bpp_to_pixfmt(int bpp)
-{
-	switch (bpp) {
-	case 16:
-		return IPU_PIX_FMT_RGB565;
-	default:
-		return 0;
-	}
-}
-
 static uint32_t dma_param_addr(enum ipu_channel channel)
 {
 	/* Channel Parameter Memory */
@@ -596,11 +554,13 @@ static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem)
 	uint32_t reg;
 	uint32_t stride_bytes;
 
-	stride_bytes = (XRES * ((BIT_PER_PIXEL + 7) / 8) + 3) & ~3;
+	stride_bytes = (panel.plnSizeX * panel.gdfBytesPP + 3) & ~3;
+
+	debug("%s(channel=%d, fbmem=%p)\n", __func__, channel, fbmem);
 
 	/* Build parameter memory data for DMA channel */
-	ipu_ch_param_set_size(&params, bpp_to_pixfmt(BIT_PER_PIXEL),
-			      XRES, YRES, stride_bytes);
+	ipu_ch_param_set_size(&params, panel.gdfIndex,
+			      panel.plnSizeX, panel.plnSizeY, stride_bytes);
 	ipu_ch_param_set_buffer(&params, fbmem, NULL);
 	params.pp.bam = 0;
 	/* Some channels (rotation) have restriction on burst length */
@@ -617,22 +577,22 @@ static void ipu_init_channel_buffer(enum ipu_channel channel, void *fbmem)
 	ipu_write_param_mem(dma_param_addr(channel), (uint32_t *)&params, 10);
 
 	/* Disable double-buffering */
-	reg = reg_read(IPU_CHA_DB_MODE_SEL);
+	reg = readl(IPU_CHA_DB_MODE_SEL);
 	reg &= ~(1UL << channel);
-	reg_write(reg, IPU_CHA_DB_MODE_SEL);
+	writel(reg, IPU_CHA_DB_MODE_SEL);
 }
 
 static void ipu_channel_set_priority(enum ipu_channel channel,
 				     int prio)
 {
-	u32 reg = reg_read(IDMAC_CHA_PRI);
+	u32 reg = readl(IDMAC_CHA_PRI);
 
 	if (prio)
 		reg |= 1UL << channel;
 	else
 		reg &= ~(1UL << channel);
 
-	reg_write(reg, IDMAC_CHA_PRI);
+	writel(reg, IDMAC_CHA_PRI);
 }
 
 /*
@@ -645,7 +605,7 @@ static int ipu_enable_channel(enum ipu_channel channel)
 	uint32_t reg;
 
 	/* Reset to buffer 0 */
-	reg_write(1UL << channel, IPU_CHA_CUR_BUF);
+	writel(1UL << channel, IPU_CHA_CUR_BUF);
 
 	switch (channel) {
 	case IDMAC_SDC_0:
@@ -655,8 +615,8 @@ static int ipu_enable_channel(enum ipu_channel channel)
 		break;
 	}
 
-	reg = reg_read(IDMAC_CHA_EN);
-	reg_write(reg | (1UL << channel), IDMAC_CHA_EN);
+	reg = readl(IDMAC_CHA_EN);
+	writel(reg | (1UL << channel), IDMAC_CHA_EN);
 
 	return 0;
 }
@@ -665,13 +625,13 @@ static int ipu_update_channel_buffer(enum ipu_channel channel, void *buf)
 {
 	uint32_t reg;
 
-	reg = reg_read(IPU_CHA_BUF0_RDY);
+	reg = readl(IPU_CHA_BUF0_RDY);
 	if (reg & (1UL << channel))
 		return -EACCES;
 
 	/* 44.3.3.1.9 - Row Number 1 (WORD1, offset 0) */
-	reg_write(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR);
-	reg_write((u32)buf, IPU_IMA_DATA);
+	writel(dma_param_addr(channel) + 0x0008UL, IPU_IMA_ADDR);
+	writel((u32)buf, IPU_IMA_DATA);
 
 	return 0;
 }
@@ -690,7 +650,7 @@ static int idmac_tx_submit(enum ipu_channel channel, void *buf)
 
 	/* ipu_idmac.c::ipu_select_buffer() */
 	/* Mark buffer 0 as ready. */
-	reg_write(1UL << channel, IPU_CHA_BUF0_RDY);
+	writel(1UL << channel, IPU_CHA_BUF0_RDY);
 
 
 	ret = ipu_enable_channel(channel);
@@ -706,8 +666,8 @@ static void sdc_enable_channel(void *fbmem)
 
 	/* mx3fb.c::sdc_fb_init() */
 	if (ret >= 0) {
-		reg = reg_read(SDC_COM_CONF);
-		reg_write(reg | SDC_COM_BG_EN, SDC_COM_CONF);
+		reg = readl(SDC_COM_CONF);
+		writel(reg | SDC_COM_BG_EN, SDC_COM_CONF);
 	}
 
 	/*
@@ -715,31 +675,33 @@ static void sdc_enable_channel(void *fbmem)
 	 * interrupts. Next sdc_set_brightness() is going to be called
 	 * from mx3fb_blank().
 	 */
-	msleep(2);
+	udelay(2000);
 }
 
 /*
  * mx3fb_set_par() - set framebuffer parameters and change the operating mode.
  * @return:	0 on success or negative error code on failure.
+ *  TODO: currently only 666 and TFT as DI setup supported
  */
 static int mx3fb_set_par(void)
 {
 	int ret;
 
-	ret = sdc_init_panel(XRES, YRES, PIXEL_FMT);
+	ret = sdc_init_panel(panel.plnSizeX, panel.plnSizeY,
+			IPU_PIX_FMT_RGB666, IPU_PANEL_TFT);
 	if (ret < 0)
 		return ret;
 
-	reg_write((H_START_WIDTH << 16) | V_START_WIDTH, SDC_BG_POS);
+	writel((mode->left_margin << 16) | mode->upper_margin, SDC_BG_POS);
 
 	return 0;
 }
 
-/* References in this function refer to respective Linux kernel sources */
-void lcd_enable(void)
+static void ll_disp3_enable(void *base)
 {
 	u32 reg;
 
+	debug("%s(base=0x%x)\n", __func__, (u32) base);
 	/* pcm037.c::mxc_board_init() */
 
 	/* Display Interface #3 */
@@ -780,78 +742,191 @@ void lcd_enable(void)
 	/* ipu_idmac.c::ipu_idmac_init() */
 
 	/* Service request counter to maximum - shouldn't be needed */
-	reg_write(0x00000070, IDMAC_CONF);
+	writel(0x00000070, IDMAC_CONF);
 
 
 	/* ipu_idmac.c::ipu_init_channel() */
 
 	/* Enable IPU sub modules */
-	reg = reg_read(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
-	reg_write(reg, IPU_CONF);
+	reg = readl(IPU_CONF) | IPU_CONF_SDC_EN | IPU_CONF_DI_EN;
+	writel(reg, IPU_CONF);
 
 
 	/* mx3fb.c::init_fb_chan() */
 
 	/* set Display Interface clock period */
-	reg_write(0x00100010L, DI_HSP_CLK_PER);
+	writel(0x00100010L, DI_HSP_CLK_PER);
 	/* Might need to trigger HSP clock change - see 44.3.3.8.5 */
 
 
 	/* mx3fb.c::sdc_set_brightness() */
 
 	/* This might be board-specific */
-	reg_write(0x03000000UL | 255 << 16, SDC_PWM_CTRL);
+	writel(0x03000000UL | 255 << 16, SDC_PWM_CTRL);
 
 
 	/* mx3fb.c::sdc_set_global_alpha() */
 
 	/* Use global - not per-pixel - Alpha-blending */
-	reg = reg_read(SDC_GW_CTRL) & 0x00FFFFFFL;
-	reg_write(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL);
+	reg = readl(SDC_GW_CTRL) & 0x00FFFFFFL;
+	writel(reg | ((uint32_t) 0xff << 24), SDC_GW_CTRL);
 
-	reg = reg_read(SDC_COM_CONF);
-	reg_write(reg | SDC_COM_GLB_A, SDC_COM_CONF);
+	reg = readl(SDC_COM_CONF);
+	writel(reg | SDC_COM_GLB_A, SDC_COM_CONF);
 
 
 	/* mx3fb.c::sdc_set_color_key() */
 
 	/* Disable colour-keying for background */
-	reg = reg_read(SDC_COM_CONF) &
+	reg = readl(SDC_COM_CONF) &
 		~(SDC_COM_GWSEL | SDC_COM_KEY_COLOR_G);
-	reg_write(reg, SDC_COM_CONF);
+	writel(reg, SDC_COM_CONF);
 
 
 	mx3fb_set_par();
 
-	sdc_enable_channel(lcd_base);
+	sdc_enable_channel(base);
 
 	/*
 	 * Linux driver calls sdc_set_brightness() here again,
 	 * once is enough for us
 	 */
+	debug("%s() done\n", __func__);
 }
 
-void lcd_ctrl_init(void *lcdbase)
+/* ------------------------ public part ------------------- */
+ulong calc_fbsize(void)
 {
-	u32 mem_len = XRES * YRES * BIT_PER_PIXEL / 8;
-	/*
-	 * We rely on lcdbase being a physical address, i.e., either MMU off,
-	 * or 1-to-1 mapping. Might want to add some virt2phys here.
-	 */
-	if (!lcdbase)
-		return;
-
-	memset(lcdbase, 0, mem_len);
+	return panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP;
 }
 
-ulong calc_fbsize(void)
+/*
+ * The current implementation is only tested for GDF_16BIT_565RGB!
+ * It was switched from the original CONFIG_LCD setup to CONFIG_VIDEO,
+ * because the lcd code seemed loaded with color table stuff, that
+ * does not relate to most modern TFTs. cfb_console.c looks more
+ * straight forward.
+ * This is the environment setting for the original setup
+ *	"unknown=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17,
+ *		up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0"
+ *	"videomode=unknown"
+ *
+ * Settings for VBEST VGG322403 display:
+ *	"videomode=video=ctfb:x:320,y:240,depth:16,mode:0,pclk:156000,
+ *		"le:20,ri:68,up:7,lo:29,hs:30,vs:3,sync:100663296,vmode:0"
+ *
+ * Settings for COM57H5M10XRC display:
+ *	"videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000,
+ *		"le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,vmode:0"
+ */
+void *video_hw_init(void)
 {
-	return ((panel_info.vl_col * panel_info.vl_row *
-		NBITS(panel_info.vl_bpix)) / 8) + PAGE_SIZE;
+	char *penv;
+	u32 memsize;
+	unsigned long t1, hsynch, vsynch;
+	int bits_per_pixel, i, tmp, vesa_idx = 0, videomode;
+
+	tmp = 0;
+
+	puts("Video: ");
+
+	videomode = CONFIG_SYS_DEFAULT_VIDEO_MODE;
+	/* get video mode via environment */
+	penv = getenv("videomode");
+	if (penv) {
+		/* decide if it is a string */
+		if (penv[0] <= '9') {
+			videomode = (int) simple_strtoul(penv, NULL, 16);
+			tmp = 1;
+		}
+	} else {
+		tmp = 1;
+	}
+	if (tmp) {
+		/* parameter are vesa modes */
+		/* search params */
+		for (i = 0; i < VESA_MODES_COUNT; i++) {
+			if (vesa_modes[i].vesanr == videomode)
+				break;
+		}
+		if (i == VESA_MODES_COUNT) {
+			printf("No VESA Mode found, switching to mode 0x%x ",
+					CONFIG_SYS_DEFAULT_VIDEO_MODE);
+			i = 0;
+		}
+		mode = (struct ctfb_res_modes *)
+				&res_mode_init[vesa_modes[i].resindex];
+		bits_per_pixel = vesa_modes[i].bits_per_pixel;
+		vesa_idx = vesa_modes[i].resindex;
+	} else {
+		mode = (struct ctfb_res_modes *) &var_mode;
+		bits_per_pixel = video_get_params(mode, penv);
+	}
+
+	/* calculate hsynch and vsynch freq (info only) */
+	t1 = (mode->left_margin + mode->xres +
+	      mode->right_margin + mode->hsync_len) / 8;
+	t1 *= 8;
+	t1 *= mode->pixclock;
+	t1 /= 1000;
+	hsynch = 1000000000L / t1;
+	t1 *= (mode->upper_margin + mode->yres +
+	       mode->lower_margin + mode->vsync_len);
+	t1 /= 1000;
+	vsynch = 1000000000L / t1;
+
+	/* fill in Graphic device struct */
+	sprintf(panel.modeIdent, "%dx%dx%d %ldkHz %ldHz",
+			mode->xres, mode->yres,
+			bits_per_pixel, (hsynch / 1000), (vsynch / 1000));
+	printf("%s\n", panel.modeIdent);
+	panel.winSizeX = mode->xres;
+	panel.winSizeY = mode->yres;
+	panel.plnSizeX = mode->xres;
+	panel.plnSizeY = mode->yres;
+
+	switch (bits_per_pixel) {
+	case 24:
+		panel.gdfBytesPP = 4;
+		panel.gdfIndex = GDF_32BIT_X888RGB;
+		break;
+	case 16:
+		panel.gdfBytesPP = 2;
+		panel.gdfIndex = GDF_16BIT_565RGB;
+		break;
+	default:
+		panel.gdfBytesPP = 1;
+		panel.gdfIndex = GDF__8BIT_INDEX;
+		break;
+	}
+
+	/* set up Hardware */
+	memsize = calc_fbsize();
+
+	debug("%s() allocating %d bytes\n", __func__, memsize);
+
+	/* fill in missing Graphic device struct */
+	panel.frameAdrs = (u32) malloc(memsize);
+	if (panel.frameAdrs == 0) {
+		printf("%s() malloc(%d) failed\n", __func__, memsize);
+		return 0;
+	}
+	panel.memSize = memsize;
+
+	ll_disp3_enable((void *) panel.frameAdrs);
+	memset((void *) panel.frameAdrs, 0, memsize);
+
+	debug("%s() done, framebuffer at 0x%x, size=%d cleared\n",
+			__func__, panel.frameAdrs, memsize);
+
+	return (void *) &panel;
 }
 
-int overwrite_console(void)
+void video_set_lut(unsigned int index,	/* color number */
+		    unsigned char r,	/* red */
+		    unsigned char g,	/* green */
+		    unsigned char b	/* blue */
+		    )
 {
-	/* Keep stdout / stderr on serial, our LCD is for splashscreen only */
-	return 1;
+	return;
 }
diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index 61f0534..48bd50b 100644
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -53,7 +53,7 @@
 /*
  * Size of malloc() pool
  */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 512 * 1024)
 
 /*
  * Hardware drivers
@@ -104,7 +104,8 @@
 	"mtdparts=" MTDPARTS_DEFAULT "\0"										\
 	"prg_uboot=tftpboot 0x80000000 $(uboot); protect off 0xa0000000 +0x20000; erase 0xa0000000 +0x20000; cp.b 0x80000000 0xa0000000 $(filesize)\0" \
 	"prg_kernel=tftpboot 0x80000000 $(uimage); erase 0xa0040000 +0x180000; cp.b 0x80000000 0xa0040000 $(filesize)\0"	\
-	"prg_jffs2=tftpboot 0x80000000 $(jffs2); erase 0xa01c0000 0xa1ffffff; cp.b 0x80000000 0xa01c0000 $(filesize)\0"
+	"prg_jffs2=tftpboot 0x80000000 $(jffs2); erase 0xa01c0000 0xa1ffffff; cp.b 0x80000000 0xa01c0000 $(filesize)\0"	\
+	"videomode=video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1,sync:1241513985,vmode:0\0"
 
 
 #define CONFIG_SMC911X		1
@@ -201,15 +202,16 @@
 
 #define CONFIG_S6E63D6				1
 
-#define CONFIG_LCD				1
-#define CONFIG_VIDEO_MX3			1
-#define CONFIG_SYS_WHITE_ON_BLACK		1
-#define LCD_BPP					LCD_COLOR8
-#define	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE	1
-#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
-
-#define	CONFIG_SPLASH_SCREEN			1
-#define CONFIG_CMD_BMP				1
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_MX3
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_CMD_BMP
+#define CONFIG_BMP_16BPP
 #endif
 
 #endif /* __CONFIG_H */
diff --git a/include/configs/qong.h b/include/configs/qong.h
index e4bc1d0..b1fc80c 100644
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -79,15 +79,16 @@
 #define CONFIG_DNET_BASE	(CS1_BASE + QONG_FPGA_PERIPH_SIZE)
 
 /* Framebuffer and LCD */
-#define CONFIG_LCD
+#define CONFIG_VIDEO
+#define CONFIG_CFB_CONSOLE
 #define CONFIG_VIDEO_MX3
-#define	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VGA_AS_SINGLE_DEVICE
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define LCD_BPP		LCD_COLOR16
-#define	CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN
 #define CONFIG_CMD_BMP
 #define CONFIG_BMP_16BPP
-#define CONFIG_DISPLAY_COM57H5M10XRC
 
 /* USB */
 #define CONFIG_CMD_USB
@@ -177,6 +178,9 @@
 		" +${filesize};cp.b ${fileaddr} "			\
 		xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"		\
 	"upd=run load update\0"						\
+	"videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000,"	\
+		"le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,"	\
+		"vmode:0\0"						\
 
 /*
  * Miscellaneous configurable options
-- 
1.7.1

[U-Boot] [PATCH v3 1/2] mx31: make HSP clock for mx3fb driver available

[Anatolij Gustschin]

Hi Stefano,

On Thu, 13 Oct 2011 11:16:28 +0200
Anatolij Gustschin <agust@denx.de> wrote:

> From: Helmut Raiger <helmut.raiger@hale.at>
> 
> This additionally updates mx31/generic.c by
> - replacing __REG() macro accesses with readl() and writel()
> - providing macros for PDR0 and PLL bit accesses
> 
> Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
> Acked-by: Marek Vasut <marek.vasut@gmail.com>
> Signed-off-by: Anatolij Gustschin <agust@denx.de>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes since v2:
>  - rebased to apply on current top of tree
> 
>  arch/arm/cpu/arm1136/mx31/generic.c       |   40 +++++++++++++++++++---------
>  arch/arm/include/asm/arch-mx31/clock.h    |    1 +
>  arch/arm/include/asm/arch-mx31/imx-regs.h |   14 ++++++++++
>  3 files changed, 42 insertions(+), 13 deletions(-)

Are you okay with this patch? Should I queue it with another
(video: Moving mx3fb.c to CONFIG_VIDEO) patch in my video tree?

Thanks,
Anatolij
--
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de

[U-Boot] [PATCH v3 1/2] mx31: make HSP clock for mx3fb driver available

[Stefano Babic]

On 10/13/2011 11:23 AM, Anatolij Gustschin wrote:
> Hi Stefano,
> 
> On Thu, 13 Oct 2011 11:16:28 +0200
> Anatolij Gustschin <agust@denx.de> wrote:
> 
>> From: Helmut Raiger <helmut.raiger@hale.at>
>>
>> This additionally updates mx31/generic.c by
>> - replacing __REG() macro accesses with readl() and writel()
>> - providing macros for PDR0 and PLL bit accesses
>>
>> Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
>> Acked-by: Marek Vasut <marek.vasut@gmail.com>
>> Signed-off-by: Anatolij Gustschin <agust@denx.de>
>> Cc: Stefano Babic <sbabic@denx.de>
>> ---
>> Changes since v2:
>>  - rebased to apply on current top of tree
>>
>>  arch/arm/cpu/arm1136/mx31/generic.c       |   40 +++++++++++++++++++---------
>>  arch/arm/include/asm/arch-mx31/clock.h    |    1 +
>>  arch/arm/include/asm/arch-mx31/imx-regs.h |   14 ++++++++++
>>  3 files changed, 42 insertions(+), 13 deletions(-)
> 
> Are you okay with this patch?

Yes, they are ok - if not yet sent, here my:

Acked-by: Stefano Babic <sbabic@denx.de>


> Should I queue it with another
> (video: Moving mx3fb.c to CONFIG_VIDEO) patch in my video tree?

Yes, they belong together - we should assure that all three goes to
mainline in the same shot.

Thanks,
Stefano

-- 
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot] [PATCH v3 2/2] video: Moving mx3fb.c to CONFIG_VIDEO

[Helmut Raiger]

On 10/13/2011 11:16 AM, Anatolij Gustschin wrote:
> From: Helmut Raiger<helmut.raiger@hale.at>
>
> mx3fb.c was based on CONFIG_LCD and is moved by this patch to
> CONFIG_VIDEO, which has greater freedom in selecting videomodes
> even at runtime.
>
> This renders the accumulating list of display defines
> (CONFIG_DISPLAY_VBEST..., CONFIG_DISPLAY_C057...) obsolete as
> these may be setup through env variables:
>
> uboot>  setenv mydisplay 'video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,
> 	le:9,ri:17,up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0'
> uboot>  setenv videomode ${mydisplay}
>
> This commit also fixes the board config files for qong and
> imx31_phycore boards as needed. The videomode settings of
> previously supported displays are added to CONFIG_EXTRA_ENV_SETTINGS
> now. CONFIG_SYS_MALLOC_LEN for imx31_phycore board is increased
> to make the frame buffer allocation working with the changed
> driver.
>
> Signed-off-by: Helmut Raiger<helmut.raiger@hale.at>
> Signed-off-by: Anatolij Gustschin<agust@denx.de>
> Cc: Stefano Babic<sbabic@denx.de>
> ---
> Changes since v2:
>   - fixed commit message
>   - added display info for removed display timings of
>     previously supported displays (in a comment)
>   - fixed compiler warning showed when compiling with debug
>     enabled
>   - added "Video: " prefix before display info output (as
>     we usually do it in U-Boot)
>   - fixed board config files for 'qong' and 'imx31_phycore' boards
>     so that this commit doesn't break compiling (bisectable now)
>   - added videomode settings for previously supported displays on
>     'qong' and 'imx31_phycore' to CONFIG_EXTRA_ENV_SETTINGS
>   - increased CONFIG_SYS_MALLOC_LEN for 'imx31_phycore' so that
>     the frame buffer can be allocated now (this is required to make
>     the display support working with the changed mx3fb driver)
>
Hi Anatolij,

     I'm fine with your changes. It still works on our board. Thanks for 
testing and improving.

Helmut




--
Scanned by MailScanner.

[U-Boot] [PATCH v3 2/2] video: Moving mx3fb.c to CONFIG_VIDEO

[Anatolij Gustschin]

Hi Helmut,

On Fri, 14 Oct 2011 08:37:48 +0200
Helmut Raiger <helmut.raiger@hale.at> wrote:
...
> Hi Anatolij,
> 
>      I'm fine with your changes. It still works on our board. Thanks for 
> testing and improving.

Great, thanks for the feedback and testing!

Anatolij

[U-Boot] [PATCH v3 1/2] mx31: make HSP clock for mx3fb driver available

[Anatolij Gustschin]

On Thu, 13 Oct 2011 11:16:28 +0200
Anatolij Gustschin <agust@denx.de> wrote:

> From: Helmut Raiger <helmut.raiger@hale.at>
> 
> This additionally updates mx31/generic.c by
> - replacing __REG() macro accesses with readl() and writel()
> - providing macros for PDR0 and PLL bit accesses
> 
> Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
> Acked-by: Marek Vasut <marek.vasut@gmail.com>
> Signed-off-by: Anatolij Gustschin <agust@denx.de>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes since v2:
>  - rebased to apply on current top of tree
> 
>  arch/arm/cpu/arm1136/mx31/generic.c       |   40 +++++++++++++++++++---------
>  arch/arm/include/asm/arch-mx31/clock.h    |    1 +
>  arch/arm/include/asm/arch-mx31/imx-regs.h |   14 ++++++++++
>  3 files changed, 42 insertions(+), 13 deletions(-)

Applied to u-boot-video master.

Anatolij

[U-Boot] [PATCH v3 2/2] video: Moving mx3fb.c to CONFIG_VIDEO

[Anatolij Gustschin]

On Thu, 13 Oct 2011 11:16:29 +0200
Anatolij Gustschin <agust@denx.de> wrote:

> From: Helmut Raiger <helmut.raiger@hale.at>
> 
> mx3fb.c was based on CONFIG_LCD and is moved by this patch to
> CONFIG_VIDEO, which has greater freedom in selecting videomodes
> even at runtime.
> 
> This renders the accumulating list of display defines
> (CONFIG_DISPLAY_VBEST..., CONFIG_DISPLAY_C057...) obsolete as
> these may be setup through env variables:
> 
> uboot> setenv mydisplay 'video=ctfb:x:240,y:320,depth:16,mode:0,pclk:185925,
> 	le:9,ri:17,up:7,lo:10,hs:1,vs:1,sync:100663296,vmode:0'
> uboot> setenv videomode ${mydisplay}
> 
> This commit also fixes the board config files for qong and
> imx31_phycore boards as needed. The videomode settings of
> previously supported displays are added to CONFIG_EXTRA_ENV_SETTINGS
> now. CONFIG_SYS_MALLOC_LEN for imx31_phycore board is increased
> to make the frame buffer allocation working with the changed
> driver.
> 
> Signed-off-by: Helmut Raiger <helmut.raiger@hale.at>
> Signed-off-by: Anatolij Gustschin <agust@denx.de>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
> Changes since v2:
>  - fixed commit message
>  - added display info for removed display timings of
>    previously supported displays (in a comment)
>  - fixed compiler warning showed when compiling with debug
>    enabled
>  - added "Video: " prefix before display info output (as
>    we usually do it in U-Boot)
>  - fixed board config files for 'qong' and 'imx31_phycore' boards
>    so that this commit doesn't break compiling (bisectable now)
>  - added videomode settings for previously supported displays on
>    'qong' and 'imx31_phycore' to CONFIG_EXTRA_ENV_SETTINGS
>  - increased CONFIG_SYS_MALLOC_LEN for 'imx31_phycore' so that
>    the frame buffer can be allocated now (this is required to make
>    the display support working with the changed mx3fb driver)
> 
>  drivers/video/Makefile          |    2 +-
>  drivers/video/cfb_console.c     |    7 +
>  drivers/video/mx3fb.c           |  459 +++++++++++++++++++++++----------------
>  include/configs/imx31_phycore.h |   24 +-
>  include/configs/qong.h          |   14 +-
>  5 files changed, 297 insertions(+), 209 deletions(-)

Applied to u-boot-video master.

Anatolij