[PATCH v2 00/16] Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER

[PATCH v2 00/16] Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER

[Marc Zyngier]

In order to support multiple primary interrupt controllers in the same
image, it is necessary to use the MULTI_IRQ_HANDLER config option.

This patch series makes a first step in that direction by:
- having the GIC code to provides a global handler,
- make GIC users to provide this handler from their machine descriptor.

A side effect of this is that it forces OMAP2/3 platforms to be
converted too in order to preserve the MULTI_OMAP feature. This leads
to a certain simplification of the interrupt handling for the
OMAP2/3/4 platforms.

The primary IRQ handlers have been written in C, and the performance
degradation is hardly noticeable. Should some tests reveal a major
increase in latency, it is always possible to restore the ASM version.

This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2
and Harmony. Patches against next-20110926 plus my PPI series.

[PATCH v2 01/16] ARM: Make global handler and CONFIG_MULTI_IRQ_HANDLER mutually exclusive

[Marc Zyngier]

Even when CONFIG_MULTI_IRQ_HANDLER is selected, the core code
requires the arch_irq_handler_default macro to be defined as
a fallback.

It turns out nobody is using that particular feature as both PXA
and shmobile have all their machine descriptors populated with
the interrupt handler, leaving unused code (or empty macros) in
their entry-macro.S file just to be able to compile entry-armv.S.

Make CONFIG_MULTI_IRQ_HANDLER exclusive wrt arch_irq_handler_default,
which allows to remove one test from the hot path. Also cleanup both
PXA and shmobile entry-macro.S.

Cc: Eric Miao <eric.y.miao@gmail.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/kernel/entry-armv.S                      |    7 ++--
 arch/arm/mach-pxa/include/mach/entry-macro.S      |   36 ---------------------
 arch/arm/mach-shmobile/include/mach/entry-macro.S |    9 -----
 3 files changed, 3 insertions(+), 49 deletions(-)

diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
index 9ad50c4..bd49a6a 100644
--- a/arch/arm/kernel/entry-armv.S
+++ b/arch/arm/kernel/entry-armv.S
@@ -36,12 +36,11 @@
 #ifdef CONFIG_MULTI_IRQ_HANDLER
 	ldr	r1, =handle_arch_irq
 	mov	r0, sp
-	ldr	r1, [r1]
 	adr	lr, BSYM(9997f)
-	teq	r1, #0
-	movne	pc, r1
-#endif
+	ldr	pc, [r1]
+#else
 	arch_irq_handler_default
+#endif
 9997:
 	.endm
 
diff --git a/arch/arm/mach-pxa/include/mach/entry-macro.S b/arch/arm/mach-pxa/include/mach/entry-macro.S
index a73bc86..260c0c1 100644
--- a/arch/arm/mach-pxa/include/mach/entry-macro.S
+++ b/arch/arm/mach-pxa/include/mach/entry-macro.S
@@ -7,45 +7,9 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-#include <mach/hardware.h>
-#include <mach/irqs.h>
 
 		.macro	disable_fiq
 		.endm
 
-		.macro  get_irqnr_preamble, base, tmp
-		.endm
-
 		.macro  arch_ret_to_user, tmp1, tmp2
 		.endm
-
-		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-		mrc	p15, 0, \tmp, c0, c0, 0		@ CPUID
-		mov	\tmp, \tmp, lsr #13
-		and	\tmp, \tmp, #0x7		@ Core G
-		cmp	\tmp, #1
-		bhi	1002f
-
-		@ Core Generation 1 (PXA25x)
-		mov	\base, #io_p2v(0x40000000)	@ IIR Ctl = 0x40d00000
-		add	\base, \base, #0x00d00000
-		ldr	\irqstat, [\base, #0]		@ ICIP
-		ldr	\irqnr, [\base, #4]		@ ICMR
-
-		ands	\irqnr, \irqstat, \irqnr
-		beq	1001f
-		rsb	\irqstat, \irqnr, #0
-		and	\irqstat, \irqstat, \irqnr
-		clz	\irqnr, \irqstat
-		rsb	\irqnr, \irqnr, #(31 + PXA_IRQ(0))
-		b	1001f
-1002:
-		@ Core Generation 2 (PXA27x) or Core Generation 3 (PXA3xx)
-		mrc	p6, 0, \irqstat, c5, c0, 0	@ ICHP
-		tst	\irqstat, #0x80000000
-		beq	1001f
-		bic	\irqstat, \irqstat, #0x80000000
-		mov	\irqnr, \irqstat, lsr #16
-		add	\irqnr, \irqnr, #(PXA_IRQ(0))
-1001:
-		.endm
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
index 8d4a416..2a57b29 100644
--- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
@@ -18,14 +18,5 @@
 	.macro  disable_fiq
 	.endm
 
-	.macro  get_irqnr_preamble, base, tmp
-	.endm
-
-	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-	.endm
-
-	.macro  test_for_ipi, irqnr, irqstat, base, tmp
-	.endm
-
 	.macro  arch_ret_to_user, tmp1, tmp2
 	.endm
-- 
1.7.0.4

[PATCH v2 02/16] ARM: smp: Add an IPI handler callable from C code

[Marc Zyngier]

In order to be able to handle IPI directly from C code instead of
assembly code, introduce handle_IPI(), which is modeled after handle_IRQ().

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/include/asm/smp.h |    5 +++++
 arch/arm/kernel/smp.c      |    5 +++++
 2 files changed, 10 insertions(+), 0 deletions(-)

diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 7c2299f..1e5717a 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -33,6 +33,11 @@ extern void show_ipi_list(struct seq_file *, int);
 asmlinkage void do_IPI(int ipinr, struct pt_regs *regs);
 
 /*
+ * Called from C code, this handles an IPI.
+ */
+void handle_IPI(int ipinr, struct pt_regs *regs);
+
+/*
  * Setup the set of possible CPUs (via set_cpu_possible)
  */
 extern void smp_init_cpus(void);
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index fcca40b..5e060ea 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -603,6 +603,11 @@ static void ipi_cpu_stop(unsigned int cpu)
  */
 asmlinkage void __exception_irq_entry do_IPI(int ipinr, struct pt_regs *regs)
 {
+	handle_IPI(ipinr, regs);
+}
+
+void handle_IPI(int ipinr, struct pt_regs *regs)
+{
 	unsigned int cpu = smp_processor_id();
 	struct pt_regs *old_regs = set_irq_regs(regs);
 
-- 
1.7.0.4

[PATCH v2 03/16] ARM: GIC: Add global gic_handle_irq() function

[Marc Zyngier]

Provide the GIC code with a low level handler that can be used
by platforms using CONFIG_MULTI_IRQ_HANDLER. Though the handler is
written in C, the compiled code doesn't feel much slower than its
assembly counterpart (at least with my gcc 4.4.1).

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/common/gic.c               |   23 +++++++++++++++++++++++
 arch/arm/include/asm/hardware/gic.h |    1 +
 2 files changed, 24 insertions(+), 0 deletions(-)

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index a3f335c..5a22896 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -209,6 +209,29 @@ static int gic_set_wake(struct irq_data *d, unsigned int on)
 #define gic_set_wake	NULL
 #endif
 
+asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+{
+	u32 irqstat, irqnr;
+
+	do {
+		irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
+		irqnr = irqstat & ~0x1c00;
+
+		if (likely(irqnr > 15 && irqnr < 1021)) {
+			handle_IRQ(irqnr, regs);
+			continue;
+		}
+		if (irqnr < 16) {
+			writel_relaxed(irqstat, gic_cpu_base_addr + GIC_CPU_EOI);
+#ifdef CONFIG_SMP
+			handle_IPI(irqnr, regs);
+#endif
+			continue;
+		}
+		break;
+	} while (1);
+}
+
 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 {
 	struct gic_chip_data *chip_data = irq_get_handler_data(irq);
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 2dadd50..45e4ab4 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -38,6 +38,7 @@ extern struct irq_chip gic_arch_extn;
 
 void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
 void gic_secondary_init(unsigned int);
+void gic_handle_irq(struct pt_regs *regs);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
 
-- 
1.7.0.4

[PATCH v2 04/16] ARM: RealView: convert to CONFIG_MULTI_IRQ_HANDLER

[Marc Zyngier]

Convert the RealView platforms to be using the gic_handle_irq
function as their primary interrupt handler.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/Kconfig                                  |    1 +
 arch/arm/mach-realview/include/mach/entry-macro.S |    2 --
 arch/arm/mach-realview/realview_eb.c              |    1 +
 arch/arm/mach-realview/realview_pb1176.c          |    1 +
 arch/arm/mach-realview/realview_pb11mp.c          |    1 +
 arch/arm/mach-realview/realview_pba8.c            |    1 +
 arch/arm/mach-realview/realview_pbx.c             |    1 +
 7 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 472a7f8..6c31cc2 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -262,6 +262,7 @@ config ARCH_REALVIEW
 	select PLAT_VERSATILE_CLCD
 	select ARM_TIMER_SP804
 	select GPIO_PL061 if GPIOLIB
+	select MULTI_IRQ_HANDLER
 	help
 	  This enables support for ARM Ltd RealView boards.
 
diff --git a/arch/arm/mach-realview/include/mach/entry-macro.S b/arch/arm/mach-realview/include/mach/entry-macro.S
index 4071164..e8a5179 100644
--- a/arch/arm/mach-realview/include/mach/entry-macro.S
+++ b/arch/arm/mach-realview/include/mach/entry-macro.S
@@ -7,8 +7,6 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-#include <mach/hardware.h>
-#include <asm/hardware/entry-macro-gic.S>
 
 		.macro	disable_fiq
 		.endm
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 427e44e..f01e332 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -470,6 +470,7 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
 	.init_early	= realview_init_early,
 	.init_irq	= gic_init_irq,
 	.timer		= &realview_eb_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= realview_eb_init,
 #ifdef CONFIG_ZONE_DMA
 	.dma_zone_size	= SZ_256M,
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 99ea1c0..c7ef434 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -364,6 +364,7 @@ MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
 	.init_early	= realview_init_early,
 	.init_irq	= gic_init_irq,
 	.timer		= &realview_pb1176_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= realview_pb1176_init,
 #ifdef CONFIG_ZONE_DMA
 	.dma_zone_size	= SZ_256M,
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index 6cb8318..32d18e5 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -367,6 +367,7 @@ MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
 	.init_early	= realview_init_early,
 	.init_irq	= gic_init_irq,
 	.timer		= &realview_pb11mp_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= realview_pb11mp_init,
 #ifdef CONFIG_ZONE_DMA
 	.dma_zone_size	= SZ_256M,
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 3db72c5..0896cc4 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -317,6 +317,7 @@ MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
 	.init_early	= realview_init_early,
 	.init_irq	= gic_init_irq,
 	.timer		= &realview_pba8_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= realview_pba8_init,
 #ifdef CONFIG_ZONE_DMA
 	.dma_zone_size	= SZ_256M,
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index bea4212..cac0b69 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -400,6 +400,7 @@ MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
 	.init_early	= realview_init_early,
 	.init_irq	= gic_init_irq,
 	.timer		= &realview_pbx_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= realview_pbx_init,
 #ifdef CONFIG_ZONE_DMA
 	.dma_zone_size	= SZ_256M,
-- 
1.7.0.4

[PATCH v2 05/16] ARM: VExpress: convert to CONFIG_MULTI_IRQ_HANDLER

[Marc Zyngier]

Convert the VExpress platform to be using the gic_handle_irq
function as its primary interrupt handler.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/Kconfig                                  |    1 +
 arch/arm/mach-vexpress/include/mach/entry-macro.S |    2 --
 arch/arm/mach-vexpress/v2m.c                      |    2 ++
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6c31cc2..d3e246c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -295,6 +295,7 @@ config ARCH_VEXPRESS
 	select ICST
 	select PLAT_VERSATILE
 	select PLAT_VERSATILE_CLCD
+	select MULTI_IRQ_HANDLER
 	help
 	  This enables support for the ARM Ltd Versatile Express boards.
 
diff --git a/arch/arm/mach-vexpress/include/mach/entry-macro.S b/arch/arm/mach-vexpress/include/mach/entry-macro.S
index 73c1129..a14f9e6 100644
--- a/arch/arm/mach-vexpress/include/mach/entry-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/entry-macro.S
@@ -1,5 +1,3 @@
-#include <asm/hardware/entry-macro-gic.S>
-
 	.macro	disable_fiq
 	.endm
 
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index 47bca2a..d540a1b 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -24,6 +24,7 @@
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/timer-sp.h>
 #include <asm/hardware/sp810.h>
+#include <asm/hardware/gic.h>
 
 #include <mach/ct-ca9x4.h>
 #include <mach/motherboard.h>
@@ -457,5 +458,6 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
 	.init_early	= v2m_init_early,
 	.init_irq	= v2m_init_irq,
 	.timer		= &v2m_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= v2m_init,
 MACHINE_END
-- 
1.7.0.4

[PATCH v2 06/16] ARM: msm: convert SMP platforms to CONFIG_MULTI_IRQ_HANDLER

[Marc Zyngier]

Convert the SMP msm platforms to be using the gic_handle_irq
function as their primary interrupt handler.

Cc: David Brown <davidb@codeaurora.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/mach-msm/Kconfig                         |    2 +
 arch/arm/mach-msm/board-msm8960.c                 |    2 +
 arch/arm/mach-msm/board-msm8x60.c                 |    4 ++
 arch/arm/mach-msm/include/mach/entry-macro-qgic.S |   17 ---------
 arch/arm/mach-msm/include/mach/entry-macro-vic.S  |   37 ---------------------
 arch/arm/mach-msm/include/mach/entry-macro.S      |   27 +++++++++++++--
 6 files changed, 31 insertions(+), 58 deletions(-)
 delete mode 100644 arch/arm/mach-msm/include/mach/entry-macro-qgic.S
 delete mode 100644 arch/arm/mach-msm/include/mach/entry-macro-vic.S

diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index ebde97f..ba36b74 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -50,6 +50,7 @@ config ARCH_MSM8X60
 	select GPIO_MSM_V2
 	select MSM_GPIOMUX
 	select MSM_SCM if SMP
+	select MULTI_IRQ_HANDLER
 
 config ARCH_MSM8960
 	bool "MSM8960"
@@ -60,6 +61,7 @@ config ARCH_MSM8960
 	select MSM_V2_TLMM
 	select MSM_GPIOMUX
 	select MSM_SCM if SMP
+	select MULTI_IRQ_HANDLER
 
 endchoice
 
diff --git a/arch/arm/mach-msm/board-msm8960.c b/arch/arm/mach-msm/board-msm8960.c
index c811e29..7af9a6d 100644
--- a/arch/arm/mach-msm/board-msm8960.c
+++ b/arch/arm/mach-msm/board-msm8960.c
@@ -101,6 +101,7 @@ MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
 	.map_io = msm8960_map_io,
 	.init_irq = msm8960_init_irq,
 	.timer = &msm_timer,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8960_sim_init,
 MACHINE_END
 
@@ -111,6 +112,7 @@ MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3")
 	.map_io = msm8960_map_io,
 	.init_irq = msm8960_init_irq,
 	.timer = &msm_timer,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8960_rumi3_init,
 MACHINE_END
 
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 30c6b58..1eca320 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -111,6 +111,7 @@ MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
 	.reserve = msm8x60_reserve,
 	.map_io = msm8x60_map_io,
 	.init_irq = msm8x60_init_irq,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8x60_init,
 	.timer = &msm_timer,
 MACHINE_END
@@ -121,6 +122,7 @@ MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
 	.reserve = msm8x60_reserve,
 	.map_io = msm8x60_map_io,
 	.init_irq = msm8x60_init_irq,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8x60_init,
 	.timer = &msm_timer,
 MACHINE_END
@@ -131,6 +133,7 @@ MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
 	.reserve = msm8x60_reserve,
 	.map_io = msm8x60_map_io,
 	.init_irq = msm8x60_init_irq,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8x60_init,
 	.timer = &msm_timer,
 MACHINE_END
@@ -141,6 +144,7 @@ MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
 	.reserve = msm8x60_reserve,
 	.map_io = msm8x60_map_io,
 	.init_irq = msm8x60_init_irq,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8x60_init,
 	.timer = &msm_timer,
 MACHINE_END
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
deleted file mode 100644
index 717076f..0000000
--- a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Low-level IRQ helper macros
- *
- * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/entry-macro-gic.S>
-
-	.macro	disable_fiq
-	.endm
-
-	.macro  arch_ret_to_user, tmp1, tmp2
-	.endm
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-vic.S b/arch/arm/mach-msm/include/mach/entry-macro-vic.S
deleted file mode 100644
index 70563ed..0000000
--- a/arch/arm/mach-msm/include/mach/entry-macro-vic.S
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <mach/msm_iomap.h>
-
-	.macro	disable_fiq
-	.endm
-
-	.macro	get_irqnr_preamble, base, tmp
-	@ enable imprecise aborts
-	cpsie	a
-	mov	\base, #MSM_VIC_BASE
-	.endm
-
-	.macro	arch_ret_to_user, tmp1, tmp2
-	.endm
-
-	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-	@ 0xD0 has irq# or old irq# if the irq has been handled
-	@ 0xD4 has irq# or -1 if none pending *but* if you just
-	@ read 0xD4 you never get the first irq for some reason
-	ldr	\irqnr, [\base, #0xD0]
-	ldr	\irqnr, [\base, #0xD4]
-	cmp	\irqnr, #0xffffffff
-	.endm
diff --git a/arch/arm/mach-msm/include/mach/entry-macro.S b/arch/arm/mach-msm/include/mach/entry-macro.S
index b16f082..41f7003 100644
--- a/arch/arm/mach-msm/include/mach/entry-macro.S
+++ b/arch/arm/mach-msm/include/mach/entry-macro.S
@@ -16,8 +16,27 @@
  *
  */
 
-#if defined(CONFIG_ARM_GIC)
-#include <mach/entry-macro-qgic.S>
-#else
-#include <mach/entry-macro-vic.S>
+	.macro	disable_fiq
+	.endm
+
+	.macro	arch_ret_to_user, tmp1, tmp2
+	.endm
+
+#if !defined(CONFIG_ARM_GIC)
+#include <mach/msm_iomap.h>
+
+	.macro	get_irqnr_preamble, base, tmp
+	@ enable imprecise aborts
+	cpsie	a
+	mov	\base, #MSM_VIC_BASE
+	.endm
+
+	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+	@ 0xD0 has irq# or old irq# if the irq has been handled
+	@ 0xD4 has irq# or -1 if none pending *but* if you just
+	@ read 0xD4 you never get the first irq for some reason
+	ldr	\irqnr, [\base, #0xD0]
+	ldr	\irqnr, [\base, #0xD4]
+	cmp	\irqnr, #0xffffffff
+	.endm
 #endif
-- 
1.7.0.4

[PATCH v2 07/16] ARM: GIC: Add global gic_handle_irq_offset() function

[Marc Zyngier]

Similar to gic_handle_irq(), gic_handle_irq_offset() is provided
for those platform who insist on having their GIC base interrupt
at something different from zero. At the moment, Exynos4 is the
only one...

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/common/gic.c               |   24 ++++++++++++++++++++++++
 arch/arm/include/asm/hardware/gic.h |    1 +
 2 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 5a22896..ef803d2 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -232,6 +232,30 @@ asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
 	} while (1);
 }
 
+asmlinkage void __exception_irq_entry gic_handle_irq_offset(struct pt_regs *regs)
+{
+	u32 irqstat, irqnr;
+	u32 offset = gic_data[0].irq_offset;
+
+	do {
+		irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
+		irqnr = irqstat & ~0x1c00;
+
+		if (likely(irqnr > 15 && irqnr < 1021)) {
+			handle_IRQ(irqnr + offset, regs);
+			continue;
+		}
+		if (irqnr < 16) {
+			writel_relaxed(irqstat, gic_cpu_base_addr + GIC_CPU_EOI);
+#ifdef CONFIG_SMP
+			handle_IPI(irqnr, regs);
+#endif
+			continue;
+		}
+		break;
+	} while (1);
+}
+
 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 {
 	struct gic_chip_data *chip_data = irq_get_handler_data(irq);
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 45e4ab4..0f454c6 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -39,6 +39,7 @@ extern struct irq_chip gic_arch_extn;
 void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
 void gic_secondary_init(unsigned int);
 void gic_handle_irq(struct pt_regs *regs);
+void gic_handle_irq_offset(struct pt_regs *regs);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
 
-- 
1.7.0.4

[PATCH v2 08/16] ARM: exynos4: convert to CONFIG_MULTI_IRQ_HANDLER

[Marc Zyngier]

Convert the Exynos4 platforms to be using the gic_handle_irq_offset()
function as their primary interrupt handler.

Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/Kconfig                                 |    1 +
 arch/arm/mach-exynos4/include/mach/entry-macro.S |   62 ----------------------
 arch/arm/mach-exynos4/mach-armlex4210.c          |    2 +
 arch/arm/mach-exynos4/mach-nuri.c                |    2 +
 arch/arm/mach-exynos4/mach-origen.c              |    2 +
 arch/arm/mach-exynos4/mach-smdk4212.c            |    2 +
 arch/arm/mach-exynos4/mach-smdkv310.c            |    2 +
 arch/arm/mach-exynos4/mach-universal_c210.c      |    2 +
 8 files changed, 13 insertions(+), 62 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d3e246c..e32a4d3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -787,6 +787,7 @@ config ARCH_EXYNOS4
 	select HAVE_S3C_RTC if RTC_CLASS
 	select HAVE_S3C2410_I2C if I2C
 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
+	select MULTI_IRQ_HANDLER
 	help
 	  Samsung EXYNOS4 series based systems
 
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index 807d05d..efe9a00 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -9,71 +9,9 @@
  * warranty of any kind, whether express or implied.
 */
 
-#include <mach/hardware.h>
-#include <mach/map.h>
-#include <asm/hardware/gic.h>
-
 		.macro	disable_fiq
 		.endm
 
-		.macro  get_irqnr_preamble, base, tmp
-		ldr	\base, =gic_cpu_base_addr
-		ldr	\base, [\base]
-		mrc     p15, 0, \tmp, c0, c0, 5
-		and     \tmp, \tmp, #3
-		cmp     \tmp, #1
-		addeq   \base, \base, #EXYNOS4_GIC_BANK_OFFSET
-		.endm
-
 		.macro  arch_ret_to_user, tmp1, tmp2
 		.endm
 
-		/*
-		 * The interrupt numbering scheme is defined in the
-		 * interrupt controller spec.  To wit:
-		 *
-		 * Interrupts 0-15 are IPI
-		 * 16-28 are reserved
-		 * 29-31 are local.  We allow 30 to be used for the watchdog.
-		 * 32-1020 are global
-		 * 1021-1022 are reserved
-		 * 1023 is "spurious" (no interrupt)
-		 *
-		 * For now, we ignore all local interrupts so only return an interrupt if it's
-		 * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
-		 *
-		 * A simple read from the controller will tell us the number of the highest
-                 * priority enabled interrupt.  We then just need to check whether it is in the
-		 * valid range for an IRQ (30-1020 inclusive).
-		 */
-
-		.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-		ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
-
-		ldr	\tmp, =1021
-
-		bic     \irqnr, \irqstat, #0x1c00
-
-		cmp     \irqnr, #15
-		cmpcc	\irqnr, \irqnr
-		cmpne	\irqnr, \tmp
-		cmpcs	\irqnr, \irqnr
-		addne	\irqnr, \irqnr, #32
-
-		.endm
-
-		/* We assume that irqstat (the raw value of the IRQ acknowledge
-		 * register) is preserved from the macro above.
-		 * If there is an IPI, we immediately signal end of interrupt on the
-		 * controller, since this requires the original irqstat value which
-		 * we won't easily be able to recreate later.
-		 */
-
-		.macro test_for_ipi, irqnr, irqstat, base, tmp
-		bic	\irqnr, \irqstat, #0x1c00
-		cmp	\irqnr, #16
-		strcc	\irqstat, [\base, #GIC_CPU_EOI]
-		cmpcs	\irqnr, \irqnr
-		.endm
-
diff --git a/arch/arm/mach-exynos4/mach-armlex4210.c b/arch/arm/mach-exynos4/mach-armlex4210.c
index 8c82c6b..969e04c 100644
--- a/arch/arm/mach-exynos4/mach-armlex4210.c
+++ b/arch/arm/mach-exynos4/mach-armlex4210.c
@@ -15,6 +15,7 @@
 #include <linux/serial_core.h>
 #include <linux/smsc911x.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
@@ -213,6 +214,7 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= armlex4210_map_io,
+	.handle_irq	= gic_handle_irq_offset,
 	.init_machine	= armlex4210_machine_init,
 	.timer		= &exynos4_timer,
 MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
index 5780ee3..5e133ae 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -28,6 +28,7 @@
 
 #include <video/platform_lcd.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
@@ -1192,6 +1193,7 @@ MACHINE_START(NURI, "NURI")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= nuri_map_io,
+	.handle_irq	= gic_handle_irq_offset,
 	.init_machine	= nuri_machine_init,
 	.timer		= &exynos4_timer,
 	.reserve        = &nuri_reserve,
diff --git a/arch/arm/mach-exynos4/mach-origen.c b/arch/arm/mach-exynos4/mach-origen.c
index 06250fc..7ede5fc 100644
--- a/arch/arm/mach-exynos4/mach-origen.c
+++ b/arch/arm/mach-exynos4/mach-origen.c
@@ -17,6 +17,7 @@
 #include <linux/pwm_backlight.h>
 #include <linux/gpio_keys.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
@@ -215,6 +216,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= origen_map_io,
+	.handle_irq	= gic_handle_irq_offset,
 	.init_machine	= origen_machine_init,
 	.timer		= &exynos4_timer,
 MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdk4212.c b/arch/arm/mach-exynos4/mach-smdk4212.c
index cf92514..84a0446 100644
--- a/arch/arm/mach-exynos4/mach-smdk4212.c
+++ b/arch/arm/mach-exynos4/mach-smdk4212.c
@@ -20,6 +20,7 @@
 #include <linux/regulator/machine.h>
 #include <linux/serial_core.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
@@ -290,6 +291,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= smdk4212_map_io,
+	.handle_irq	= gic_handle_irq_offset,
 	.init_machine	= smdk4212_machine_init,
 	.timer		= &exynos4_timer,
 MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index 088644e..8e11eaa 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -20,6 +20,7 @@
 #include <linux/input.h>
 #include <linux/pwm_backlight.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
@@ -351,6 +352,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= smdkv310_map_io,
+	.handle_irq	= gic_handle_irq_offset,
 	.init_machine	= smdkv310_machine_init,
 	.timer		= &exynos4_timer,
 MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
index 39c34a1..43f156d 100644
--- a/arch/arm/mach-exynos4/mach-universal_c210.c
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -23,6 +23,7 @@
 #include <linux/i2c/mcs.h>
 #include <linux/i2c/atmel_mxt_ts.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
@@ -876,6 +877,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= universal_map_io,
+	.handle_irq	= gic_handle_irq_offset,
 	.init_machine	= universal_machine_init,
 	.timer		= &exynos4_timer,
 	.reserve        = &universal_reserve,
-- 
1.7.0.4

[PATCH v2 09/16] ARM: tegra2: convert to CONFIG_MULTI_IRQ_HANDLER

[Marc Zyngier]

Convert the tegra2 platforms to be using the gic_handle_irq
function as their primary interrupt handler.

Tested on harmony.

Cc: Colin Cross <ccross@android.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/mach-tegra/Kconfig                    |    1 +
 arch/arm/mach-tegra/board-dt.c                 |    2 ++
 arch/arm/mach-tegra/board-harmony.c            |    2 ++
 arch/arm/mach-tegra/board-paz00.c              |    2 ++
 arch/arm/mach-tegra/board-seaboard.c           |    4 ++++
 arch/arm/mach-tegra/board-trimslice.c          |    2 ++
 arch/arm/mach-tegra/include/mach/entry-macro.S |   22 ++--------------------
 7 files changed, 15 insertions(+), 20 deletions(-)

diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index d82ebab..ba0ac3f 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -13,6 +13,7 @@ config ARCH_TEGRA_2x_SOC
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
 	select USB_ULPI if USB_SUPPORT
 	select USB_ULPI_VIEWPORT if USB_SUPPORT
+	select MULTI_IRQ_HANDLER
 	help
 	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
diff --git a/arch/arm/mach-tegra/board-dt.c b/arch/arm/mach-tegra/board-dt.c
index 0b3f937..cfa39c5 100644
--- a/arch/arm/mach-tegra/board-dt.c
+++ b/arch/arm/mach-tegra/board-dt.c
@@ -32,6 +32,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c-tegra.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -115,6 +116,7 @@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)")
 	.soc		= &tegra_soc_desc,
 	.init_early	= tegra_init_early,
 	.init_irq	= tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer		= &tegra_timer,
 	.init_machine	= tegra_dt_init,
 	.dt_compat	= tegra_dt_board_compat,
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index f2ef94f..eb65d68 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -31,6 +31,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <asm/hardware/gic.h>
 #include <asm/setup.h>
 
 #include <mach/tegra_wm8903_pdata.h>
@@ -189,6 +190,7 @@ MACHINE_START(HARMONY, "harmony")
 	.map_io         = tegra_map_common_io,
 	.init_early	= tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_harmony_init,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 63595f0..fc7831f 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -28,6 +28,7 @@
 #include <linux/i2c.h>
 #include <linux/rfkill-gpio.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
@@ -192,6 +193,7 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
 	.map_io         = tegra_map_common_io,
 	.init_early	= tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_paz00_init,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index dfd9c95..7fd71cf 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -34,6 +34,7 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 
 #include "board.h"
 #include "board-seaboard.h"
@@ -286,6 +287,7 @@ MACHINE_START(SEABOARD, "seaboard")
 	.map_io         = tegra_map_common_io,
 	.init_early     = tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_seaboard_init,
 MACHINE_END
@@ -296,6 +298,7 @@ MACHINE_START(KAEN, "kaen")
 	.map_io         = tegra_map_common_io,
 	.init_early     = tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_kaen_init,
 MACHINE_END
@@ -306,6 +309,7 @@ MACHINE_START(WARIO, "wario")
 	.map_io         = tegra_map_common_io,
 	.init_early     = tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_wario_init,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index 16cfc39..c5aa9df 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -26,6 +26,7 @@
 #include <linux/i2c.h>
 #include <linux/gpio.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/setup.h>
@@ -179,6 +180,7 @@ MACHINE_START(TRIMSLICE, "trimslice")
 	.map_io         = tegra_map_common_io,
 	.init_early	= tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_trimslice_init,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/include/mach/entry-macro.S b/arch/arm/mach-tegra/include/mach/entry-macro.S
index dd165c5..ac11262 100644
--- a/arch/arm/mach-tegra/include/mach/entry-macro.S
+++ b/arch/arm/mach-tegra/include/mach/entry-macro.S
@@ -12,30 +12,15 @@
  * GNU General Public License for more details.
  *
  */
-#include <mach/iomap.h>
-#include <mach/io.h>
-
-#if defined(CONFIG_ARM_GIC)
-#define HAVE_GET_IRQNR_PREAMBLE
-#include <asm/hardware/entry-macro-gic.S>
-
-	/* Uses the GIC interrupt controller built into the cpu */
-#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
 
 	.macro	disable_fiq
 	.endm
 
-	.macro	get_irqnr_preamble, base, tmp
-	movw \base, #(ICTRL_BASE & 0x0000ffff)
-	movt \base, #((ICTRL_BASE & 0xffff0000) >> 16)
+	.macro	arch_ret_to_user, tmp1, tmp2
 	.endm
 
-	.macro  arch_ret_to_user, tmp1, tmp2
-	.endm
-#else
+#if !defined(CONFIG_ARM_GIC)
 	/* legacy interrupt controller for AP16 */
-	.macro	disable_fiq
-	.endm
 
 	.macro	get_irqnr_preamble, base, tmp
 	@ enable imprecise aborts
@@ -46,9 +31,6 @@
 	orr \base, #0x0000f000
 	.endm
 
-	.macro	arch_ret_to_user, tmp1, tmp2
-	.endm
-
 	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 	ldr \irqnr, [\base, #0x20]	@ EVT_IRQ_STS
 	cmp \irqnr, #0x80
-- 
1.7.0.4

[PATCH v2 10/16] ARM: ux500: convert to CONFIG_MULTI_IRQ_HANDLER

[Marc Zyngier]

Convert the ux500 platforms to be using the gic_handle_irq
function as their primary interrupt handler.

Cc: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/mach-ux500/Kconfig                    |    1 +
 arch/arm/mach-ux500/board-mop500.c             |    4 ++++
 arch/arm/mach-ux500/board-u5500.c              |    2 ++
 arch/arm/mach-ux500/include/mach/entry-macro.S |    2 --
 4 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index a3e0c86..bb2b52b 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -7,6 +7,7 @@ config UX500_SOC_COMMON
 	select HAS_MTU
 	select ARM_ERRATA_753970
 	select ARM_ERRATA_754322
+	select MULTI_IRQ_HANDLER
 
 menu "Ux500 SoC"
 
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index f0b1a00..2539b0b 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -33,6 +33,7 @@
 #include <linux/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 
 #include <plat/i2c.h>
 #include <plat/ste_dma40.h>
@@ -696,6 +697,7 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
 	.init_irq	= ux500_init_irq,
 	/* we re-use nomadik timer here */
 	.timer		= &ux500_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= mop500_init_machine,
 MACHINE_END
 
@@ -705,6 +707,7 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
 	.map_io		= u8500_map_io,
 	.init_irq	= ux500_init_irq,
 	.timer		= &ux500_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= hrefv60_init_machine,
 MACHINE_END
 
@@ -715,5 +718,6 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
 	.init_irq	= ux500_init_irq,
 	/* we re-use nomadik timer here */
 	.timer		= &ux500_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= snowball_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
index ddfad36..c4c90a3 100644
--- a/arch/arm/mach-ux500/board-u5500.c
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -11,6 +11,7 @@
 #include <linux/irq.h>
 #include <linux/i2c.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 
@@ -123,5 +124,6 @@ MACHINE_START(U5500, "ST-Ericsson U5500 Platform")
 	.map_io		= u5500_map_io,
 	.init_irq	= ux500_init_irq,
 	.timer		= &ux500_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= u5500_init_machine,
 MACHINE_END
diff --git a/arch/arm/mach-ux500/include/mach/entry-macro.S b/arch/arm/mach-ux500/include/mach/entry-macro.S
index 071bba9..e16299e 100644
--- a/arch/arm/mach-ux500/include/mach/entry-macro.S
+++ b/arch/arm/mach-ux500/include/mach/entry-macro.S
@@ -10,8 +10,6 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-#include <mach/hardware.h>
-#include <asm/hardware/entry-macro-gic.S>
 
 		.macro	disable_fiq
 		.endm
-- 
1.7.0.4

[PATCH v2 11/16] ARM: shmobile: convert smp platforms to gic_handle_irq()

[Marc Zyngier]

Convert the SMP shmobile platforms to use gic_handle_irq() instead
of the assembly macro.

Cc: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/mach-shmobile/Makefile              |    1 -
 arch/arm/mach-shmobile/board-ag5evm.c        |    2 +-
 arch/arm/mach-shmobile/entry-gic.S           |   18 ------------------
 arch/arm/mach-shmobile/include/mach/common.h |    1 -
 4 files changed, 1 insertions(+), 21 deletions(-)
 delete mode 100644 arch/arm/mach-shmobile/entry-gic.S

diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index 612b270..f58ef1e 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -28,7 +28,6 @@ pfc-$(CONFIG_ARCH_SH73A0)	+= pfc-sh73a0.o
 obj-$(CONFIG_ARCH_SH7367)	+= entry-intc.o
 obj-$(CONFIG_ARCH_SH7377)	+= entry-intc.o
 obj-$(CONFIG_ARCH_SH7372)	+= entry-intc.o
-obj-$(CONFIG_ARCH_SH73A0)	+= entry-gic.o
 
 # PM objects
 obj-$(CONFIG_SUSPEND)		+= suspend.o
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 475342b..145473e 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -602,7 +602,7 @@ struct sys_timer ag5evm_timer = {
 MACHINE_START(AG5EVM, "ag5evm")
 	.map_io		= ag5evm_map_io,
 	.init_irq	= ag5evm_init_irq,
-	.handle_irq	= shmobile_handle_irq_gic,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= ag5evm_init,
 	.timer		= &ag5evm_timer,
 MACHINE_END
diff --git a/arch/arm/mach-shmobile/entry-gic.S b/arch/arm/mach-shmobile/entry-gic.S
deleted file mode 100644
index e20239b..0000000
--- a/arch/arm/mach-shmobile/entry-gic.S
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * ARM Interrupt demux handler using GIC
- *
- * Copyright (C) 2010 Magnus Damm
- * Copyright (C) 2011 Paul Mundt
- * Copyright (C) 2010 - 2011 Renesas Solutions Corp.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/assembler.h>
-#include <asm/entry-macro-multi.S>
-#include <asm/hardware/gic.h>
-#include <asm/hardware/entry-macro-gic.S>
-
-	arch_irq_handler shmobile_handle_irq_gic
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index c0cdbf9..137ba2a 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -7,7 +7,6 @@ extern void shmobile_secondary_vector(void);
 struct clk;
 extern int clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
-extern void shmobile_handle_irq_gic(struct pt_regs *);
 extern struct platform_suspend_ops shmobile_suspend_ops;
 struct cpuidle_device;
 extern void (*shmobile_cpuidle_modes[])(void);
-- 
1.7.0.4

[PATCH v2 12/16] ARM: cns3xxx: convert to CONFIG_MULTI_IRQ_HANDLER

[Marc Zyngier]

Convert the cns3xxx platform to be using the gic_handle_irq
function as its primary interrupt handler.

Cc: Anton Vorontsov <avorontsov@mvista.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/Kconfig                                 |    1 +
 arch/arm/mach-cns3xxx/cns3420vb.c                |    2 ++
 arch/arm/mach-cns3xxx/include/mach/entry-macro.S |    2 --
 3 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e32a4d3..70a947e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -334,6 +334,7 @@ config ARCH_CNS3XXX
 	select ARM_GIC
 	select MIGHT_HAVE_PCI
 	select PCI_DOMAINS if PCI
+	select MULTI_IRQ_HANDLER
 	help
 	  Support for Cavium Networks CNS3XXX platform.
 
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 55f7b4b..594852f 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -26,6 +26,7 @@
 #include <linux/mtd/partitions.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -201,5 +202,6 @@ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
 	.map_io		= cns3420_map_io,
 	.init_irq	= cns3xxx_init_irq,
 	.timer		= &cns3xxx_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= cns3420_init,
 MACHINE_END
diff --git a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
index d87bfc3..01c57df 100644
--- a/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
+++ b/arch/arm/mach-cns3xxx/include/mach/entry-macro.S
@@ -8,8 +8,6 @@
  * published by the Free Software Foundation.
  */
 
-#include <asm/hardware/entry-macro-gic.S>
-
 		.macro	disable_fiq
 		.endm
 
-- 
1.7.0.4

[PATCH v2 13/16] ARM: zynq: convert to CONFIG_MULTI_IRQ_HANDLER

[Marc Zyngier]

Convert the zynq platform to be using the gic_handle_irq
function as its primary interrupt handler.

Acked-by: John Linn <john.linn@xilinx.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/Kconfig                              |    1 +
 arch/arm/mach-zynq/common.c                   |    1 +
 arch/arm/mach-zynq/include/mach/entry-macro.S |    3 ---
 3 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 70a947e..0514264 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -911,6 +911,7 @@ config ARCH_ZYNQ
 	select ARM_AMBA
 	select ICST
 	select USE_OF
+	select MULTI_IRQ_HANDLER
 	help
 	  Support for Xilinx Zynq ARM Cortex A9 Platform
 endchoice
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 73e9368..ab5cfdd 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -112,6 +112,7 @@ static const char *xilinx_dt_match[] = {
 MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
 	.map_io		= xilinx_map_io,
 	.init_irq	= xilinx_irq_init,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= xilinx_init_machine,
 	.timer		= &xttcpss_sys_timer,
 	.dt_compat	= xilinx_dt_match,
diff --git a/arch/arm/mach-zynq/include/mach/entry-macro.S b/arch/arm/mach-zynq/include/mach/entry-macro.S
index 3cfc01b..d621fb7 100644
--- a/arch/arm/mach-zynq/include/mach/entry-macro.S
+++ b/arch/arm/mach-zynq/include/mach/entry-macro.S
@@ -20,9 +20,6 @@
  * GNU General Public License for more details.
  */
 
-#include <mach/hardware.h>
-#include <asm/hardware/entry-macro-gic.S>
-
 		.macro  disable_fiq
 		.endm
 
-- 
1.7.0.4

[PATCH v2 14/16] ARM: omap2/3: Add global omap2/3_intc_handle_irq() functions

[Marc Zyngier]

Provide the OMAP2/3 IRQ code with low level handlers that can be used
by platforms using CONFIG_MULTI_IRQ_HANDLER. Though the handlers are
written in C, the compiled code looks very similar to its assembly
counterpart (at least with my gcc 4.4.1).

Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/mach-omap2/irq.c              |   49 ++++++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/irqs.h |    2 +
 2 files changed, 51 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 3a12f75..0a48b33 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -35,6 +35,11 @@
 /* Number of IRQ state bits in each MIR register */
 #define IRQ_BITS_PER_REG	32
 
+#define OMAP2_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
+#define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
+#define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */
+#define ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
+
 /*
  * OMAP2 has a number of different interrupt controllers, each interrupt
  * controller is identified as its own "bank". Register definitions are
@@ -191,6 +196,44 @@ void __init ti816x_init_irq(void)
 	omap_init_irq(OMAP34XX_IC_BASE, 128);
 }
 
+static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
+{
+	u32 irqnr;
+
+	do {
+		irqnr = readl_relaxed(base_addr + 0x98);
+		if (irqnr)
+			goto out;
+
+		irqnr = readl_relaxed(base_addr + 0xb8);
+		if (irqnr)
+			goto out;
+
+		irqnr = readl_relaxed(base_addr + 0xd8);
+#ifdef CONFIG_SOC_OMAPTI816X
+		if (irqnr)
+			goto out;
+		irqnr = readl_relaxed(base_addr + 0xf8);
+#endif
+
+out:
+		if (!irqnr)
+			break;
+
+		irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
+		irqnr &= ACTIVEIRQ_MASK;
+
+		if (irqnr)
+			handle_IRQ(irqnr, regs);
+	} while (irqnr);
+}
+
+asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
+{
+	void __iomem *base_addr = OMAP2_IRQ_BASE;
+	omap_intc_handle_irq(base_addr, regs);
+}
+
 #ifdef CONFIG_ARCH_OMAP3
 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
 
@@ -263,4 +306,10 @@ void omap3_intc_resume_idle(void)
 	/* Re-enable autoidle */
 	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
 }
+
+asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
+{
+	void __iomem *base_addr = OMAP3_IRQ_BASE;
+	omap_intc_handle_irq(base_addr, regs);
+}
 #endif /* CONFIG_ARCH_OMAP3 */
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 30e1071..8b19a63 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -448,6 +448,8 @@ void omap_intc_restore_context(void);
 void omap3_intc_suspend(void);
 void omap3_intc_prepare_idle(void);
 void omap3_intc_resume_idle(void);
+void omap2_intc_handle_irq(struct pt_regs *regs);
+void omap3_intc_handle_irq(struct pt_regs *regs);
 #endif
 
 #include <mach/hardware.h>
-- 
1.7.0.4

[PATCH v2 15/16] ARM: omap2plus: convert to CONFIG_MULTI_IRQ_HANDLER

[Marc Zyngier]

Convert the omap2plus platforms to be using CONFIG_MULTI_IRQ_HANDLER.
Each machine is modified to provide either omap2_intc_handle_irq(),
omap3_intc_handle_irq() or gic_handle_irq().

This allows for a major cleanup, removing the MULTI_OMAP setup
from the interrupt path.

Tested on both Panda and IGEPv2 (single kernel image)

Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/mach-omap2/Kconfig                    |    1 +
 arch/arm/mach-omap2/board-2430sdp.c            |    1 +
 arch/arm/mach-omap2/board-3430sdp.c            |    1 +
 arch/arm/mach-omap2/board-3630sdp.c            |    1 +
 arch/arm/mach-omap2/board-4430sdp.c            |    2 +
 arch/arm/mach-omap2/board-am3517crane.c        |    1 +
 arch/arm/mach-omap2/board-am3517evm.c          |    1 +
 arch/arm/mach-omap2/board-apollon.c            |    1 +
 arch/arm/mach-omap2/board-cm-t35.c             |    2 +
 arch/arm/mach-omap2/board-cm-t3517.c           |    1 +
 arch/arm/mach-omap2/board-devkit8000.c         |    1 +
 arch/arm/mach-omap2/board-generic.c            |    1 +
 arch/arm/mach-omap2/board-h4.c                 |    1 +
 arch/arm/mach-omap2/board-igep0020.c           |    2 +
 arch/arm/mach-omap2/board-ldp.c                |    1 +
 arch/arm/mach-omap2/board-n8x0.c               |    3 +
 arch/arm/mach-omap2/board-omap3beagle.c        |    1 +
 arch/arm/mach-omap2/board-omap3evm.c           |    1 +
 arch/arm/mach-omap2/board-omap3logic.c         |    2 +
 arch/arm/mach-omap2/board-omap3pandora.c       |    1 +
 arch/arm/mach-omap2/board-omap3stalker.c       |    1 +
 arch/arm/mach-omap2/board-omap3touchbook.c     |    1 +
 arch/arm/mach-omap2/board-omap4panda.c         |    2 +
 arch/arm/mach-omap2/board-overo.c              |    1 +
 arch/arm/mach-omap2/board-rm680.c              |    1 +
 arch/arm/mach-omap2/board-rx51.c               |    1 +
 arch/arm/mach-omap2/board-zoom.c               |    2 +
 arch/arm/mach-omap2/include/mach/entry-macro.S |  137 ------------------------
 arch/arm/plat-omap/Kconfig                     |    1 +
 29 files changed, 36 insertions(+), 137 deletions(-)

diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 1aee224..4c5b01d 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -25,6 +25,7 @@ config ARCH_OMAP2
 	depends on ARCH_OMAP2PLUS
 	default y
 	select CPU_V6
+	select MULTI_IRQ_HANDLER
 
 config ARCH_OMAP3
 	bool "TI OMAP3"
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 4191743..56785c6 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -256,6 +256,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
 	.map_io		= omap_2430sdp_map_io,
 	.init_early	= omap2430_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_2430sdp_init,
 	.timer		= &omap2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 77142c1..1c17bd8 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -728,6 +728,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap_3430sdp_init,
 	.timer		= &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index f552305..b27aa85 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -215,6 +215,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3630_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap_sdp_init,
 	.timer		= &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index c404c5b..1b9e372 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -28,6 +28,7 @@
 
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -991,6 +992,7 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
 	.map_io		= omap_4430sdp_map_io,
 	.init_early	= omap4430_init_early,
 	.init_irq	= gic_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= omap_4430sdp_init,
 	.timer		= &omap4_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 7834536..0166f4e 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -98,6 +98,7 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
 	.map_io		= omap3_map_io,
 	.init_early	= am35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= am3517_crane_init,
 	.timer		= &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index d314f03..18cf2ce 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -491,6 +491,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
 	.map_io		= omap3_map_io,
 	.init_early	= am35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= am3517_evm_init,
 	.timer		= &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 868d5f0..ab6704f 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -350,6 +350,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
 	.map_io		= omap_apollon_map_io,
 	.init_early	= omap2420_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_apollon_init,
 	.timer		= &omap2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index bd1bcac..21a2436 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -634,6 +634,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= cm_t35_init,
 	.timer		= &omap3_timer,
 MACHINE_END
@@ -644,6 +645,7 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730")
 	.map_io         = omap3_map_io,
 	.init_early     = omap3630_init_early,
 	.init_irq       = omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine   = cm_t3730_init,
 	.timer          = &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 3f4dc66..1e2c52b 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -299,6 +299,7 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
 	.map_io		= omap3_map_io,
 	.init_early	= am35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= cm_t3517_init,
 	.timer		= &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 8d362dd..d8a02be 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -666,6 +666,7 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= devkit8000_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= devkit8000_init,
 	.timer		= &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 7ac5462..dd2a5c2 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -70,6 +70,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
 	.map_io		= omap_generic_map_io,
 	.init_early	= omap_generic_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_generic_init,
 	.timer		= &omap2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index f0ddc27..e75f09f 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -381,6 +381,7 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
 	.map_io		= omap_h4_map_io,
 	.init_early	= omap2420_init_early,
 	.init_irq	= omap_h4_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_h4_init,
 	.timer		= &omap2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index d0a3f78..b45d48d 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -672,6 +672,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= igep_init,
 	.timer		= &omap3_timer,
 MACHINE_END
@@ -682,6 +683,7 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= igep_init,
 	.timer		= &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index 5797917..4a53582 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -332,6 +332,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap_ldp_init,
 	.timer		= &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 4373a6a..49d9cc3 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -695,6 +695,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
 	.map_io		= n8x0_map_io,
 	.init_early	= omap2420_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= n8x0_init_machine,
 	.timer		= &omap2_timer,
 MACHINE_END
@@ -705,6 +706,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
 	.map_io		= n8x0_map_io,
 	.init_early	= omap2420_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= n8x0_init_machine,
 	.timer		= &omap2_timer,
 MACHINE_END
@@ -715,6 +717,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
 	.map_io		= n8x0_map_io,
 	.init_early	= omap2420_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= n8x0_init_machine,
 	.timer		= &omap2_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 0c49ee7..03af775 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -569,6 +569,7 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3_beagle_init_early,
 	.init_irq	= omap3_beagle_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3_beagle_init,
 	.timer		= &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index ec00b2e..f86c1e8 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -681,6 +681,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3_evm_init,
 	.timer		= &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 7c0f193..bd65196 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -208,6 +208,7 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3logic_init,
 	.timer		= &omap3_timer,
 MACHINE_END
@@ -217,6 +218,7 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3logic_init,
 	.timer		= &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index f7811f4..caf607c 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -606,6 +606,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3pandora_init,
 	.timer		= &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 8ab73af..ca02d2f 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -459,6 +459,7 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
 	.map_io			= omap3_map_io,
 	.init_early		= omap35xx_init_early,
 	.init_irq		= omap3_stalker_init_irq,
+	.handle_irq		= omap3_intc_handle_irq,
 	.init_machine		= omap3_stalker_init,
 	.timer			= &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 5e3e22f..7586e2c 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -404,6 +404,7 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
 	.init_irq	= omap3_touchbook_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3_touchbook_init,
 	.timer		= &omap3_secure_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 42d6168..41b2032 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -31,6 +31,7 @@
 
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -584,6 +585,7 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
 	.map_io		= omap4_panda_map_io,
 	.init_early	= omap4430_init_early,
 	.init_irq	= gic_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= omap4_panda_init,
 	.timer		= &omap4_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 4cf7aea..9865d8d 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -562,6 +562,7 @@ MACHINE_START(OVERO, "Gumstix Overo")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= overo_init,
 	.timer		= &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index d7c8f60..cf9e2db 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -155,6 +155,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
 	.map_io		= rm680_map_io,
 	.init_early	= omap3630_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= rm680_init,
 	.timer		= &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index e2e958a..f777d11 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -158,6 +158,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
 	.map_io		= rx51_map_io,
 	.init_early	= omap3430_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= rx51_init,
 	.timer		= &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index be6684d..011b2e3 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -135,6 +135,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap_zoom_init,
 	.timer		= &omap3_timer,
 MACHINE_END
@@ -145,6 +146,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3630_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap_zoom_init,
 	.timer		= &omap3_timer,
 MACHINE_END
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index feb90a1..56964a0 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -10,146 +10,9 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-#include <mach/hardware.h>
-#include <mach/io.h>
-#include <mach/irqs.h>
-#include <asm/hardware/gic.h>
-
-#include <plat/omap24xx.h>
-#include <plat/omap34xx.h>
-#include <plat/omap44xx.h>
-
-#include <plat/multi.h>
-
-#define OMAP2_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
-#define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
-#define OMAP4_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
-#define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */
-#define	ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
 
 		.macro	disable_fiq
 		.endm
 
 		.macro  arch_ret_to_user, tmp1, tmp2
 		.endm
-
-/*
- * Unoptimized irq functions for multi-omap2, 3 and 4
- */
-
-#ifdef MULTI_OMAP2
-		/*
-		 * Configure the interrupt base on the first interrupt.
-		 * See also omap_irq_base_init for setting omap_irq_base.
-		 */
-		.macro  get_irqnr_preamble, base, tmp
-		ldr	\base, =omap_irq_base	@ irq base address
-		ldr	\base, [\base, #0]	@ irq base value
-		.endm
-
-		/* Check the pending interrupts. Note that base already set */
-		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-		tst	\base, #0x100		@ gic address?
-		bne	4401f			@ found gic
-
-		/* Handle omap2 and omap3 */
-		ldr	\irqnr, [\base, #0x98] /* IRQ pending reg 1 */
-		cmp	\irqnr, #0x0
-		bne	9998f
-		ldr	\irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
-		cmp	\irqnr, #0x0
-		bne	9998f
-		ldr	\irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
-		cmp	\irqnr, #0x0
-		bne	9998f
-
-		/*
-		 * ti816x has additional IRQ pending register. Checking this
-		 * register on omap2 & omap3 has no effect (read as 0).
-		 */
-		ldr	\irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
-		cmp	\irqnr, #0x0
-9998:
-		ldrne	\irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
-		and	\irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
-		b	9999f
-
-		/* Handle omap4 */
-4401:		ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-		ldr     \tmp, =1021
-		bic     \irqnr, \irqstat, #0x1c00
-		cmp     \irqnr, #15
-		cmpcc   \irqnr, \irqnr
-		cmpne   \irqnr, \tmp
-		cmpcs   \irqnr, \irqnr
-9999:
-		.endm
-
-#ifdef CONFIG_SMP
-		/* We assume that irqstat (the raw value of the IRQ acknowledge
-		 * register) is preserved from the macro above.
-		 * If there is an IPI, we immediately signal end of interrupt
-		 * on the controller, since this requires the original irqstat
-		 * value which we won't easily be able to recreate later.
-		 */
-
-		.macro test_for_ipi, irqnr, irqstat, base, tmp
-		bic	\irqnr, \irqstat, #0x1c00
-		cmp	\irqnr, #16
-		it	cc
-		strcc	\irqstat, [\base, #GIC_CPU_EOI]
-		it	cs
-		cmpcs	\irqnr, \irqnr
-		.endm
-#endif	/* CONFIG_SMP */
-
-#else	/* MULTI_OMAP2 */
-
-
-/*
- * Optimized irq functions for omap2, 3 and 4
- */
-
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
-		.macro  get_irqnr_preamble, base, tmp
-#ifdef CONFIG_ARCH_OMAP2
-		ldr	\base, =OMAP2_IRQ_BASE
-#else
-		ldr	\base, =OMAP3_IRQ_BASE
-#endif
-		.endm
-
-		/* Check the pending interrupts. Note that base already set */
-		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-		ldr	\irqnr, [\base, #0x98] /* IRQ pending reg 1 */
-		cmp	\irqnr, #0x0
-		bne	9999f
-		ldr	\irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
-		cmp	\irqnr, #0x0
-		bne	9999f
-		ldr	\irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
-		cmp	\irqnr, #0x0
-#ifdef CONFIG_SOC_OMAPTI816X
-		bne	9999f
-		ldr	\irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
-		cmp	\irqnr, #0x0
-#endif
-9999:
-		ldrne	\irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
-		and	\irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
-
-		.endm
-#endif
-
-
-#ifdef CONFIG_ARCH_OMAP4
-#define HAVE_GET_IRQNR_PREAMBLE
-#include <asm/hardware/entry-macro-gic.S>
-
-		.macro  get_irqnr_preamble, base, tmp
-		ldr     \base, =OMAP4_IRQ_BASE
-		.endm
-
-#endif
-
-#endif	/* MULTI_OMAP2 */
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index fa62037..c39cbca 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -22,6 +22,7 @@ config ARCH_OMAP2PLUS
 	select CLKDEV_LOOKUP
 	select GENERIC_IRQ_CHIP
 	select OMAP_DM_TIMER
+	select MULTI_IRQ_HANDLER
 	help
 	  "Systems based on OMAP2, OMAP3 or OMAP4"
 
-- 
1.7.0.4

[PATCH v2 16/16] ARM: GIC: Make MULTI_IRQ_HANDLER mandatory

[Marc Zyngier]

Now that MULTI_IRQ_HANDLER is selected by all the in-tree
GIC users, make it mandatory and remove the unused macros.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 arch/arm/Kconfig                                |    3 -
 arch/arm/common/Kconfig                         |    1 +
 arch/arm/common/gic.c                           |    2 +-
 arch/arm/include/asm/hardware/entry-macro-gic.S |   60 -----------------------
 arch/arm/include/asm/hardware/gic.h             |    1 -
 arch/arm/mach-msm/Kconfig                       |    2 -
 arch/arm/mach-omap2/Kconfig                     |    1 +
 arch/arm/mach-tegra/Kconfig                     |    1 -
 arch/arm/mach-ux500/Kconfig                     |    1 -
 arch/arm/plat-omap/Kconfig                      |    1 -
 10 files changed, 3 insertions(+), 70 deletions(-)
 delete mode 100644 arch/arm/include/asm/hardware/entry-macro-gic.S

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0514264..d3e246c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -334,7 +334,6 @@ config ARCH_CNS3XXX
 	select ARM_GIC
 	select MIGHT_HAVE_PCI
 	select PCI_DOMAINS if PCI
-	select MULTI_IRQ_HANDLER
 	help
 	  Support for Cavium Networks CNS3XXX platform.
 
@@ -788,7 +787,6 @@ config ARCH_EXYNOS4
 	select HAVE_S3C_RTC if RTC_CLASS
 	select HAVE_S3C2410_I2C if I2C
 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
-	select MULTI_IRQ_HANDLER
 	help
 	  Samsung EXYNOS4 series based systems
 
@@ -911,7 +909,6 @@ config ARCH_ZYNQ
 	select ARM_AMBA
 	select ICST
 	select USE_OF
-	select MULTI_IRQ_HANDLER
 	help
 	  Support for Xilinx Zynq ARM Cortex A9 Platform
 endchoice
diff --git a/arch/arm/common/Kconfig b/arch/arm/common/Kconfig
index 114a432..de31997 100644
--- a/arch/arm/common/Kconfig
+++ b/arch/arm/common/Kconfig
@@ -1,5 +1,6 @@
 config ARM_GIC
 	select IRQ_PERCPU_DEVID
+	select MULTI_IRQ_HANDLER
 	bool
 
 config ARM_VIC
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index ef803d2..8f55cf3 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -39,7 +39,7 @@
 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 
 /* Address of GIC 0 CPU interface */
-void __iomem *gic_cpu_base_addr __read_mostly;
+static void __iomem *gic_cpu_base_addr __read_mostly;
 
 /*
  * Supported arch specific GIC irq extension.
diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S
deleted file mode 100644
index 74ebc80..0000000
--- a/arch/arm/include/asm/hardware/entry-macro-gic.S
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * arch/arm/include/asm/hardware/entry-macro-gic.S
- *
- * Low-level IRQ helper macros for GIC
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/gic.h>
-
-#ifndef HAVE_GET_IRQNR_PREAMBLE
-	.macro	get_irqnr_preamble, base, tmp
-	ldr	\base, =gic_cpu_base_addr
-	ldr	\base, [\base]
-	.endm
-#endif
-
-/*
- * The interrupt numbering scheme is defined in the
- * interrupt controller spec.  To wit:
- *
- * Interrupts 0-15 are IPI
- * 16-31 are local.  We allow 30 to be used for the watchdog.
- * 32-1020 are global
- * 1021-1022 are reserved
- * 1023 is "spurious" (no interrupt)
- *
- * A simple read from the controller will tell us the number of the highest
- * priority enabled interrupt.  We then just need to check whether it is in the
- * valid range for an IRQ (30-1020 inclusive).
- */
-
-	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-
-	ldr     \irqstat, [\base, #GIC_CPU_INTACK]
-	/* bits 12-10 = src CPU, 9-0 = int # */
-
-	ldr	\tmp, =1021
-	bic     \irqnr, \irqstat, #0x1c00
-	cmp     \irqnr, #15
-	cmpcc	\irqnr, \irqnr
-	cmpne	\irqnr, \tmp
-	cmpcs	\irqnr, \irqnr
-	.endm
-
-/* We assume that irqstat (the raw value of the IRQ acknowledge
- * register) is preserved from the macro above.
- * If there is an IPI, we immediately signal end of interrupt on the
- * controller, since this requires the original irqstat value which
- * we won't easily be able to recreate later.
- */
-
-	.macro test_for_ipi, irqnr, irqstat, base, tmp
-	bic	\irqnr, \irqstat, #0x1c00
-	cmp	\irqnr, #16
-	strcc	\irqstat, [\base, #GIC_CPU_EOI]
-	cmpcs	\irqnr, \irqnr
-	.endm
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 0f454c6..3411d37 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -33,7 +33,6 @@
 #define GIC_DIST_SOFTINT		0xf00
 
 #ifndef __ASSEMBLY__
-extern void __iomem *gic_cpu_base_addr;
 extern struct irq_chip gic_arch_extn;
 
 void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index ba36b74..ebde97f 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -50,7 +50,6 @@ config ARCH_MSM8X60
 	select GPIO_MSM_V2
 	select MSM_GPIOMUX
 	select MSM_SCM if SMP
-	select MULTI_IRQ_HANDLER
 
 config ARCH_MSM8960
 	bool "MSM8960"
@@ -61,7 +60,6 @@ config ARCH_MSM8960
 	select MSM_V2_TLMM
 	select MSM_GPIOMUX
 	select MSM_SCM if SMP
-	select MULTI_IRQ_HANDLER
 
 endchoice
 
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 4c5b01d..9e29f9d 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -36,6 +36,7 @@ config ARCH_OMAP3
 	select ARM_L1_CACHE_SHIFT_6 if !ARCH_OMAP4
 	select ARCH_HAS_OPP
 	select PM_OPP if PM
+	select MULTI_IRQ_HANDLER
 
 config ARCH_OMAP4
 	bool "TI OMAP4"
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index ba0ac3f..d82ebab 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -13,7 +13,6 @@ config ARCH_TEGRA_2x_SOC
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
 	select USB_ULPI if USB_SUPPORT
 	select USB_ULPI_VIEWPORT if USB_SUPPORT
-	select MULTI_IRQ_HANDLER
 	help
 	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index bb2b52b..a3e0c86 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -7,7 +7,6 @@ config UX500_SOC_COMMON
 	select HAS_MTU
 	select ARM_ERRATA_753970
 	select ARM_ERRATA_754322
-	select MULTI_IRQ_HANDLER
 
 menu "Ux500 SoC"
 
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index c39cbca..fa62037 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -22,7 +22,6 @@ config ARCH_OMAP2PLUS
 	select CLKDEV_LOOKUP
 	select GENERIC_IRQ_CHIP
 	select OMAP_DM_TIMER
-	select MULTI_IRQ_HANDLER
 	help
 	  "Systems based on OMAP2, OMAP3 or OMAP4"
 
-- 
1.7.0.4

[PATCH v2 00/16] Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER

[David Brown]

On Mon, Sep 26, 2011 at 12:02:19PM +0100, Marc Zyngier wrote:

> This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2
> and Harmony. Patches against next-20110926 plus my PPI series.

Tested on an msm8660.

Tested-by: David Brown <davidb@codeaurora.org>
Acked-by: David Brown <davidb@codeaurora.org>

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 00/16] Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER

[David Brown]

On Mon, Sep 26, 2011 at 01:20:07PM -0700, David Brown wrote:
> On Mon, Sep 26, 2011 at 12:02:19PM +0100, Marc Zyngier wrote:
> 
> > This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2
> > and Harmony. Patches against next-20110926 plus my PPI series.
> 
> Tested on an msm8660.
> 
> Tested-by: David Brown <davidb@codeaurora.org>
> Acked-by: David Brown <davidb@codeaurora.org>

Tested as well on msm8250.

David

-- 
Sent by an employee of the Qualcomm Innovation Center, Inc.
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.

[PATCH v2 16/16] ARM: GIC: Make MULTI_IRQ_HANDLER mandatory

[Shawn Guo]

On Mon, Sep 26, 2011 at 12:02:35PM +0100, Marc Zyngier wrote:
> Now that MULTI_IRQ_HANDLER is selected by all the in-tree
> GIC users, make it mandatory and remove the unused macros.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
>  arch/arm/Kconfig                                |    3 -
>  arch/arm/common/Kconfig                         |    1 +
>  arch/arm/common/gic.c                           |    2 +-
>  arch/arm/include/asm/hardware/entry-macro-gic.S |   60 -----------------------
>  arch/arm/include/asm/hardware/gic.h             |    1 -
>  arch/arm/mach-msm/Kconfig                       |    2 -
>  arch/arm/mach-omap2/Kconfig                     |    1 +
>  arch/arm/mach-tegra/Kconfig                     |    1 -
>  arch/arm/mach-ux500/Kconfig                     |    1 -
>  arch/arm/plat-omap/Kconfig                      |    1 -
>  10 files changed, 3 insertions(+), 70 deletions(-)
>  delete mode 100644 arch/arm/include/asm/hardware/entry-macro-gic.S
> 
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 0514264..d3e246c 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -334,7 +334,6 @@ config ARCH_CNS3XXX
>  	select ARM_GIC
>  	select MIGHT_HAVE_PCI
>  	select PCI_DOMAINS if PCI
> -	select MULTI_IRQ_HANDLER
>  	help
>  	  Support for Cavium Networks CNS3XXX platform.
>  
> @@ -788,7 +787,6 @@ config ARCH_EXYNOS4
>  	select HAVE_S3C_RTC if RTC_CLASS
>  	select HAVE_S3C2410_I2C if I2C
>  	select HAVE_S3C2410_WATCHDOG if WATCHDOG
> -	select MULTI_IRQ_HANDLER
>  	help
>  	  Samsung EXYNOS4 series based systems
>  
> @@ -911,7 +909,6 @@ config ARCH_ZYNQ
>  	select ARM_AMBA
>  	select ICST
>  	select USE_OF
> -	select MULTI_IRQ_HANDLER
>  	help
>  	  Support for Xilinx Zynq ARM Cortex A9 Platform
>  endchoice

Hi Marc,

I'm unsure about your base.  But I have the following platforms in
arch/arm/Kconfig selecting MULTI_IRQ_HANDLER at the end of your series,
which should also be removed from?

  ARCH_REALVIEW
  ARCH_VEXPRESS
  ARCH_PXA
  ARCH_SHMOBILE

-- 
Regards,
Shawn

[PATCH v2 16/16] ARM: GIC: Make MULTI_IRQ_HANDLER mandatory

[Marc Zyngier]

Hi Shawn,

On 27/09/11 04:43, Shawn Guo wrote:
> On Mon, Sep 26, 2011 at 12:02:35PM +0100, Marc Zyngier wrote:
>> Now that MULTI_IRQ_HANDLER is selected by all the in-tree
>> GIC users, make it mandatory and remove the unused macros.
>>
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>>  arch/arm/Kconfig                                |    3 -
>>  arch/arm/common/Kconfig                         |    1 +
>>  arch/arm/common/gic.c                           |    2 +-
>>  arch/arm/include/asm/hardware/entry-macro-gic.S |   60 -----------------------
>>  arch/arm/include/asm/hardware/gic.h             |    1 -
>>  arch/arm/mach-msm/Kconfig                       |    2 -
>>  arch/arm/mach-omap2/Kconfig                     |    1 +
>>  arch/arm/mach-tegra/Kconfig                     |    1 -
>>  arch/arm/mach-ux500/Kconfig                     |    1 -
>>  arch/arm/plat-omap/Kconfig                      |    1 -
>>  10 files changed, 3 insertions(+), 70 deletions(-)
>>  delete mode 100644 arch/arm/include/asm/hardware/entry-macro-gic.S
>>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index 0514264..d3e246c 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -334,7 +334,6 @@ config ARCH_CNS3XXX
>>  	select ARM_GIC
>>  	select MIGHT_HAVE_PCI
>>  	select PCI_DOMAINS if PCI
>> -	select MULTI_IRQ_HANDLER
>>  	help
>>  	  Support for Cavium Networks CNS3XXX platform.
>>  
>> @@ -788,7 +787,6 @@ config ARCH_EXYNOS4
>>  	select HAVE_S3C_RTC if RTC_CLASS
>>  	select HAVE_S3C2410_I2C if I2C
>>  	select HAVE_S3C2410_WATCHDOG if WATCHDOG
>> -	select MULTI_IRQ_HANDLER
>>  	help
>>  	  Samsung EXYNOS4 series based systems
>>  
>> @@ -911,7 +909,6 @@ config ARCH_ZYNQ
>>  	select ARM_AMBA
>>  	select ICST
>>  	select USE_OF
>> -	select MULTI_IRQ_HANDLER
>>  	help
>>  	  Support for Xilinx Zynq ARM Cortex A9 Platform
>>  endchoice
> 
> Hi Marc,
> 
> I'm unsure about your base.  But I have the following platforms in
> arch/arm/Kconfig selecting MULTI_IRQ_HANDLER at the end of your series,
> which should also be removed from?
> 
>   ARCH_REALVIEW
>   ARCH_VEXPRESS

These two can be indeed removed, as they are GIC users and GIC now
selects MULTI_IRQ_HANDLER directly. I'll fix the patch.

>   ARCH_PXA

PXA doesn't use the GIC, so it has to select MULTI_IRQ_HANDLER directly
as it used to before my patch.

>   ARCH_SHMOBILE

This one is caught in the middle. Only SMP shmobile platforms use the
GIC, but they all need MULTI_IRQ_HANDLER anyway, so keeping the option
selected doesn't hurt.

Cheers,

	M.
-- 
Jazz is not dead. It just smells funny...

[PATCH v2 00/16] Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER

[Marc Zyngier]

On 27/09/11 01:15, David Brown wrote:
> On Mon, Sep 26, 2011 at 01:20:07PM -0700, David Brown wrote:
>> On Mon, Sep 26, 2011 at 12:02:19PM +0100, Marc Zyngier wrote:
>>
>>> This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2
>>> and Harmony. Patches against next-20110926 plus my PPI series.
>>
>> Tested on an msm8660.
>>
>> Tested-by: David Brown <davidb@codeaurora.org>
>> Acked-by: David Brown <davidb@codeaurora.org>
> 
> Tested as well on msm8250.

Awesome. Thanks a lot for testing all of this David.

	M.
-- 
Jazz is not dead. It just smells funny...

[PATCH v2 16/16] ARM: GIC: Make MULTI_IRQ_HANDLER mandatory

[Shawn Guo]

On Tue, Sep 27, 2011 at 09:32:26AM +0100, Marc Zyngier wrote:
> Hi Shawn,
> 
> On 27/09/11 04:43, Shawn Guo wrote:
> > On Mon, Sep 26, 2011 at 12:02:35PM +0100, Marc Zyngier wrote:
> >> Now that MULTI_IRQ_HANDLER is selected by all the in-tree
> >> GIC users, make it mandatory and remove the unused macros.
> >>
> >> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> >> ---
> >>  arch/arm/Kconfig                                |    3 -
> >>  arch/arm/common/Kconfig                         |    1 +
> >>  arch/arm/common/gic.c                           |    2 +-
> >>  arch/arm/include/asm/hardware/entry-macro-gic.S |   60 -----------------------
> >>  arch/arm/include/asm/hardware/gic.h             |    1 -
> >>  arch/arm/mach-msm/Kconfig                       |    2 -
> >>  arch/arm/mach-omap2/Kconfig                     |    1 +
> >>  arch/arm/mach-tegra/Kconfig                     |    1 -
> >>  arch/arm/mach-ux500/Kconfig                     |    1 -
> >>  arch/arm/plat-omap/Kconfig                      |    1 -
> >>  10 files changed, 3 insertions(+), 70 deletions(-)
> >>  delete mode 100644 arch/arm/include/asm/hardware/entry-macro-gic.S
> >>
> >> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> >> index 0514264..d3e246c 100644
> >> --- a/arch/arm/Kconfig
> >> +++ b/arch/arm/Kconfig
> >> @@ -334,7 +334,6 @@ config ARCH_CNS3XXX
> >>  	select ARM_GIC
> >>  	select MIGHT_HAVE_PCI
> >>  	select PCI_DOMAINS if PCI
> >> -	select MULTI_IRQ_HANDLER
> >>  	help
> >>  	  Support for Cavium Networks CNS3XXX platform.
> >>  
> >> @@ -788,7 +787,6 @@ config ARCH_EXYNOS4
> >>  	select HAVE_S3C_RTC if RTC_CLASS
> >>  	select HAVE_S3C2410_I2C if I2C
> >>  	select HAVE_S3C2410_WATCHDOG if WATCHDOG
> >> -	select MULTI_IRQ_HANDLER
> >>  	help
> >>  	  Samsung EXYNOS4 series based systems
> >>  
> >> @@ -911,7 +909,6 @@ config ARCH_ZYNQ
> >>  	select ARM_AMBA
> >>  	select ICST
> >>  	select USE_OF
> >> -	select MULTI_IRQ_HANDLER
> >>  	help
> >>  	  Support for Xilinx Zynq ARM Cortex A9 Platform
> >>  endchoice
> > 
> > Hi Marc,
> > 
> > I'm unsure about your base.  But I have the following platforms in
> > arch/arm/Kconfig selecting MULTI_IRQ_HANDLER at the end of your series,
> > which should also be removed from?
> > 
> >   ARCH_REALVIEW
> >   ARCH_VEXPRESS
> 
> These two can be indeed removed, as they are GIC users and GIC now
> selects MULTI_IRQ_HANDLER directly. I'll fix the patch.
> 
> >   ARCH_PXA
> 
> PXA doesn't use the GIC, so it has to select MULTI_IRQ_HANDLER directly
> as it used to before my patch.
> 
Ah, yes.  I missed that the MULTI_IRQ_HANDLER was selected by ARM_GIC
in arch/arm/common/Kconfig.

Regards,
Shawn

> >   ARCH_SHMOBILE
> 
> This one is caught in the middle. Only SMP shmobile platforms use the
> GIC, but they all need MULTI_IRQ_HANDLER anyway, so keeping the option
> selected doesn't hurt.
> 
> Cheers,
> 
> 	M.
> -- 
> Jazz is not dead. It just smells funny...
> 

[PATCH v2 00/16] Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER

[Shawn Guo]

On Mon, Sep 26, 2011 at 12:02:19PM +0100, Marc Zyngier wrote:
> In order to support multiple primary interrupt controllers in the same
> image, it is necessary to use the MULTI_IRQ_HANDLER config option.
> 
> This patch series makes a first step in that direction by:
> - having the GIC code to provides a global handler,
> - make GIC users to provide this handler from their machine descriptor.
> 
> A side effect of this is that it forces OMAP2/3 platforms to be
> converted too in order to preserve the MULTI_OMAP feature. This leads
> to a certain simplification of the interrupt handling for the
> OMAP2/3/4 platforms.
> 
> The primary IRQ handlers have been written in C, and the performance
> degradation is hardly noticeable. Should some tests reveal a major
> increase in latency, it is always possible to restore the ASM version.
> 
> This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2
> and Harmony. Patches against next-20110926 plus my PPI series.
> 
> From v1:
> - Add forgotten patch to make global handler and MULTI_IRQ_HANDLER
>   mutually exclusive.
> - Introduce handle_IPI(), which is similar to do_IP() and callable
>   from C code.
> 
> Marc Zyngier (16):
>   ARM: Make global handler and CONFIG_MULTI_IRQ_HANDLER mutually
>     exclusive
>   ARM: smp: Add an IPI handler callable from C code
>   ARM: GIC: Add global gic_handle_irq() function
>   ARM: RealView: convert to CONFIG_MULTI_IRQ_HANDLER
>   ARM: VExpress: convert to CONFIG_MULTI_IRQ_HANDLER
>   ARM: msm: convert SMP platforms to CONFIG_MULTI_IRQ_HANDLER
>   ARM: GIC: Add global gic_handle_irq_offset() function
>   ARM: exynos4: convert to CONFIG_MULTI_IRQ_HANDLER
>   ARM: tegra2: convert to CONFIG_MULTI_IRQ_HANDLER
>   ARM: ux500: convert to CONFIG_MULTI_IRQ_HANDLER
>   ARM: shmobile: convert smp platforms to gic_handle_irq()
>   ARM: cns3xxx: convert to CONFIG_MULTI_IRQ_HANDLER
>   ARM: zynq: convert to CONFIG_MULTI_IRQ_HANDLER
>   ARM: omap2/3: Add global omap2/3_intc_handle_irq() functions
>   ARM: omap2plus: convert to CONFIG_MULTI_IRQ_HANDLER
>   ARM: GIC: Make MULTI_IRQ_HANDLER mandatory
> 
On imx6q:

Tested-by: Shawn Guo <shawn.guo@linaro.org>

-- 
Regards,
Shawn

[PATCH v2 00/16] Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER

[Marc Zyngier]

On 27/09/11 11:20, Shawn Guo wrote:
> On Mon, Sep 26, 2011 at 12:02:19PM +0100, Marc Zyngier wrote:
>> In order to support multiple primary interrupt controllers in the same
>> image, it is necessary to use the MULTI_IRQ_HANDLER config option.
>>
>> This patch series makes a first step in that direction by:
>> - having the GIC code to provides a global handler,
>> - make GIC users to provide this handler from their machine descriptor.
>>
>> A side effect of this is that it forces OMAP2/3 platforms to be
>> converted too in order to preserve the MULTI_OMAP feature. This leads
>> to a certain simplification of the interrupt handling for the
>> OMAP2/3/4 platforms.
>>
>> The primary IRQ handlers have been written in C, and the performance
>> degradation is hardly noticeable. Should some tests reveal a major
>> increase in latency, it is always possible to restore the ASM version.
>>
>> This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2
>> and Harmony. Patches against next-20110926 plus my PPI series.
>>
>> From v1:
>> - Add forgotten patch to make global handler and MULTI_IRQ_HANDLER
>>   mutually exclusive.
>> - Introduce handle_IPI(), which is similar to do_IP() and callable
>>   from C code.
>>
>> Marc Zyngier (16):
>>   ARM: Make global handler and CONFIG_MULTI_IRQ_HANDLER mutually
>>     exclusive
>>   ARM: smp: Add an IPI handler callable from C code
>>   ARM: GIC: Add global gic_handle_irq() function
>>   ARM: RealView: convert to CONFIG_MULTI_IRQ_HANDLER
>>   ARM: VExpress: convert to CONFIG_MULTI_IRQ_HANDLER
>>   ARM: msm: convert SMP platforms to CONFIG_MULTI_IRQ_HANDLER
>>   ARM: GIC: Add global gic_handle_irq_offset() function
>>   ARM: exynos4: convert to CONFIG_MULTI_IRQ_HANDLER
>>   ARM: tegra2: convert to CONFIG_MULTI_IRQ_HANDLER
>>   ARM: ux500: convert to CONFIG_MULTI_IRQ_HANDLER
>>   ARM: shmobile: convert smp platforms to gic_handle_irq()
>>   ARM: cns3xxx: convert to CONFIG_MULTI_IRQ_HANDLER
>>   ARM: zynq: convert to CONFIG_MULTI_IRQ_HANDLER
>>   ARM: omap2/3: Add global omap2/3_intc_handle_irq() functions
>>   ARM: omap2plus: convert to CONFIG_MULTI_IRQ_HANDLER
>>   ARM: GIC: Make MULTI_IRQ_HANDLER mandatory
>>
> On imx6q:
> 
> Tested-by: Shawn Guo <shawn.guo@linaro.org>
> 

Thanks for testing.

	M.
-- 
Jazz is not dead. It just smells funny...

[PATCH v2 10/16] ARM: ux500: convert to CONFIG_MULTI_IRQ_HANDLER

[Linus Walleij]

On Mon, Sep 26, 2011 at 1:02 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:

> Convert the ux500 platforms to be using the gic_handle_irq
> function as their primary interrupt handler.
>
> Cc: Linus Walleij <linus.walleij@stericsson.com>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

Seems straight-forward provided the first patch is working
good so:
Acked-by: Linus Walleij <linus.walleij@linaro.org>

Thanks,
Linus Walleij

[PATCH v2 10/16] ARM: ux500: convert to CONFIG_MULTI_IRQ_HANDLER

[Marc Zyngier]

On 27/09/11 12:47, Linus Walleij wrote:
> On Mon, Sep 26, 2011 at 1:02 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> 
>> Convert the ux500 platforms to be using the gic_handle_irq
>> function as their primary interrupt handler.
>>
>> Cc: Linus Walleij <linus.walleij@stericsson.com>
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> 
> Seems straight-forward provided the first patch is working
> good so:
> Acked-by: Linus Walleij <linus.walleij@linaro.org>

Thanks Linus!

	M.
-- 
Jazz is not dead. It just smells funny...

[PATCH v2 00/16] Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER

[Tony Lindgren]

Hi Marc,

* Marc Zyngier <marc.zyngier@arm.com> [110926 07:02]:
> In order to support multiple primary interrupt controllers in the same
> image, it is necessary to use the MULTI_IRQ_HANDLER config option.
> 
> This patch series makes a first step in that direction by:
> - having the GIC code to provides a global handler,
> - make GIC users to provide this handler from their machine descriptor.
> 
> A side effect of this is that it forces OMAP2/3 platforms to be
> converted too in order to preserve the MULTI_OMAP feature. This leads
> to a certain simplification of the interrupt handling for the
> OMAP2/3/4 platforms.

That's nice :)
 
> The primary IRQ handlers have been written in C, and the performance
> degradation is hardly noticeable. Should some tests reveal a major
> increase in latency, it is always possible to restore the ASM version.
> 
> This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2
> and Harmony. Patches against next-20110926 plus my PPI series.

I gave this series a quick try, it works except with all the patches
applied omap2plus_defconfig will failt to boot on omap4. It seems that
the issue is somewhere in the GIC related patches, the last one just
enables the MULTI_IRQ..

Care to give it a try on your Panda and see if omap2plus_defconfig
works for you with this series?

Looks like disabling CONFIG_SMP made it omap4 boot again.

Regards,

Tony 

[PATCH v2 00/16] Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [110927 16:19]:
> 
> * Marc Zyngier <marc.zyngier@arm.com> [110926 07:02]:
> > 
> > This series has been tested on VE (A9, A5, A15), PB11MP, Panda, IGEPv2
> > and Harmony. Patches against next-20110926 plus my PPI series.
> 
> I gave this series a quick try, it works except with all the patches
> applied omap2plus_defconfig will failt to boot on omap4. It seems that
> the issue is somewhere in the GIC related patches, the last one just
> enables the MULTI_IRQ..
> 
> Care to give it a try on your Panda and see if omap2plus_defconfig
> works for you with this series?
> 
> Looks like disabling CONFIG_SMP made it omap4 boot again.

Nevermind, looks like I was missing the PPI series.. No wonder
I had to do some rebasing to get the patches to apply..

Booting just fine now, will ack some patches separately. Gave
the PPI + MULTI_IRQ series a quick boot test on n800, 2430sdp,
n900, zoom3 and blaze. So that pretty much covers omap2, 3 & 4.

Regards,

Tony

[PATCH v2 01/16] ARM: Make global handler and CONFIG_MULTI_IRQ_HANDLER mutually exclusive

[Tony Lindgren]

* Marc Zyngier <marc.zyngier@arm.com> [110926 03:30]:
> Even when CONFIG_MULTI_IRQ_HANDLER is selected, the core code
> requires the arch_irq_handler_default macro to be defined as
> a fallback.
> 
> It turns out nobody is using that particular feature as both PXA
> and shmobile have all their machine descriptors populated with
> the interrupt handler, leaving unused code (or empty macros) in
> their entry-macro.S file just to be able to compile entry-armv.S.
> 
> Make CONFIG_MULTI_IRQ_HANDLER exclusive wrt arch_irq_handler_default,
> which allows to remove one test from the hot path. Also cleanup both
> PXA and shmobile entry-macro.S.
> 
> Cc: Eric Miao <eric.y.miao@gmail.com>
> Cc: Paul Mundt <lethal@linux-sh.org>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

Tested-by: Tony Lindgren <tony@atomide.com>

[PATCH v2 02/16] ARM: smp: Add an IPI handler callable from C code

[Tony Lindgren]

* Marc Zyngier <marc.zyngier@arm.com> [110926 03:33]:
> In order to be able to handle IPI directly from C code instead of
> assembly code, introduce handle_IPI(), which is modeled after handle_IRQ().
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

Tested-by: Tony Lindgren <tony@atomide.com>

[PATCH v2 03/16] ARM: GIC: Add global gic_handle_irq() function

[Tony Lindgren]

* Marc Zyngier <marc.zyngier@arm.com> [110926 03:33]:
> Provide the GIC code with a low level handler that can be used
> by platforms using CONFIG_MULTI_IRQ_HANDLER. Though the handler is
> written in C, the compiled code doesn't feel much slower than its
> assembly counterpart (at least with my gcc 4.4.1).
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

Tested-by: Tony Lindgren <tony@atomide.com>

[PATCH v2 14/16] ARM: omap2/3: Add global omap2/3_intc_handle_irq() functions

[Tony Lindgren]

* Marc Zyngier <marc.zyngier@arm.com> [110926 07:02]:
> Provide the OMAP2/3 IRQ code with low level handlers that can be used
> by platforms using CONFIG_MULTI_IRQ_HANDLER. Though the handlers are
> written in C, the compiled code looks very similar to its assembly
> counterpart (at least with my gcc 4.4.1).
> 
> Cc: Tony Lindgren <tony@atomide.com>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

Nice, thanks for doing this!

Tested-by: Tony Lindgren <tony@atomide.com>

[PATCH v2 15/16] ARM: omap2plus: convert to CONFIG_MULTI_IRQ_HANDLER

[Tony Lindgren]

* Marc Zyngier <marc.zyngier@arm.com> [110926 07:02]:
> Convert the omap2plus platforms to be using CONFIG_MULTI_IRQ_HANDLER.
> Each machine is modified to provide either omap2_intc_handle_irq(),
> omap3_intc_handle_irq() or gic_handle_irq().
> 
> This allows for a major cleanup, removing the MULTI_OMAP setup
> from the interrupt path.
> 
> Tested on both Panda and IGEPv2 (single kernel image)
...

> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -25,6 +25,7 @@ config ARCH_OMAP2
>  	depends on ARCH_OMAP2PLUS
>  	default y
>  	select CPU_V6
> +	select MULTI_IRQ_HANDLER
>  
>  config ARCH_OMAP3
>  	bool "TI OMAP3"

This one selects it only for ARCH_OMAP2, not for ARCH_OMAP2PLUS.

This might require minor merging with the cleanup I've posted, but
that should be trivial.

Other than that:

Tested-by: Tony Lindgren <tony@atomide.com>

[PATCH v2 16/16] ARM: GIC: Make MULTI_IRQ_HANDLER mandatory

[Tony Lindgren]

* Marc Zyngier <marc.zyngier@arm.com> [110926 03:35]:
> Now that MULTI_IRQ_HANDLER is selected by all the in-tree
> GIC users, make it mandatory and remove the unused macros.
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

Tested-by: Tony Lindgren <tony@atomide.com>

[PATCH v2 07/16] ARM: GIC: Add global gic_handle_irq_offset() function

[Rob Herring]

On 09/26/2011 06:02 AM, Marc Zyngier wrote:
> Similar to gic_handle_irq(), gic_handle_irq_offset() is provided
> for those platform who insist on having their GIC base interrupt
> at something different from zero. At the moment, Exynos4 is the
> only one...
> 
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
>  arch/arm/common/gic.c               |   24 ++++++++++++++++++++++++
>  arch/arm/include/asm/hardware/gic.h |    1 +
>  2 files changed, 25 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
> index 5a22896..ef803d2 100644
> --- a/arch/arm/common/gic.c
> +++ b/arch/arm/common/gic.c
> @@ -232,6 +232,30 @@ asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
>  	} while (1);
>  }
>  
> +asmlinkage void __exception_irq_entry gic_handle_irq_offset(struct pt_regs *regs)
> +{
> +	u32 irqstat, irqnr;
> +	u32 offset = gic_data[0].irq_offset;
> +
> +	do {
> +		irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
> +		irqnr = irqstat & ~0x1c00;
> +
> +		if (likely(irqnr > 15 && irqnr < 1021)) {
> +			handle_IRQ(irqnr + offset, regs);

Can't this be combined with gic_handle_irq. irq_offset will be 0 in that
case. Really, irq_domain should be used here.

Rob

> +			continue;
> +		}
> +		if (irqnr < 16) {
> +			writel_relaxed(irqstat, gic_cpu_base_addr + GIC_CPU_EOI);
> +#ifdef CONFIG_SMP
> +			handle_IPI(irqnr, regs);
> +#endif
> +			continue;
> +		}
> +		break;
> +	} while (1);
> +}
> +
>  static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
>  {
>  	struct gic_chip_data *chip_data = irq_get_handler_data(irq);
> diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
> index 45e4ab4..0f454c6 100644
> --- a/arch/arm/include/asm/hardware/gic.h
> +++ b/arch/arm/include/asm/hardware/gic.h
> @@ -39,6 +39,7 @@ extern struct irq_chip gic_arch_extn;
>  void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
>  void gic_secondary_init(unsigned int);
>  void gic_handle_irq(struct pt_regs *regs);
> +void gic_handle_irq_offset(struct pt_regs *regs);
>  void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
>  void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
>  

[PATCH v2 07/16] ARM: GIC: Add global gic_handle_irq_offset() function

[Marc Zyngier]

On 28/09/11 16:50, Rob Herring wrote:
> On 09/26/2011 06:02 AM, Marc Zyngier wrote:
>> Similar to gic_handle_irq(), gic_handle_irq_offset() is provided
>> for those platform who insist on having their GIC base interrupt
>> at something different from zero. At the moment, Exynos4 is the
>> only one...
>>
>> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
>> ---
>>  arch/arm/common/gic.c               |   24 ++++++++++++++++++++++++
>>  arch/arm/include/asm/hardware/gic.h |    1 +
>>  2 files changed, 25 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
>> index 5a22896..ef803d2 100644
>> --- a/arch/arm/common/gic.c
>> +++ b/arch/arm/common/gic.c
>> @@ -232,6 +232,30 @@ asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
>>  	} while (1);
>>  }
>>  
>> +asmlinkage void __exception_irq_entry gic_handle_irq_offset(struct pt_regs *regs)
>> +{
>> +	u32 irqstat, irqnr;
>> +	u32 offset = gic_data[0].irq_offset;
>> +
>> +	do {
>> +		irqstat = readl_relaxed(gic_cpu_base_addr + GIC_CPU_INTACK);
>> +		irqnr = irqstat & ~0x1c00;
>> +
>> +		if (likely(irqnr > 15 && irqnr < 1021)) {
>> +			handle_IRQ(irqnr + offset, regs);
> 
> Can't this be combined with gic_handle_irq. irq_offset will be 0 in that
> case. Really, irq_domain should be used here.

I completely agree on the irq_domain thing. The reason I introduced two
functions is to keep things as similar as possible to the old
implementation, and also to save a memory reference + addition on the
hot path of all the other platforms.

If we all agree that keeping that piece of code as generic as possible
is the way forward, then I'll happily drop that patch and let Exynos4
use the same handler.

Cheers,

	M.
-- 
Jazz is not dead. It just smells funny...