From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefano Babic Date: Fri, 14 Oct 2011 15:29:28 +0200 Subject: [U-Boot] [PATCH V2 2/3] mx31: add ESD control registers In-Reply-To: <1318579550-22843-2-git-send-email-helmut.raiger@hale.at> References: <1318579550-22843-1-git-send-email-helmut.raiger@hale.at> <1318579550-22843-2-git-send-email-helmut.raiger@hale.at> Message-ID: <4E983938.8030206@denx.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 10/14/2011 10:05 AM, Helmut Raiger wrote: > This allows to initialize DDR memory in C code. > Currently all mx31 boards use assembler code (lowlevel_init.S) > > Signed-off-by: Helmut Raiger > --- > V2: new in V2 > > arch/arm/include/asm/arch-mx31/imx-regs.h | 13 +++++++++++++ > 1 files changed, 13 insertions(+), 0 deletions(-) > > diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h > index 40abc34..f7a39f1 100644 > --- a/arch/arm/include/asm/arch-mx31/imx-regs.h > +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h > @@ -484,6 +484,17 @@ struct mx31_weim { > struct mx31_weim_cscr cscr[6]; > }; > > +/* ESD control registers */ > +struct esdc_regs { > + u32 ctl0; > + u32 cfg0; > + u32 ctl1; > + u32 cfg1; > + u32 misc; > + u32 dly[5]; > + u32 dlyl; > +}; > + > #endif > > #define __REG(x) (*((volatile u32 *)(x))) > @@ -548,6 +559,8 @@ struct mx31_weim { > #define ESDCTL_BL(x) ((x) << 7) > #define ESDCTL_PRCT(x) ((x) << 0) > > +#define ESDCTL_BASE_ADDR 0xB8001000 > + > /* 13 fields of the upper CS control register */ > #define CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \ > cnc, wsc, ew, wws, edc) \ Acked-by: Stefano Babic Best regards, Stefano Babic -- ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office at denx.de =====================================================================