From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:43327) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RdcgY-0006Ye-58 for qemu-devel@nongnu.org; Thu, 22 Dec 2011 02:03:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1RdcgW-0006b0-DM for qemu-devel@nongnu.org; Thu, 22 Dec 2011 02:03:26 -0500 Received: from mailout2.w1.samsung.com ([210.118.77.12]:61707) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1RdcgW-0006au-77 for qemu-devel@nongnu.org; Thu, 22 Dec 2011 02:03:24 -0500 Received: from euspt1 (mailout2.w1.samsung.com [210.118.77.12]) by mailout2.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTP id <0LWL00FKBFLK5W@mailout2.w1.samsung.com> for qemu-devel@nongnu.org; Thu, 22 Dec 2011 07:03:20 +0000 (GMT) Received: from [106.109.8.48] by spt1.w1.samsung.com (iPlanet Messaging Server 5.2 Patch 2 (built Jul 14 2004)) with ESMTPA id <0LWL00C5MFLJ8F@spt1.w1.samsung.com> for qemu-devel@nongnu.org; Thu, 22 Dec 2011 07:03:20 +0000 (GMT) Date: Thu, 22 Dec 2011 11:03:18 +0400 From: Evgeny Voevodin In-reply-to: Message-id: <4EF2D636.6000609@samsung.com> MIME-version: 1.0 Content-type: text/plain; charset=UTF-8; format=flowed Content-transfer-encoding: 7BIT References: <1324295617-5798-1-git-send-email-e.voevodin@samsung.com> <1324295617-5798-5-git-send-email-e.voevodin@samsung.com> <4EF1F681.7090805@samsung.com> Subject: Re: [Qemu-devel] [PATCH v4 04/11] ARM: exynos4210: IRQ subsystem support. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: m.kozlov@samsung.com, qemu-devel@nongnu.org, d.solodkiy@samsung.com On 12/22/2011 12:31 AM, Peter Maydell wrote: > On 21 December 2011 15:08, Evgeny Voevodin wrote: >> On 12/21/2011 05:50 PM, Peter Maydell wrote: >>> arm_gic.c exposes the CPU and distributor interfaces as their own >>> memory regions now -- you shouldn't need any of this intermediate >>> layer of functions. >> These functions are not actually for splitting CPU and Distributer >> interfaces. >> In our board we have two GICs - internal and external. Internal GIC is >> completely >> matching arm_gic.c. >> >> Internal GIC CPU[n] and Distributer[n] interfaces are at 0x100 and 0x1000 >> offsets from >> 0x10500000 base. >> >> But external GIC is different. >> It's CPU[0] interface is at 0x0 offset from 0x10480000 base >> and >> CPU[1] interface is at 0x8000 offset from 0x10480000 base >> >> It's Distributer[0] interface is at 0x0 offset from 0x10490000 base >> and >> Distributer[1] interface is at 0x8000 offset from 0x10490000 base >> >> [n] - is corresponding to SMP CPU Core. >> >> So, we need these wrapper functions for External GIC. > I don't understand this reasoning. If there are two GICs then > you should just instantiate two GIC devices and map and/or alias > their memory regions at the right addresses. The reason why > the distributor and CPU interfaces are exposed as multiple > memory regions is exactly so you can put them at different > offsets for different boards/CPUs. If arm_gic doesn't > provide suitably split up memory regions then it should be > fixed to do so. > > -- PMM > One of our GICs (internal) plus private memory region is represented as "a9mpcore_priv" device. This implementation fits the documentation. Second GIC (external) is represented as "exynos4210.gic" with splitted mapping for CPU (0x10480000) and Distributer (0x10490000) (we used arm_gic.c availability to split CPU and Distributer memories). The reason for creation of this device with it's own read/write functions is: CPU and Distributer registers which are banked per SMP Core in internal GIC are not banked in external GIC and their offsets could not be used as is with arm_gic.c. External GIC registers in comparison to Internal GIC registers are moved from base by offset n * 0x8000 for each SMP Core, where n is SMP Core index. The rest functionality of external GIC is identical to internal GIC and arm_gic.c. So, we can use arm_gic.c in external GIC if we will pass correct offsets to it's read/write functions. To obtain arm_gic.c compliant addresses, we introduced exynos4210_gic/dist_read/write functions. They obtain arm_gic.c compliant offsets for primary and secondary SMP Cores and simply call arm_gic.c functions to do all the work. -- Kind regards, Evgeny Voevodin, Leading Software Engineer, ASWG, Moscow R&D center, Samsung Electronics e-mail: e.voevodin@samsung.com