From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:59086) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ReFsj-0000we-5L for qemu-devel@nongnu.org; Fri, 23 Dec 2011 19:54:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ReFsi-0005C5-AU for qemu-devel@nongnu.org; Fri, 23 Dec 2011 19:54:37 -0500 Received: from smtp171.dfw.emailsrvr.com ([67.192.241.171]:53156) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ReFsi-0005By-7M for qemu-devel@nongnu.org; Fri, 23 Dec 2011 19:54:36 -0500 Message-ID: <4EF522CA.4040106@calxeda.com> Date: Fri, 23 Dec 2011 18:54:34 -0600 From: Rob Herring MIME-Version: 1.0 References: <1324578014-24746-1-git-send-email-mark.langsdorf@calxeda.com> <1324578014-24746-10-git-send-email-mark.langsdorf@calxeda.com> In-Reply-To: <1324578014-24746-10-git-send-email-mark.langsdorf@calxeda.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 9/9] arm: increase a9mp interrupts to 160 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Mark Langsdorf Cc: kwolf@redhat.com, peter.maydell@linaro.org, qemu-devel@nongnu.org, paul@codesourcery.com Mark, On 12/22/2011 12:20 PM, Mark Langsdorf wrote: > From: Rob Herring > > Signed-off-by: Rob Herring > Signed-off-by: Mark Langsdorf > --- > hw/a9mpcore.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c > index 875ae98..93b0498 100644 > --- a/hw/a9mpcore.c > +++ b/hw/a9mpcore.c > @@ -13,7 +13,7 @@ > /* Configuration for arm_gic.c: > * number of external IRQ lines, max number of CPUs, how to ID current CPU > */ > -#define GIC_NIRQ 96 > +#define GIC_NIRQ 160 > #define NCPU 4 This needs to be run-time. The value gets put in a register and read by the OS. It breaks platforms expecting 96 irqs. Rob