From: Albert ARIBAUD <albert.u.boot@aribaud.net>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 3/5] msm7x30: Add support for Qualcomm msm7630 soc
Date: Wed, 29 Feb 2012 01:00:43 +0100 [thread overview]
Message-ID: <4F4D6AAB.4090709@aribaud.net> (raw)
In-Reply-To: <1329361163-11228-4-git-send-email-mohamed.haneef@lntinfotech.com>
Hi Mohamed,
Le 16/02/2012 03:59, mohamed.haneef at lntinfotech.com a ?crit :
> +#define BIT(n) (1<< (n))
> +#define VREG_CONFIG (BIT(7) | BIT(6))
BIT() is not used elsewhere. It would be simpler not to define it and to
define VREG_CONFIG as (3 << 6).
Besides, isn't that rather a VREG_CONFIG_MASK?
> +void set_vector_base(unsigned long addr)
> +{
> + __asm__ volatile ("mcr p15, 0, %0, c12, c0, 0" : : "r" (addr));
> +}
Where is it used?
> +int dram_init(void)
> +{
> + /* We do not initialise DRAM here. We just query the size */
> + gd->ram_size = PHYS_SDRAM_1_SIZE;
> + /* Now check it dynamically */
It says 'check it dynamically', but does not seem to. Any reason not to
detect RAM size dynamically?
> +static struct gpioregs *find_gpio(unsigned n, unsigned *bit)
> +{
> + if (n> 150) {
> + *bit = 1<< (n - 151);
> + return GPIO_REGS + 7;
> + }
> + if (n> 133) {
> + *bit = 1<< (n - 134);
> + return GPIO_REGS + 6;
> + }
> + if (n> 106) {
> + *bit = 1<< (n - 107);
> + return GPIO_REGS + 5;
> + }
> + if (n> 94) {
> + *bit = 1<< (n - 95);
> + return GPIO_REGS + 4;
> + }
> + if (n> 67) {
> + *bit = 1<< (n - 68);
> + return GPIO_REGS + 3;
> + }
> + if (n> 43) {
> + *bit = 1<< (n - 44);
> + return GPIO_REGS + 2;
> + }
> + if (n> 15) {
> + *bit = 1<< (n - 16);
> + return GPIO_REGS + 1;
> + }
> + *bit = 1<< n;
> + return GPIO_REGS + 0;
> +}
> +
> +int gpio_config(unsigned n, unsigned flags)
> +{
> + struct gpioregs *r;
> + unsigned b;
> + unsigned v;
> +
> + r = find_gpio(n,&b);
> + if (!r)
> + return -1;
> +
> + v = readl(r->oe);
> + if (flags& GPIO_OUTPUT)
> + writel(v | b, r->oe);
> + else
> + writel(v& (~b), r->oe);
> + return 0;
> +}
> +
> +void gpio_set(unsigned n, unsigned on)
> +{
> + struct gpioregs *r;
> + unsigned b;
> + unsigned v;
> +
> + r = find_gpio(n,&b);
> + if (r == 0)
> + return;
> +
> + v = readl(r->out);
> + if (on)
> + writel(v | b, r->out);
> + else
> + writel(v& (~b), r->out);
> +}
> +
> +int gpio_get(unsigned n)
> +{
> + struct gpioregs *r;
> + unsigned b;
> +
> + r = find_gpio(n,&b);
> + if (r == 0)
> + return 0;
> + return (readl(r->in)& b) ? 1 : 0;
> +}
> +
> +void platform_config_interleaved_mode_gpios(void)
> +{
> + /* configure EB2_CS1 through GPIO86 */
> + writel(GPIO_ALT_FUNC_PAGE_REG, 0x56);
> + writel(GPIO_ALT_FUNC_CFG_REG, 0x04);
> + /* configure the EBI2_BUSY1_N through GPIO115 */
> + writel(GPIO_ALT_FUNC_PAGE_REG, 0x73);
> + writel(GPIO_ALT_FUNC_CFG_REG, 0x08);
> +}
> +
> +/* Enables all gpios passed in table*/
> +int platform_gpios_enable(const struct msm_gpio *table, int size)
> +{
> + int rc;
> + int i;
> + const struct msm_gpio *g;
> + for (i = 0; i< size; i++) {
> + g = table + i;
> + /* Enable gpio */
> + rc = gpio_tlmm_config(g->gpio_cfg, GPIO_ENABLE);
> + if (rc)
> + goto err;
> + }
> + return 0;
> +err:
> + return rc;
> +}
> +
> diff --git a/arch/arm/cpu/armv7/msm7630/lowlevel_init.S b/arch/arm/cpu/armv7/msm7630/lowlevel_init.S
> new file mode 100644
> index 0000000..d8d5b46
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/msm7630/lowlevel_init.S
> @@ -0,0 +1,626 @@
> +/*
> + * (C) Copyright 2012
> + * LARSEN& TOUBRO INFOTECH LTD<www.lntinfotech.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + *
> + */
> +
> +#include<config.h>
> +#include<version.h>
> +
> +.text
> +.code 32
> +
> +#define DSB .byte 0x4f, 0xf0, 0x7f, 0xf5
> +#define ISB .byte 0x6f, 0xf0, 0x7f, 0xf5
> +
> +/*
> + ; LVT Ring Osc counter
> + ; used to determine sense amp settings
> + ; Clobbers registers r0, r4, r5, r6, r7, r9, r10, r11
> +*/
> +.equ CLK_CTL_BASE, 0xA8600000
> +.equ A_GLBL_CLK_ENA, 0x0000
> +.equ A_PRPH_WEB_NS_REG,0x0080
> +.equ A_MSM_CLK_RINGOSC,0x00D0
> +.equ A_TCXO_CNT, 0x00D4
> +.equ A_TCXO_CNT_DONE, 0x00D8
> +.equ A_RINGOSC_CNT, 0x00DC
> +.equ A_MISC_CLK_CTL, 0x0108
> +.equ CLK_TEST, 0xA8600114
> +.equ SPSS_CSR_BASE, 0xAC100000
> +.equ A_SCRINGOSC, 0x0510
> +
> +//;; Number of TCXO cycles to count ring oscillations
> +.equ TCXO_CNT_VAL, 0x100
> +
> +//; Halcyon addresses
> +.equ TCSR_CONF_FUSE_1, 0xAB600060 //; TCSR_CONF_FUSE_1 register
> +.equ TCSR_CONF_FUSE_4, 0xAB60006C //; TCSR_CONF_FUSE_4 register
> +
> +//; SCORPION_L1_ACC (1:0) Fuses bit location
> +.equ L1_ACC_BIT_0, 12 //;12th bit of TCSR_CONF_FUSE_4
> +.equ L1_ACC_BIT_1, 13 //;13th bit of TCSR_CONF_FUSE_4
> +//; SCORPION_L2_ACC (2:0) Fuses bit location
> +.equ L2_ACC_BIT_0, 25 //;25th bit of TCSR_CONF_FUSE_1
> +.equ L2_ACC_BIT_1, 10 //;10th bit of TCSR_CONF_FUSE_4
> +.equ L2_ACC_BIT_2, 11 //;11th bit of TCSR_CONF_FUSE_4
> +
> +//; CP15: PVR2F0 values according to SCORPION_L1_ACC (1:0)
> +.equ PVR2F0_00, 0x00000000
> +.equ PVR2F0_01, 0x04000000
> +.equ PVR2F0_10, 0x08000000
> +.equ PVR2F0_11, 0x0C000000
> +
> +//; CP15: PVR2F1 values according to SCORPION_L1_ACC (1:0)
> +.equ PVR2F1_00, 0x00000008
> +.equ PVR2F1_01, 0x00000008
> +.equ PVR2F1_10, 0x00000208
> +.equ PVR2F1_11, 0x00000208
> +
> +//; CP15: PVR0F2 values according to SCORPION_L1_ACC (1:0)
> +.equ PVR0F2_00, 0x00000000
> +.equ PVR0F2_01, 0x00000000
> +.equ PVR0F2_10, 0x00000200
> +.equ PVR0F2_11, 0x00000200
> +
> +//; CP15: PVR0F0 values according to SCORPION_L1_ACC (1:0)
> +.equ PVR0F0_00, 0x7F000000
> +.equ PVR0F0_01, 0x7F000400
> +.equ PVR0F0_10, 0x7F000000
> +.equ PVR0F0_11, 0x7F000400
> +
> +//; CP15: L2VR3F1 values according to SCORPION_L2_ACC (2:0)
> +.equ L2VR3F1_000, 0x00FFFF60
> +.equ L2VR3F1_001, 0x00FFFF40
> +.equ L2VR3F1_010, 0x00FFFC60
> +.equ L2VR3F1_011, 0x00FFFC40
> +.equ L2VR3F1_100, 0x00FCFF60
> +.equ L2VR3F1_101, 0x00FCFF40
> +.equ L2VR3F1_110, 0x00FCFC60
> +.equ L2VR3F1_111, 0x00FCFC40
> +
> +
> +
> +
> +_TEXT_BASE:
> + .word CONFIG_SYS_TEXT_BASE @ sdram load addr from config file
> +
> +.global invalidate_dcache
> +invalidate_dcache:
> + mov pc, lr
> +
> + .align 5
> +.globl lowlevel_init
> +lowlevel_init:
> + mov pc, lr @ back to arch calling code
> +
> +.global reset_cpu
> +reset_cpu:
> +_loop_forever:
> + b _loop_forever
> +
> +.globl SET_SA
> +SET_SA:
> +
> + //;--------------------------------------------------------------------
> + //; Fuse bits used to determine sense amp settings
> + //;--------------------------------------------------------------------
> +
> + //; Reading L1_ACC
> + ldr r4, = 0x0
> +
> + //; Read L1_ACC_BIT_0
> + ldr r1, =TCSR_CONF_FUSE_4
> + ldr r2, =L1_ACC_BIT_0
> + ldr r3, [r1]
> + mov r3, r3, LSR r2
> + and r3, r3, #1
> + orr r4, r3, r4
> +
> + //; Read L1_ACC_BIT_1
> + ldr r1, =TCSR_CONF_FUSE_4
> + ldr r2, =L1_ACC_BIT_1
> + ldr r3, [r1]
> + mov r3, r3, LSR r2
> + and r3, r3, #1
> + mov r3, r3, LSL #1
> + orr r4, r3, r4
> +
> +l1_ck_0:
> + //; if L1_[1:0] == 00
> + ldr r5, = 0x0
> + cmp r4, r5
> + bne l1_ck_1
> + ldr r0, =PVR0F0_00
> + ldr r1, =PVR0F2_00
> + ldr r2, =PVR2F0_00
> + ldr r3, =PVR2F1_00
> + b WRITE_L1_SA_SETTINGS
> +
> +l1_ck_1:
> + //; if L1_[1:0] == 01
> + ldr r1, = 0x01
> + cmp r4, r1
> + bne l1_ck_2
> + ldr r0, =PVR0F0_01
> + ldr r1, =PVR0F2_01
> + ldr r2, =PVR2F0_01
> + ldr r3, =PVR2F1_01
> + b WRITE_L1_SA_SETTINGS
> +
> +l1_ck_2:
> + //; if L1_[2:0] == 10
> + ldr r1, = 0x02
> + cmp r4, r1
> + bne l1_ck_3
> + ldr r0, =PVR0F0_10
> + ldr r1, =PVR0F2_10
> + ldr r2, =PVR2F0_10
> + ldr r3, =PVR2F1_10
> + b WRITE_L1_SA_SETTINGS
> +
> +l1_ck_3:
> + //; if L1_[2:0] == 11
> + ldr r1, = 0x03
> + cmp r4, r1
> + ldr r0, =PVR0F0_11
> + ldr r1, =PVR0F2_11
> + ldr r2, =PVR2F0_11
> + ldr r3, =PVR2F1_11
> + b WRITE_L1_SA_SETTINGS
> +
> +
> +WRITE_L1_SA_SETTINGS:
> +
> + //;WCP15_PVR0F0 r0
> + mcr p15, 0x0, r0, c15, c15, 0x0 //; write R0 to PVR0F0
> +
> + //;WCP15_PVR0F2 r1
> + mcr p15, 0x0, r1, c15, c15, 0x2 //; write R1 to PVR0F2
> +
> + //;WCP15_PVR2F0 r2
> + mcr p15, 0x2, r2, c15, c15, 0x0 //; write R2 to PVR2F0
> +
> + // Disable predecode repair cache on certain Scorpion revisions
> + // (Raptor V2 and earlier, or Halcyon V1)
> + mrc p15, 0, r1, c0, c0, 0 //; MIDR
> + BIC r2, r1, #0xf0 //; check for Halcyon V1
> + ldr r4, =0x511f0000
> + cmp r2, r4
> + bne PVR2F1
> +
> +DPRC:
> + mrc p15, 0, r1, c15, c15, 2 //; PVR0F2
> + orr r1, r1, #0x10 //; enable bit 4
> + mcr p15, 0, r1, c15, c15, 2 //; disable predecode repair cache
> +
> +PVR2F1:
> + //;WCP15_PVR2F1 r3
> + mcr p15, 0x2, r3, c15, c15, 0x1 //; write R3 to PVR2F1
> +
> + //; Reading L2_ACC
> + ldr r4, = 0x0
> +
> + //; Read L2_ACC_BIT_0
> + ldr r1, =TCSR_CONF_FUSE_1
> + ldr r2, =L2_ACC_BIT_0
> + ldr r3, [r1]
> + mov r3, r3, LSR r2
> + and r3, r3, #1
> + orr r4, r3, r4
> +
> + //; Read L2_ACC_BIT_1
> + ldr r1, =TCSR_CONF_FUSE_4
> + ldr r2, =L2_ACC_BIT_1
> + ldr r3, [r1]
> + mov r3, r3, LSR r2
> + and r3, r3, #1
> + mov r3, r3, LSL #1
> + orr r4, r3, r4
> +
> + //; Read L2_ACC_BIT_2
> + ldr r1, =TCSR_CONF_FUSE_4
> + ldr r2, =L2_ACC_BIT_2
> + ldr r3, [r1]
> + mov r3, r3, LSR r2
> + and r3, r3, #1
> + mov r3, r3, LSL #2
> + orr r4, r3, r4
> +
> +l2_ck_0:
> + //; if L2_[2:0] == 000
> + ldr r5, = 0x0
> + cmp r4, r5
> + bne l2_ck_1
> + ldr r0, =L2VR3F1_000
> + b WRITE_L2_SA_SETTINGS
> +
> +l2_ck_1:
> + //; if L2_[2:0] == 001
> + ldr r5, = 0x1
> + cmp r4, r5
> + bne l2_ck_2
> + ldr r0, =L2VR3F1_001
> + b WRITE_L2_SA_SETTINGS
> +
> +l2_ck_2:
> + //; if L2_[2:0] == 010
> + ldr r5, = 0x2
> + cmp r4, r5
> + bne l2_ck_3
> + ldr r0, =L2VR3F1_010
> + b WRITE_L2_SA_SETTINGS
> +
> +l2_ck_3:
> + //; if L2_[2:0] == 011
> + ldr r5, = 0x3
> + cmp r4, r5
> + bne l2_ck_4
> + ldr r0, =L2VR3F1_011
> + b WRITE_L2_SA_SETTINGS
> +
> +l2_ck_4:
> + //; if L2_[2:0] == 100
> + ldr r5, = 0x4
> + cmp r4, r5
> + bne l2_ck_5
> + ldr r0, =L2VR3F1_100
> + b WRITE_L2_SA_SETTINGS
> +
> +l2_ck_5:
> + //; if L2_[2:0] == 101
> + ldr r5, = 0x5
> + cmp r4, r5
> + bne l2_ck_6
> + ldr r0, =L2VR3F1_101
> + b WRITE_L2_SA_SETTINGS
> +
> +l2_ck_6:
> + //; if L2_[2:0] == 110
> + ldr r5, = 0x6
> + cmp r4, r5
> + bne l2_ck_7
> + ldr r0, =L2VR3F1_110
> + b WRITE_L2_SA_SETTINGS
> +
> +l2_ck_7:
> + //; if L2_[2:0] == 111
> + ldr r5, = 0x7
> + cmp r4, r5
> + ldr r0, =L2VR3F1_111
> + b WRITE_L2_SA_SETTINGS
> +
> +WRITE_L2_SA_SETTINGS:
> + //;WCP15_L2VR3F1 r0
> + mcr p15, 0x3, r0, c15, c15, 0x1 //;write r0 to L2VR3F1
> + DSB
> + ISB
> +
> + ldr r0, =0 //;make sure the registers we touched
> + ldr r1, =0 //;are cleared when we return
> + ldr r2, =0
> + ldr r3, =0
> + ldr r4, =0
> + ldr r5, =0
> +
> + mrs r0, cpsr
> + orr r0, r0, #(1<<7)
> + msr cpsr_c, r0
> +
> + //; routine complete
> + pop {r5-r12,pc}
> +
> +.ltorg
> +
> +.globl __cpu_early_init
> +__cpu_early_init:
> +
> + //; Zero out r0 for use throughout this code. All other GPRs
> + //; (r1-r3) are set throughout this code to help establish
> + //; a consistent startup state for any code that follows.
> + //; Users should add code at the end of this routine to establish
> + //; their own stack address (r13), add translation page tables, enable
> + //; the caches, etc.
> + push {r5-r12,r14}
> + mov r0, #0x0
> +
> +
> + //; Remove hardcoded cache settings. appsbl_handler.s calls Set_SA
> + //; API to dynamically configure cache for slow/nominal/fast parts
> +
> + //; DCIALL to invalidate L2 cache bank (needs to be run 4 times,
> + //; once per bank)
> + //; This must be done early in code (prior to enabling the caches)
> + mov r1, #0x2
> + mcr p15, 0, r1, c9, c0, 6 //; DCIALL bank D ([15:14] == 2'b00)
> + orr r1, r1, #0x00004000
> + mcr p15, 0, r1, c9, c0, 6 //; DCIALL bank C ([15:14] == 2'b01)
> + add r1, r1, #0x00004000
> + mcr p15, 0, r1, c9, c0, 6 //; DCIALL bank B ([15:14] == 2'b10)
> + add r1, r1, #0x00004000
> + mcr p15, 0, r1, c9, c0, 6 //; DCIALL bank A ([15:14] == 2'b11)
> +
> + //; Initialize the BPCR - setup Global History Mask (GHRM) to all 1's
> + //; and have all address bits (AM) participate.
> + //; Different settings can be used to improve performance
> + // movW r1, #0x01FF
> +.word 0xe30011ff // hardcoded movW instruction due to lack of compiler support
> + // movT r1, #0x01FF
> +.word 0xe34011ff // hardcoded movT instruction due to lack of compiler support
> + mcr p15, 7, r1, c15, c0, 2 //; WCP15_BPCR
> +
> +
> + //; Initialize all I$ Victim Registers to 0 for startup
> + mcr p15, 0, r0, c9, c1, 0 //; WCP15_ICVIC0 r0
> + mcr p15, 0, r0, c9, c1, 1 //; WCP15_ICVIC1 r0
> + mcr p15, 0, r0, c9, c1, 2 //; WCP15_ICVIC2 r0
> + mcr p15, 0, r0, c9, c1, 3 //; WCP15_ICVIC3 r0
> + mcr p15, 0, r0, c9, c1, 4 //; WCP15_ICVIC4 r0
> + mcr p15, 0, r0, c9, c1, 5 //; WCP15_ICVIC5 r0
> + mcr p15, 0, r0, c9, c1, 6 //; WCP15_ICVIC5 r0
> + mcr p15, 0, r0, c9, c1, 7 //; WCP15_ICVIC7 r0
> +
> + //; Initialize all I$ Locked Victim Registers (Unlocked Floors) to 0
> + mcr p15, 1, r0, c9, c1, 0 //; WCP15_ICFLOOR0 r0
> + mcr p15, 1, r0, c9, c1, 1 //; WCP15_ICFLOOR1 r0
> + mcr p15, 1, r0, c9, c1, 2 //; WCP15_ICFLOOR2 r0
> + mcr p15, 1, r0, c9, c1, 3 //; WCP15_ICFLOOR3 r0
> + mcr p15, 1, r0, c9, c1, 4 //; WCP15_ICFLOOR4 r0
> + mcr p15, 1, r0, c9, c1, 5 //; WCP15_ICFLOOR5 r0
> + mcr p15, 1, r0, c9, c1, 6 //; WCP15_ICFLOOR6 r0
> + mcr p15, 1, r0, c9, c1, 7 //; WCP15_ICFLOOR7 r0
> +
> + //; Initialize all D$ Victim Registers to 0
> + mcr p15, 2, r0, c9, c1, 0 //; WP15_DCVIC0 r0
> + mcr p15, 2, r0, c9, c1, 1 //; WP15_DCVIC1 r0
> + mcr p15, 2, r0, c9, c1, 2 //; WP15_DCVIC2 r0
> + mcr p15, 2, r0, c9, c1, 3 //; WP15_DCVIC3 r0
> + mcr p15, 2, r0, c9, c1, 4 //; WP15_DCVIC4 r0
> + mcr p15, 2, r0, c9, c1, 5 //; WP15_DCVIC5 r0
> + mcr p15, 2, r0, c9, c1, 6 //; WP15_DCVIC6 r0
> + mcr p15, 2, r0, c9, c1, 7 //; WP15_DCVIC7 r0
> +
> + //; Initialize all D$ Locked VDCtim Registers (Unlocked Floors) to 0
> + mcr p15, 3, r0, c9, c1, 0 //; WCP15_DCFLOOR0 r0
> + mcr p15, 3, r0, c9, c1, 1 //; WCP15_DCFLOOR1 r0
> + mcr p15, 3, r0, c9, c1, 2 //; WCP15_DCFLOOR2 r0
> + mcr p15, 3, r0, c9, c1, 3 //; WCP15_DCFLOOR3 r0
> + mcr p15, 3, r0, c9, c1, 4 //; WCP15_DCFLOOR4 r0
> + mcr p15, 3, r0, c9, c1, 5 //; WCP15_DCFLOOR5 r0
> + mcr p15, 3, r0, c9, c1, 6 //; WCP15_DCFLOOR6 r0
> + mcr p15, 3, r0, c9, c1, 7 //; WCP15_DCFLOOR7 r0
> +
> + //; Initialize ASID to zero
> + mcr p15, 0, r0, c13, c0, 1 //; WCP15_CONTEXTIDR r0
> +
> + //; ICIALL to invalidate entire I-Cache
> + mcr p15, 0, r0, c7, c5, 0 //; ICIALLU
> +
> + //; DCIALL to invalidate entire D-Cache
> + mcr p15, 0, r0, c9, c0, 6 //; DCIALL r0
> +
> + //; Initialize ADFSR to zero
> + mcr p15, 0, r0, c5, c1, 0 //; ADFSR r0
> +
> + //; Initialize EFSR to zero
> + mcr p15, 7, r0, c15, c0, 1 //; EFSR r0
> +
> + //; The VBAR (Vector Base Address Register) should be initialized
> + //; early in your code. We are setting it to zero
> + mcr p15, 0, r0, c12, c0, 0 //; WCP15_VBAR r0
> +
> + //; Ensure the mcr's above have completed their operation
> + //; before continuing
> + DSB
> + ISB
> +
> + //; Setup CCPR - Cache Coherency Policy Register
> + //; setup CCPR[L1ISHP, L2ISHP] both to 0b00 (no forcing)
> + //; setup CCPR[L1OSHP, L2OSHP] both to 0b10 (force non-cacheable)
> + movw r2, #0x88
> + mcr p15, 0, r2, c10, c4, 2
> +
> + //;-------------------------------------------------------------------
> + //; There are a number of registers that must be set prior to enabling
> + //; the MMU. The DCAR is one of these registers. We are setting
> + //; it to zero (no access) to easily detect improper setup in subsequent
> + //; code sequences
> + //;-------------------------------------------------------------------
> + //; Setup DACR (Domain Access Control Register) to zero
> + mcr p15, 0, r0, c3, c0, 0 //; WCP15_DACR r0
> +
> + //; Setup DCLKCR to allow normal D-Cache line fills
> + mcr p15, 1, r0, c9, c0, 7 //; WCP15_DCLKCR r0
> +
> + //; Setup the TLBLKCR
> + //; Victim = 6'b000000; Floor = 6'b000000;
> + //; IASIDCFG =
> + //;2'b00 (State-Machine); IALLCFG = 2'b01 (Flash); BNA = 1'b0;
> + mov r1, #0x02
> + mcr p15, 0, r1, c10, c1, 3 //; WCP15_TLBLKCR r1
> +
> + //;Make sure TLBLKCR is complete before continuing
> + ISB
> +
> + //; Invalidate the UTLB
> + mcr p15, 0, r0, c8, c7, 0 //; UTLBIALL
> +
> + //; Make sure UTLB request has been presented to macro before continuing
> + ISB
> +
> +SYSI2:
> + //; setup L2CR1 to some default Instruction and data prefetching values
> + //; Users may want specific settings for various performance
> + //; enhancements
> + //; In Halcyon we do not have broadcasting barriers. So we need to turn
> + // ; on bit 8 of L2CR1; which DBB:( Disable barrier broadcast )
> + ldr r2, =0x133
> + mcr p15, 3, r2, c15, c0, 3 //; WCP15_L2CR1 r0
> +
> +
> + //; Enable Z bit to enable branch prediction (default is off)
> + mrc p15, 0, r2, c1, c0, 0 //; RCP15_SCTLR r2
> + orr r2, r2, #0x00000800
> + mcr p15, 0, r2, c1, c0, 0 //; WCP15_SCTLR r2
> +
> + //; Make sure Link stack is initialized with branch and links to
> + //; sequential addresses
> + //; This aids in creating a predictable startup environment
> + bl SEQ1
> +SEQ1: bl SEQ2
> +SEQ2: bl SEQ3
> +SEQ3: bl SEQ4
> +SEQ4: bl SEQ5
> +SEQ5: bl SEQ6
> +SEQ6: bl SEQ7
> +SEQ7: bl SEQ8
> +SEQ8:
> +
> + //; REMOVE FOLLOWING THREE INSTRUCTIONS WHEN POWER COLLAPSE IS ENA
> + //;Make sure the DBGOSLSR[LOCK] bit is cleared to allow access to the
> + //;debug registers
> + //; Writing anything but the "secret code" to the DBGOSLAR clears the
> + //;DBGOSLSR[LOCK] bit
> + mcr p14, 0, r0, c1, c0, 4 //; WCP14_DBGOSLAR r0
> +
> +
> + //; Read the DBGPRSR to clear the DBGPRSR[STICKYPD]
> + //; Any read to DBGPRSR clear the STICKYPD bit
> + //; ISB guarantees the read completes before attempting to
> + //; execute a CP14 instruction.
> + mrc p14, 0, r3, c1, c5, 4 //; RCP14_DBGPRSR r3
> + ISB
> +
> + //; Initialize the Watchpoint Control Registers to zero (optional)
If that is optional, why do it?
> + //;;; mcr p14, 0, r0, c0, c0, 7 ; WCP14_DBGWCR0 r0
> + //;;; mcr p14, 0, r0, c0, c1, 7 ; WCP14_DBGWCR1 r0
> +
> +
> + //;--------------------------------------------------------------------
> + //; The saved Program Status Registers (SPSRs) should be setup
> + //; prior to any automatic mode switches. The following
> + //; code sets these registers up to a known state. Users will need to
> + //; customize these settings to meet their needs.
> + //;--------------------------------------------------------------------
> + mov r2, #0x1f
> + mov r1, #0xd7 //;ABT mode
> + msr cpsr_c, r1 //;ABT mode
> + msr spsr_cxfs, r2 //;clear the spsr
> + mov r1, #0xdb //;UND mode
> + msr cpsr_c, r1 //;UND mode
> + msr spsr_cxfs, r2 //;clear the spsr
> + mov r1, #0xd1 //;FIQ mode
> + msr cpsr_c, r1 //;FIQ mode
> + msr spsr_cxfs, r2 //;clear the spsr
> + mov r1, #0xd2 //;IRQ mode
> + msr cpsr_c, r1 //;IRQ mode
> + msr spsr_cxfs, r2 //;clear the spsr
> + mov r1, #0xd6 //;Monitor mode
> + msr cpsr_c, r1 //;Monitor mode
> + msr spsr_cxfs, r2 //;clear the spsr
> + mov r1, #0xd3 //;SVC mode
> + msr cpsr_c, r1 //;SVC mode
> + msr spsr_cxfs, r2 //;clear the spsr
> +
> +
> + //;--------------------------------------------------------------------
> + //; Enabling Error reporting is something users may want to do at
> + //; some other point in time. We have chosen some default settings
> + //; that should be reviewed. Most of these registers come up in an
> + //; unpredictable state after reset.
> + //;--------------------------------------------------------------------
> +//;Start of error and control setting
> +
> + //; setup L2CR0 with various L2/TCM control settings
> + //; enable out of order bus attributes and error reporting
> + //; this register comes up unpredictable after reset
> + // movw r1, #0x0F0F
> +.word 0xe3001f0f // hardcoded movw instruction due to lack of compiler support
> + // movT r1, #0xC005
> +.word 0xe34c1005 // hardcoded movw instruction due to lack of compiler support
> + mcr p15, 3, r1, c15, c0, 1 //; WCP15_L2CR0 r1
> +
> + //; setup L2CPUCR
> + //; mov r2, #0xFF
> + //; Enable I and D cache parity
> + //;L2CPUCR[7:5] = 3~Rh7 ~V enable parity error reporting for modified,
> + //;tag, and data parity errors
> + mov r2, #0xe0
> + mcr p15, 3, r2, c15, c0, 2 //; WCP15_L2CPUCR r2
> +
> + //; setup SPCR
> + //; enable all error reporting
> + //;(reset value is unpredicatble for most bits)
> + mov r3, #0x0F
> + mcr p15, 0, r3, c9, c7, 0 //; WCP15_SPCR r3
> +
> + //; setup DMACHCRs (reset value unpredictable)
> + //; control setting and enable all error reporting
> + mov r1, #0x0F
> +
> + //; DMACHCR0 = 0000000F
> + mov r2, #0x00 //; channel 0
> + mcr p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
> + mcr p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
> +
> + //; DMACHCR1 = 0000000F
> + mov r2, #0x01 //; channel 1
> + mcr p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
> + mcr p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
> +
> + //; DMACHCR2 = 0000000F
> + mov r2, #0x02 //; channel 2
> + mcr p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
> + mcr p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
> +
> + //; DMACHCR3 = 0000000F
> + mov r2, #0x03 //; channel 3
> + mcr p15, 0, r2, c11, c0, 0 //; WCP15_DMASELR r2
> + mcr p15, 0, r1, c11, c0, 2 //; WCP15_DMACHCR r1
> +
> + //; Set ACTLR (reset unpredictable)
> + //; Set AVIVT control, error reporting, etc.
> + //; mov r3, #0x07
> + //; Enable I and D cache parity
> + //;ACTLR[2:0] = 3'h7 - enable parity error reporting from L2/I$/D$)
> + //;ACTLR[5:4] = 2'h3 - enable parity
> + //;ACTLR[19:18] =2'h3 - always generate and
> + //;check parity(when MMU disabled).
> + //;Value to be written #0xC0037
> + // movw r3, #0x0037
> +.word 0xe3003037 // hardcoded movw instruction due to lack of compiler support
> + // movT r3, #0x000C
> +.word 0xe340300c // hardcoded movw instruction due to lack of compiler support
> + mcr p15, 0, r3, c1, c0, 1 //; WCP15_ACTLR r3
> +
> +//;End of error and control setting
> +
> + //;---------------------------------------------------------------------
> + //; Unlock ETM and read StickyPD to halt the ETM clocks from running.
> + //; This is required for power saving whether the ETM is used or not.
> + //;---------------------------------------------------------------------
> +
> + //;Clear ETMOSLSR[LOCK] bit
> + mov r1, #0x00000000
> + mcr p14, 1, r1, c1, c0, 4 //; WCP14_ETMOSLAR r1
> +
> + //;Clear ETMPDSR[STICKYPD] bit
> + mrc p14, 1, r2, c1, c5, 4 //; RCP14_ETMPDSR r2
> + b SET_SA
> +
> +
> +.ltorg
> diff --git a/arch/arm/cpu/armv7/msm7630/timer.c b/arch/arm/cpu/armv7/msm7630/timer.c
> new file mode 100644
> index 0000000..1c3f7ba
> --- /dev/null
> +++ b/arch/arm/cpu/armv7/msm7630/timer.c
> @@ -0,0 +1,148 @@
> +/*
> + * (C) Copyright 2012
> + * LARSEN& TOUBRO INFOTECH LTD<www.lntinfotech.com>
> + *
> + * (C) Copyright 2010,2011
> + * NVIDIA Corporation<www.nvidia.com>
> + *
> + * (C) Copyright 2008
> + * Texas Instruments
> + *
> + * Richard Woodruff<r-woodruff2@ti.com>
> + * Syed Moahmmed Khasim<khasim@ti.com>
> + *
> + * (C) Copyright 2002
> + * Sysgo Real-Time Solutions, GmbH<www.elinos.com>
> + * Marius Groeger<mgroeger@sysgo.de>
> + * Alex Zuepke<azu@sysgo.de>
> + *
> + * (C) Copyright 2002
> + * Gary Jennejohn, DENX Software Engineering,<garyj@denx.de>
> + *
> + * See file CREDITS for list of people who contributed to this
> + * project.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
> + * MA 02111-1307 USA
> + */
> +
> +#include<asm/arch/iomap.h>
> +#include<asm/io.h>
> +#include<config.h>
> +#include<common.h>
> +#include<asm/types.h>
> +#define TIMER_LOAD_VAL 0x21
> +
> +#define GPT_ENABLE_CLR_ON_MATCH_EN 2
> +#define GPT_ENABLE_EN 1
> +#define DGT_ENABLE_CLR_ON_MATCH_EN 2
> +#define DGT_ENABLE_EN 1
> +
> +#define SPSS_TIMER_STATUS_DGT_EN (1<< 0)
> +
> +
> +#define READ_TIMER readl(GPT_COUNT_VAL)
> +
> +static ulong timestamp;
> +static ulong lastinc;
> +#define DGT_HZ 6750000 /* Uses LPXO/4 (27.0 MHz / 4) */
> +
> +
> +/* nothing really to do with interrupts, just starts up a counter. */
> +int timer_init(void)
> +{
> + uint32_t val = 0;
> +
> + /* Disable timer */
> + writel(0, DGT_ENABLE);
> +
> + /* Check for the hardware revision */
> + val = readl(HW_REVISION_NUMBER);
> + val = (val>> 28)& 0x0F;
> + if (val>= 1)
> + writel(1, DGT_CLK_CTL);
> + return 0;
> +}
> +
> +
> +ulong get_timer(ulong base)
> +{
> + return get_timer_masked() - base;
> +}
> +
> +/* delay x useconds AND perserve advance timstamp value */
> +void __udelay(unsigned long usecs)
> +{
> + unsigned int val;
> + usecs = (usecs * 33 + 1000 - 33) / 1000;
> +
> + writel(0, GPT_CLEAR);
> + writel(0, GPT_ENABLE);
> + do {
> + val = 0;
> + val = readl(GPT_COUNT_VAL);
> + } while (val != 0);
> +
> + writel(GPT_ENABLE_EN, GPT_ENABLE);
> + do {
> + val = 0;
> + val = readl(GPT_COUNT_VAL);
> + } while (val< usecs) ;
> +
> + writel(0, GPT_ENABLE);
> + writel(0, GPT_CLEAR);
> +
> +}
> +
> +void reset_timer_masked(void)
Why do you need a timer reset function?
> +{
> + /* reset time */
> + lastinc = READ_TIMER; /* capure current decrementer value time */
> + timestamp = 0; /* start "advancing" time stamp from 0 */
> +}
> +
> +ulong get_timer_masked(void)
> +{
> + ulong now = READ_TIMER; /* current tick value */
> +
> + if (lastinc<= now) { /* normal mode (non roll) */
> + /* normal mode */
> + timestamp += now - lastinc;
> + /* move stamp forward with absolute diff ticks */
> + } else { /* we have overflow of the count down timer */
> + timestamp += now + (TIMER_LOAD_VAL - lastinc);
> + }
> + lastinc = now;
> +
> + return timestamp;
> +}
> +
> +/*
> + * This function is derived from PowerPC code (read timebase as long long).
> + * On ARM it just returns the timer value.
> + */
> +unsigned long long get_ticks(void)
> +{
> + return get_timer(0);
> +}
> +
> +/*
> + * This function is derived from PowerPC code (timebase clock frequency).
> + * On ARM it returns the number of timer ticks per second.
> + */
> +ulong get_tbclk(void)
> +{
> + return 19200000;
> +}
> diff --git a/arch/arm/include/asm/arch-msm7630/adm.h b/arch/arm/include/asm/arch-msm7630/adm.h
> new file mode 100644
> index 0000000..0e8af85
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-msm7630/adm.h
> @@ -0,0 +1,28 @@
> +/*
> + * (C) Copyright 2012
> + * LARSEN& TOUBRO INFOTECH LTD<www.lntinfotech.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + *
> + */
> +
> +#ifndef __ADM_H
> +#define __ADM_H
> +
> +/* Channel #s and security domain */
> +#define ADM_CHN 8
> +#define ADM_SD 2
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-msm7630/gpio.h b/arch/arm/include/asm/arch-msm7630/gpio.h
> new file mode 100644
> index 0000000..af6ddaa
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-msm7630/gpio.h
> @@ -0,0 +1,47 @@
> +/*
> + * (C) Copyright 2012
> + * LARSEN& TOUBRO INFOTECH LTD<www.lntinfotech.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + *
> + */
> +
> +#ifndef __GPIO_H
> +#define __GPIO_H
> +
> +#ifndef GPIO_INPUT
> +#define GPIO_INPUT 0x0000
> +#endif
> +#ifndef GPIO_OUTPUT
> +#define GPIO_OUTPUT 0x0001
> +#endif
> +
> +#define GPIO_LEVEL 0x0000
> +#define GPIO_EDGE 0x0010
> +
> +#define GPIO_RISING 0x0020
> +#define GPIO_FALLING 0x0040
> +
> +#define GPIO_HIGH 0x0020
> +#define GPIO_LOW 0x0040
> +
> +#define GPIO_PULLUP 0x0100
> +#define GPIO_PULLDOWN 0x0200
> +
> +int gpio_config(unsigned nr, unsigned flags);
> +void gpio_set(unsigned nr, unsigned on);
> +int gpio_get(unsigned nr);
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-msm7630/gpio_hw.h b/arch/arm/include/asm/arch-msm7630/gpio_hw.h
> new file mode 100644
> index 0000000..c8244d8
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-msm7630/gpio_hw.h
> @@ -0,0 +1,168 @@
> +/*
> + * (C) Copyright 2012
> + * LARSEN& TOUBRO INFOTECH LTD<www.lntinfotech.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + *
> + */
> +
> +#ifndef __GPIO_HW_H
> +#define __GPIO_HW_H
> +
> +#define MSM_GPIO1_BASE 0xAC001000
> +#define MSM_GPIO2_BASE 0xAC101000
> +
> +#define GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
> +#define GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
> +
> +/* output value */
> +#define GPIO_OUT_0 GPIO1_REG(0x00) /* gpio 15-0 */
> +#define GPIO_OUT_1 GPIO2_REG(0x00) /* gpio 43-16 */
> +#define GPIO_OUT_2 GPIO1_REG(0x04) /* gpio 67-44 */
> +#define GPIO_OUT_3 GPIO1_REG(0x08) /* gpio 94-68 */
> +#define GPIO_OUT_4 GPIO1_REG(0x0C) /* gpio 106-95 */
> +#define GPIO_OUT_5 GPIO1_REG(0x50) /* gpio 133-107 */
> +#define GPIO_OUT_6 GPIO1_REG(0xC4) /* gpio 150-134 */
> +#define GPIO_OUT_7 GPIO1_REG(0x214) /* gpio 181-151 */
> +
> +/* same pin map as above, output enable */
> +#define GPIO_OE_0 GPIO1_REG(0x10)
> +#define GPIO_OE_1 GPIO2_REG(0x08)
> +#define GPIO_OE_2 GPIO1_REG(0x14)
> +#define GPIO_OE_3 GPIO1_REG(0x18)
> +#define GPIO_OE_4 GPIO1_REG(0x1C)
> +#define GPIO_OE_5 GPIO1_REG(0x54)
> +#define GPIO_OE_6 GPIO1_REG(0xC8)
> +#define GPIO_OE_7 GPIO1_REG(0x218)
> +
> +/* same pin map as above, input read */
> +#define GPIO_IN_0 GPIO1_REG(0x34)
> +#define GPIO_IN_1 GPIO2_REG(0x20)
> +#define GPIO_IN_2 GPIO1_REG(0x38)
> +#define GPIO_IN_3 GPIO1_REG(0x3C)
> +#define GPIO_IN_4 GPIO1_REG(0x40)
> +#define GPIO_IN_5 GPIO1_REG(0x44)
> +#define GPIO_IN_6 GPIO1_REG(0xCC)
> +#define GPIO_IN_7 GPIO1_REG(0x21C)
> +
> +/* same pin map as above, 1=edge 0=level interrup */
> +#define GPIO_INT_EDGE_0 GPIO1_REG(0x60)
> +#define GPIO_INT_EDGE_1 GPIO2_REG(0x50)
> +#define GPIO_INT_EDGE_2 GPIO1_REG(0x64)
> +#define GPIO_INT_EDGE_3 GPIO1_REG(0x68)
> +#define GPIO_INT_EDGE_4 GPIO1_REG(0x6C)
> +#define GPIO_INT_EDGE_5 GPIO1_REG(0xC0)
> +#define GPIO_INT_EDGE_6 GPIO1_REG(0xD0)
> +#define GPIO_INT_EDGE_7 GPIO1_REG(0x240)
> +
> +/* same pin map as above, 1=positive 0=negative */
> +#define GPIO_INT_POS_0 GPIO1_REG(0x70)
> +#define GPIO_INT_POS_1 GPIO2_REG(0x58)
> +#define GPIO_INT_POS_2 GPIO1_REG(0x74)
> +#define GPIO_INT_POS_3 GPIO1_REG(0x78)
> +#define GPIO_INT_POS_4 GPIO1_REG(0x7C)
> +#define GPIO_INT_POS_5 GPIO1_REG(0xBC)
> +#define GPIO_INT_POS_6 GPIO1_REG(0xD4)
> +#define GPIO_INT_POS_7 GPIO1_REG(0x228)
> +
> +/* same pin map as above, interrupt enable */
> +#define GPIO_INT_EN_0 GPIO1_REG(0x80)
> +#define GPIO_INT_EN_1 GPIO2_REG(0x60)
> +#define GPIO_INT_EN_2 GPIO1_REG(0x84)
> +#define GPIO_INT_EN_3 GPIO1_REG(0x88)
> +#define GPIO_INT_EN_4 GPIO1_REG(0x8C)
> +#define GPIO_INT_EN_5 GPIO1_REG(0xB8)
> +#define GPIO_INT_EN_6 GPIO1_REG(0xD8)
> +#define GPIO_INT_EN_7 GPIO1_REG(0x22C)
> +
> +/* same pin map as above, write 1 to clear interrupt */
> +#define GPIO_INT_CLEAR_0 GPIO1_REG(0x90)
> +#define GPIO_INT_CLEAR_1 GPIO2_REG(0x68)
> +#define GPIO_INT_CLEAR_2 GPIO1_REG(0x94)
> +#define GPIO_INT_CLEAR_3 GPIO1_REG(0x98)
> +#define GPIO_INT_CLEAR_4 GPIO1_REG(0x9C)
> +#define GPIO_INT_CLEAR_5 GPIO1_REG(0xB4)
> +#define GPIO_INT_CLEAR_6 GPIO1_REG(0xDC)
> +#define GPIO_INT_CLEAR_7 GPIO1_REG(0x230)
> +
> +/* same pin map as above, 1=interrupt pending */
> +#define GPIO_INT_STATUS_0 GPIO1_REG(0xA0)
> +#define GPIO_INT_STATUS_1 GPIO2_REG(0x70)
> +#define GPIO_INT_STATUS_2 GPIO1_REG(0xA4)
> +#define GPIO_INT_STATUS_3 GPIO1_REG(0xA8)
> +#define GPIO_INT_STATUS_4 GPIO1_REG(0xAC)
> +#define GPIO_INT_STATUS_5 GPIO1_REG(0xB0)
> +#define GPIO_INT_STATUS_6 GPIO1_REG(0xE0)
> +#define GPIO_INT_STATUS_7 GPIO1_REG(0x234)
> +
> +
> +#define GPIO_OUT_VAL_REG_BASE 0xABC00000
> +#define GPIO_ALT_FUNC_PAGE_REG (GPIO_OUT_VAL_REG_BASE + 0x20)
> +#define GPIO_ALT_FUNC_CFG_REG (GPIO_OUT_VAL_REG_BASE + 0x24)
> +
> +
> +/* GPIO TLMM: Pullup/Pulldown */
> +#define GPIO_NO_PULL 0
> +#define GPIO_PULL_DOWN 1
> +#define GPIO_KEEPER 2
> +#define GPIO_PULL_UP 3
> +
> +/* GPIO TLMM: Drive Strength */
> +#define GPIO_2MA 0
> +#define GPIO_4MA 1
> +#define GPIO_6MA 2
> +#define GPIO_8MA 3
> +#define GPIO_10MA 4
> +#define GPIO_12MA 5
> +#define GPIO_14MA 6
> +#define GPIO_16MA 7
> +
> +#define GPIO38_GPIO_CNTRL 0x175
> +
> +/* GPIO TLMM: Status */
> +#define GPIO_ENABLE 0
> +#define GPIO_DISABLE 1
> +
> +#define GPIO_CFG(gpio, func, dir, pull, drvstr) \
> + ((((gpio)& 0x3FF)<< 4) | \
> + ((func)& 0xf) | \
> + (((dir)& 0x1)<< 14) | \
> + (((pull)& 0x3)<< 15) | \
> + (((drvstr)& 0xF)<< 17))
> +
> +/**
> + * struct msm_gpio - GPIO pin description
> + * @gpio_cfg - configuration bitmap, as per gpio_tlmm_config()
> + * @label - textual label
> + *
> + * Usually, GPIO's are operated by sets.
> + * This struct accumulate all GPIO information in single source
> + * and facilitete group operations provided by msm_gpios_xxx()
> + */
> +struct msm_gpio {
> + unsigned gpio_cfg;
> + const char *label;
> +};
> +
> +/**
> + * extract GPIO pin from bit-field used for gpio_tlmm_config
> + */
> +#define GPIO_PIN(gpio_cfg) (((gpio_cfg)>> 4)& 0x3ff)
> +#define GPIO_FUNC(gpio_cfg) (((gpio_cfg)>> 0)& 0xf)
> +#define GPIO_DIR(gpio_cfg) (((gpio_cfg)>> 14)& 0x1)
> +#define GPIO_PULL(gpio_cfg) (((gpio_cfg)>> 15)& 0x3)
> +#define GPIO_DRVSTR(gpio_cfg) (((gpio_cfg)>> 17)& 0xf)
> +
> +#endif
> diff --git a/arch/arm/include/asm/arch-msm7630/iomap.h b/arch/arm/include/asm/arch-msm7630/iomap.h
> new file mode 100644
> index 0000000..186c6c2
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-msm7630/iomap.h
> @@ -0,0 +1,96 @@
> +/*
> + * (C) Copyright 2012
> + * LARSEN& TOUBRO INFOTECH LTD<www.lntinfotech.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + *
> + */
> +
> +#ifndef __IOMAP_H_
> +#define __IOMAP_H_
> +
> +#define MSM_UART1_BASE 0xACA00000
> +#define MSM_UART2_BASE 0xACB00000
> +#define MSM_UART3_BASE 0xACC00000
> +
> +#define MSM_VIC_BASE 0xC0080000
> +#define MSM_TMR_BASE 0xC0100000
> +
> +#define MSM_GPT_BASE (MSM_TMR_BASE + 0x04)
> +#define MSM_DGT_BASE (MSM_TMR_BASE + 0x24)
> +#define SPSS_TIMER_STATUS (MSM_TMR_BASE + 0x88)
> +
> +#define GPT_REG(off) (MSM_GPT_BASE + (off))
> +#define DGT_REG(off) (MSM_DGT_BASE + (off))
> +
> +#define GPT_MATCH_VAL GPT_REG(0x0000)
> +#define GPT_COUNT_VAL GPT_REG(0x0004)
> +#define GPT_ENABLE GPT_REG(0x0008)
> +#define GPT_CLEAR GPT_REG(0x000C)
> +
> +#define DGT_MATCH_VAL DGT_REG(0x0000)
> +#define DGT_COUNT_VAL DGT_REG(0x0004)
> +#define DGT_ENABLE DGT_REG(0x0008)
> +#define DGT_CLEAR DGT_REG(0x000C)
> +#define DGT_CLK_CTL DGT_REG(0x0010)
> +
> +#define HW_REVISION_NUMBER 0xABC00270
> +
> +#define MSM_CSR_BASE 0xC0100000
> +#define MSM_GCC_BASE 0xC0182000
> +
> +#define MSM_SDC1_BASE 0xA0400000
> +#define MSM_SDC2_BASE 0xA0500000
> +#define MSM_SDC3_BASE 0xA3000000
> +#define MSM_SDC4_BASE 0xA3100000
> +
> +#define MSM_SHARED_BASE 0x00100000
> +#define MSM_CLK_CTL_BASE 0xAB800000
> +#define MSM_CLK_CTL_SH2_BASE 0xABA01000
> +
> +#define REG_BASE(off) (MSM_CLK_CTL_BASE + (off))
> +#define REG_SH2_BASE(off) (MSM_CLK_CTL_SH2_BASE + (off))
> +
> +#define SCSS_CLK_CTL 0xC0101004
> +#define SCSS_CLK_SEL 0xC0101008
> +
> +#define MSM_USB_BASE 0xA3600000
> +#define MSM_CRYPTO_BASE 0xA8400000
> +
> +#define SH2_USBH_MD_REG REG_SH2_BASE(0x2BC)
> +#define SH2_USBH_NS_REG REG_SH2_BASE(0x2C0)
> +
> +#define SH2_MDP_NS_REG REG_SH2_BASE(0x14C)
> +#define SH2_MDP_LCDC_MD_REG REG_SH2_BASE(0x38C)
> +#define SH2_MDP_LCDC_NS_REG REG_SH2_BASE(0x390)
> +#define SH2_MDP_VSYNC_REG REG_SH2_BASE(0x460)
> +#define SH2_PMDH_NS_REG REG_SH2_BASE(0x8C)
> +
> +#define SH2_GLBL_CLK_ENA_SC REG_SH2_BASE(0x3BC)
> +#define SH2_GLBL_CLK_ENA_2_SC REG_SH2_BASE(0x3C0)
> +
> +#define SH2_OWN_ROW1_BASE_REG REG_BASE(0x041C)
> +#define SH2_OWN_ROW2_BASE_REG REG_BASE(0x0424)
> +#define SH2_OWN_APPS2_BASE_REG REG_BASE(0x0414)
> +
> +#define MSM_ADM_BASE 0xAC200000
> +#define MSM_ADM_SD_OFFSET 0x00100400
> +
> +#define MSM_SAW_BASE 0xC0102000
> +
> +#define PLL_ENA_REG REG_SH2_BASE(0x0264)
> +#define PLL2_STATUS_BASE_REG REG_BASE(0x0350)
> +#define PLL2_L_VAL_ADDR REG_BASE(0x033C)
> +#endif
> diff --git a/arch/arm/include/asm/arch-msm7630/proc_comm.h b/arch/arm/include/asm/arch-msm7630/proc_comm.h
> new file mode 100644
> index 0000000..3df08b9
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-msm7630/proc_comm.h
> @@ -0,0 +1,42 @@
> +/*
> + * (C) Copyright 2012
> + * LARSEN& TOUBRO INFOTECH LTD<www.lntinfotech.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + *
> + */
> +
> +#ifndef __PROC_COMM_H_
> +#define __PROC_COMM_H_
> +
> +void usb_clock_init(void);
> +void lcdc_clock_init(unsigned rate);
> +void mdp_clock_init(unsigned rate);
> +void uart3_clock_init(void);
> +void uart2_clock_init(void);
> +void uart1_clock_init(void);
> +void mddi_clock_init(unsigned num, unsigned rate);
> +void reboot(unsigned reboot_reason);
> +int mmc_clock_enable_disable(unsigned id, unsigned enable);
> +int mmc_clock_set_rate(unsigned id, unsigned rate);
> +int mmc_clock_get_rate(unsigned id);
> +int gpio_tlmm_config(unsigned config, unsigned disable);
> +int vreg_set_level(unsigned id, unsigned mv);
> +int vreg_enable(unsigned id);
> +int vreg_disable(unsigned id);
> +
> +#endif
> +
> +
> diff --git a/arch/arm/include/asm/arch-msm7630/sys_proto.h b/arch/arm/include/asm/arch-msm7630/sys_proto.h
> new file mode 100644
> index 0000000..c679d92
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-msm7630/sys_proto.h
> @@ -0,0 +1,29 @@
> +/*
> + * (C) Copyright 2012
> + * LARSEN& TOUBRO INFOTECH LTD<www.lntinfotech.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
> + *
> + */
> +
> +#ifndef _SYS_PROTO_H_
> +#define _SYS_PROTO_H_
> +
> +void pll8_enable(void);
> +void clock_init(void);
> +void __cpu_early_init(void);
> +
> +#endif
> +
> --
> 1.7.1
>
>
> The contents of this e-mail and any attachment(s) may contain confidential or privileged information for the intended recipient(s). Unintended recipients are prohibited from taking action on the basis of information in this e-mail and using or disseminating the information, and must notify the sender and delete it from their system. L&T Infotech will not accept responsibility or liability for the accuracy or completeness of, or the presence of any virus or disabling code in this e-mail"
>
Amicalement,
--
Albert.
next prev parent reply other threads:[~2012-02-29 0:00 UTC|newest]
Thread overview: 716+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <yes>
2009-01-16 18:08 ` Quota fixes and improvements Jan Kara
2009-01-16 18:08 ` [PATCH 01/11] quota: Improve locking Jan Kara
2009-01-16 18:08 ` [PATCH 02/11] ocfs2: Remove ocfs2_dquot_initialize() and ocfs2_dquot_drop() Jan Kara
2009-01-16 18:08 ` [PATCH 03/11] ocfs2: Push out dropping of dentry lock to ocfs2_wq Jan Kara
2009-01-16 18:08 ` [PATCH 04/11] ocfs2: Fix possible deadlock in ocfs2_write_dquot() Jan Kara
2009-01-16 18:08 ` [PATCH 05/11] quota: Add quota reservation support Jan Kara
2009-01-16 18:08 ` [PATCH 06/11] quota: Add quota reservation claim and released operations Jan Kara
2009-01-16 18:08 ` [PATCH 07/11] quota: Use inode->i_blkbits to get block bits Jan Kara
2009-01-16 18:08 ` [PATCH 08/11] quota: Move EXPORT_SYMBOL immediately next to the functions/varibles Jan Kara
2009-01-16 18:08 ` [PATCH 09/11] ext3: Remove unnecessary quota functions Jan Kara
2009-01-16 18:08 ` [PATCH 10/11] ext4: " Jan Kara
2009-01-16 18:08 ` [PATCH 11/11] reiserfs: " Jan Kara
2009-01-16 18:08 ` Jan Kara
2009-01-20 21:41 ` [PATCH 10/11] ext4: " Mingming Cao
2009-01-20 21:41 ` Mingming Cao
2009-01-20 21:41 ` [PATCH 09/11] ext3: " Mingming Cao
2009-01-20 21:41 ` Mingming Cao
2009-01-24 7:49 ` [PATCH 01/11] quota: Improve locking Andrew Morton
2009-01-26 10:04 ` Jan Kara
2009-05-31 14:49 ` [PATCH 0/8] kernel:lockdep:replace DFS with BFS tom.leiming
2009-05-31 14:49 ` [PATCH 1/8] kernel:lockdep:improve implementation of BFS tom.leiming
2009-05-31 14:49 ` [PATCH 2/8] kernel:lockdep: introduce match function to BFS tom.leiming
2009-05-31 14:49 ` [PATCH 3/8] kernel:lockdep:implement check_noncircular() by BFS tom.leiming
2009-05-31 14:49 ` [PATCH 4/8] kernel:lockdep:implement find_usage_*wards " tom.leiming
2009-05-31 14:49 ` [PATCH 5/8] kernel:lockdep:introduce print_shortest_lock_dependencies tom.leiming
2009-05-31 14:49 ` [PATCH 6/8] kernel:lockdep: implement lockdep_count_*ward_deps by BFS tom.leiming
2009-05-31 14:49 ` [PATCH 7/8] kernel:lockdep: update memory usage introduced " tom.leiming
2009-05-31 14:49 ` [PATCH 8/8] kernel:lockdep:add statistics info for max bfs queue depth tom.leiming
2009-05-31 15:14 ` [PATCH 4/8] kernel:lockdep:implement find_usage_*wards by BFS Daniel Walker
2009-06-01 0:14 ` Ming Lei
2009-06-08 12:22 ` [PATCH 0/8] kernel:lockdep:replace DFS with BFS Peter Zijlstra
2009-06-08 13:38 ` Ming Lei
2009-06-08 13:58 ` Ming Lei
2009-06-08 14:04 ` Peter Zijlstra
2009-06-08 15:50 ` Ming Lei
2009-06-09 12:52 ` Ming Lei
2009-07-28 16:34 ` [U-Boot] [RFC 0/3] uboot-doc User's Manual Generation Tool John Schmoller
2009-07-28 17:49 ` Wolfgang Denk
2009-07-28 20:40 ` jschmoller
2009-07-28 21:27 ` Wolfgang Denk
2009-07-28 22:16 ` Robin Getz
2009-07-30 9:59 ` Detlev Zundel
2009-07-30 18:45 ` Wolfgang Denk
2009-07-30 19:50 ` Robin Getz
2009-07-30 19:55 ` Wolfgang Denk
2009-07-31 1:49 ` Robin Getz
2009-08-13 7:32 ` Mike Frysinger
2009-07-29 14:48 ` jschmoller
2009-07-28 16:34 ` [U-Boot] [RFC 1/3] uboot-doc: Initial support of user documentation generator John Schmoller
2009-07-28 16:34 ` [U-Boot] [RFC 2/3] uboot-doc: Add example support for uboot-doc John Schmoller
2009-07-28 17:52 ` Wolfgang Denk
2009-07-28 20:42 ` jschmoller
2009-07-28 21:37 ` Wolfgang Denk
2009-07-28 16:34 ` [U-Boot] [RFC 3/3] xpedite5370: Add uboot-doc support John Schmoller
2009-10-07 13:49 ` [PATCH 1/1] perf tools: Up the verbose level for some really verbose stuff Arnaldo Carvalho de Melo
2009-10-08 17:31 ` [tip:perf/core] " tip-bot for Arnaldo Carvalho de Melo
2010-06-22 15:20 ` [RFC][PATCH 00/10] cifs: local caching support using FS-Cache Suresh Jayaraman
2010-06-22 15:20 ` Suresh Jayaraman
2010-06-22 15:22 ` [RFC][PATCH 01/10] cifs: add kernel config option for CIFS Client caching support Suresh Jayaraman
2010-06-22 15:22 ` [RFC][PATCH 02/10] cifs: guard cifsglob.h against multiple inclusion Suresh Jayaraman
[not found] ` <1277220170-3442-1-git-send-email-sjayaraman-l3A5Bk7waGM@public.gmane.org>
2010-06-22 21:37 ` Jeff Layton
2010-06-22 21:37 ` Jeff Layton
2010-06-22 15:23 ` [RFC][PATCH 03/10] cifs: register CIFS for caching Suresh Jayaraman
2010-06-22 15:23 ` Suresh Jayaraman
2010-06-22 15:23 ` [RFC][PATCH 04/10] cifs: define server-level cache index objects and register them with FS-Cache Suresh Jayaraman
2010-06-22 15:23 ` Suresh Jayaraman
[not found] ` <1277220198-3522-1-git-send-email-sjayaraman-l3A5Bk7waGM@public.gmane.org>
2010-06-22 21:52 ` Jeff Layton
2010-06-22 21:52 ` Jeff Layton
[not found] ` <20100622175214.4c56234f-4QP7MXygkU+dMjc06nkz3ljfA9RmPOcC@public.gmane.org>
2010-06-23 5:34 ` Suresh Jayaraman
2010-06-23 5:34 ` Suresh Jayaraman
2010-06-22 15:23 ` [RFC][PATCH 05/10] cifs: define superblock-level cache index objects and register them Suresh Jayaraman
2010-06-22 15:23 ` Suresh Jayaraman
2010-06-22 15:23 ` [RFC][PATCH 06/10] cifs: define inode-level cache object " Suresh Jayaraman
2010-06-22 15:23 ` [RFC][PATCH 07/10] cifs: FS-Cache page management Suresh Jayaraman
2010-06-22 15:24 ` [RFC][PATCH 08/10] cifs: store pages into local cache Suresh Jayaraman
2010-06-22 15:24 ` [RFC][PATCH 09/10] cifs: read pages from FS-Cache Suresh Jayaraman
2010-06-22 15:24 ` Suresh Jayaraman
2010-06-22 15:25 ` [RFC][PATCH 10/10] cifs: add mount option to enable local caching Suresh Jayaraman
2010-06-22 15:25 ` Suresh Jayaraman
2010-06-23 18:32 ` Scott Lovenberg
[not found] ` <4C225338.9010807-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2010-06-25 10:48 ` Suresh Jayaraman
2010-06-25 10:48 ` Suresh Jayaraman
[not found] ` <1277220189-3485-1-git-send-email-sjayaraman-l3A5Bk7waGM@public.gmane.org>
2010-06-23 16:51 ` [RFC][PATCH 03/10] cifs: register CIFS for caching David Howells
2010-06-23 16:51 ` David Howells
[not found] ` <9603.1277311877-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2010-06-25 10:56 ` Suresh Jayaraman
2010-06-25 10:56 ` Suresh Jayaraman
2010-06-23 16:54 ` [RFC][PATCH 04/10] cifs: define server-level cache index objects and register them with FS-Cache David Howells
[not found] ` <1277220206-3559-1-git-send-email-sjayaraman-l3A5Bk7waGM@public.gmane.org>
2010-06-23 16:58 ` [RFC][PATCH 05/10] cifs: define superblock-level cache index objects and register them David Howells
2010-06-23 16:58 ` David Howells
[not found] ` <9720.1277312290-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2010-06-25 12:44 ` Suresh Jayaraman
2010-06-25 12:44 ` Suresh Jayaraman
2010-06-25 12:58 ` David Howells
[not found] ` <22746.1277470713-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2010-06-25 13:26 ` David Howells
2010-06-25 13:26 ` David Howells
[not found] ` <23204.1277472412-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2010-06-28 12:53 ` Suresh Jayaraman
2010-06-28 12:53 ` Suresh Jayaraman
2010-06-28 13:24 ` David Howells
[not found] ` <1277220214-3597-1-git-send-email-sjayaraman-l3A5Bk7waGM@public.gmane.org>
2010-06-23 17:02 ` [RFC][PATCH 06/10] cifs: define inode-level cache object " David Howells
2010-06-23 17:02 ` David Howells
[not found] ` <9822.1277312573-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2010-06-25 12:50 ` Suresh Jayaraman
2010-06-25 12:50 ` Suresh Jayaraman
[not found] ` <4C24A606.5040001-l3A5Bk7waGM@public.gmane.org>
2010-06-25 12:55 ` David Howells
2010-06-25 12:55 ` David Howells
[not found] ` <22697.1277470549-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
2010-06-25 16:53 ` Jeff Layton
2010-06-25 16:53 ` Jeff Layton
2010-06-25 21:46 ` David Howells
2010-06-25 22:26 ` Jeff Layton
2010-06-25 22:26 ` Jeff Layton
2010-06-25 23:05 ` Steve French
2010-06-25 23:05 ` Steve French
2010-06-26 0:52 ` Mingming Cao
2010-06-27 18:17 ` Aneesh Kumar K. V
[not found] ` <871vbscpce.fsf-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org>
2010-06-27 18:22 ` Christoph Hellwig
2010-06-27 18:22 ` Christoph Hellwig
[not found] ` <20100625182651.36800d06-9yPaYZwiELC+kQycOl6kW4xkIHaj4LzF@public.gmane.org>
2010-06-25 23:04 ` David Howells
2010-06-25 23:04 ` David Howells
2010-06-23 17:05 ` [RFC][PATCH 07/10] cifs: FS-Cache page management David Howells
[not found] ` <1277220240-3674-1-git-send-email-sjayaraman-l3A5Bk7waGM@public.gmane.org>
2010-06-23 17:06 ` [RFC][PATCH 08/10] cifs: store pages into local cache David Howells
2010-06-23 17:06 ` David Howells
[not found] ` <1277220261-3717-1-git-send-email-sjayaraman-l3A5Bk7waGM@public.gmane.org>
2010-06-23 17:07 ` [RFC][PATCH 09/10] cifs: read pages from FS-Cache David Howells
2010-06-23 17:07 ` David Howells
2010-06-23 17:08 ` [RFC][PATCH 10/10] cifs: add mount option to enable local caching David Howells
2010-08-11 5:21 ` [PATCH v3] OpenRD: Enable SD/UART selection for serial port 1 Tanmay Upadhyay
2010-08-11 7:27 ` Russell King - ARM Linux
2011-02-03 9:49 ` [PATCH 1/7] usb: otg: enable regulator only on cable/device connect Hema HK
2011-02-03 9:49 ` [PATCH 2/7] usb: otg: Remove one unnecessary I2C read request Hema HK
2011-02-03 9:49 ` [PATCH 3/7] usb: otg: OMAP4430: Introducing suspend function for power management Hema HK
2011-02-03 9:49 ` [PATCH 4/7] usb: otg: OMAP4430: Add phy_suspend function pointer to twl4030_usb_data Hema HK
2011-02-03 13:45 ` Sergei Shtylyov
[not found] ` <4D4AB187.50406-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
2011-02-04 5:23 ` Hema Kalliguddi
2011-02-03 13:50 ` Sergei Shtylyov
[not found] ` <4D4AB2A5.7000002-hkdhdckH98+B+jHODAdFcQ@public.gmane.org>
2011-02-04 6:03 ` Hema Kalliguddi
2011-02-03 9:49 ` [PATCH 5/7] usb: otg: TWL6030: Introduce the twl6030_phy_suspend function Hema HK
2011-02-03 9:49 ` [PATCH 6/7] usb: otg: TWL6030 Save the last event in otg_transceiver Hema HK
2011-02-03 9:49 ` [PATCH 7/7] usb: musb: OMAP4430: Fix usb device detection if connected during boot Hema HK
2011-02-14 10:05 ` Felipe Balbi
2011-02-15 8:23 ` Hema Kalliguddi
2011-04-13 22:08 ` [PATCH 2/2] ltp-ddt: New recipe to build ltp-ddt test tool Carlos Hernandez
2011-05-02 21:01 ` [U-Boot] [PATCH v4 0/5] Add support for LaCie NAS Network Space v2 Simon Guinot
2011-05-02 21:29 ` Wolfgang Denk
2011-05-02 22:46 ` Simon Guinot
2011-05-02 21:01 ` [U-Boot] [PATCH v4 1/5] sf: disable write protection for Macronix flash Simon Guinot
2011-05-02 21:07 ` Mike Frysinger
2011-05-02 21:01 ` [U-Boot] [PATCH v4 2/5] Kirkwood: allow to override CONFIG_SYS_TCLK Simon Guinot
2011-05-02 21:01 ` [U-Boot] [PATCH v4 3/5] mv-common.h: fix DRAM banks configuration Simon Guinot
2011-05-02 21:01 ` [U-Boot] [PATCH v4 4/5] netconsole: remove `serverip' check Simon Guinot
2011-05-02 21:01 ` [U-Boot] [PATCH v4 5/5] Add support for Network Space v2 Simon Guinot
2011-05-02 22:42 ` [U-Boot] [PATCH v5 0/5] Add support for LaCie NAS " Simon Guinot
2011-05-03 9:59 ` Prafulla Wadaskar
2011-05-02 22:42 ` [U-Boot] [PATCH v5 1/5] sf: disable write protection for Macronix flash Simon Guinot
2011-07-08 20:32 ` [U-Boot] [PATCH v6] sf: macronix: disable write protection when initializing Mike Frysinger
2011-08-02 20:02 ` Wolfgang Denk
2011-05-02 22:42 ` [U-Boot] [PATCH v5 2/5] Kirkwood: allow to override CONFIG_SYS_TCLK Simon Guinot
2011-05-03 12:09 ` Prafulla Wadaskar
2011-05-02 22:42 ` [U-Boot] [PATCH v5 3/5] mv-common.h: fix DRAM banks configuration Simon Guinot
2011-05-03 12:09 ` Prafulla Wadaskar
2011-05-02 22:42 ` [U-Boot] [PATCH v5 4/5] netconsole: remove `serverip' check Simon Guinot
2011-05-02 22:42 ` [U-Boot] [PATCH v5 5/5] Add support for Network Space v2 Simon Guinot
2011-05-03 13:19 ` Simon Guinot
2011-05-12 17:24 ` Wolfgang Denk
2011-06-15 0:46 ` [PATCH] Add ok2440 development board support Wu DaoGuang
2011-06-15 0:46 ` Wu DaoGuang
2011-06-22 5:55 ` [PATCH 3/3 v2] ARM: pxa168: Add board support for gplugD Tanmay Upadhyay
2011-07-06 12:20 ` Daniel Mack
2011-07-06 12:44 ` Eric Miao
2011-07-21 4:54 ` [PATCHV2] OMAP4: OPP: add OMAP4460 definitions Vishwanath BS
2011-07-21 4:54 ` Vishwanath BS
[not found] ` <4e27b0d0.100e8e0a.43e0.ffffe6d9SMTPIN_ADDED@mx.google.com>
2011-07-21 4:56 ` Vishwanath Sripathy
2011-07-21 4:56 ` Vishwanath Sripathy
2011-10-03 0:32 ` [PATCH 1/1] ARM: Make debug UART optional for S3C devices Thiago A. Correa
2011-10-03 0:32 ` Thiago A. Correa
2011-10-10 14:44 ` Thiago A. Corrêa
2011-10-10 14:44 ` Thiago A. Corrêa
2011-12-11 13:10 ` [PATCH] block: Needn't read the size of device or partition again taco
2012-01-08 15:28 ` [Qemu-devel] [PATCH] Add tab-completion for device_add Andrzej Zaborowski
2012-01-12 17:01 ` Anthony Liguori
2012-02-16 2:59 ` [U-Boot] [PATCH 0/5] Support for qualcomm msm7630 board mohamed.haneef at lntinfotech.com
2012-02-23 8:59 ` [U-Boot] reminder for " Mohamed Haneef
2012-10-26 21:15 ` [U-Boot] " Albert ARIBAUD
2012-02-16 2:59 ` [U-Boot] [PATCH 1/5] msm7x30: Add support for low speed uart on msm7x30 mohamed.haneef at lntinfotech.com
2012-02-28 23:44 ` Albert ARIBAUD
2012-03-05 14:34 ` [U-Boot] [PATCH v2 1/5] msm7x30: Add Support " Mohamed Haneef
2012-03-22 8:50 ` [U-Boot] reminder for [PATCH 0/5] Support for qualcomm msm7630 board mohamed.haneef at lntinfotech.com
2012-04-23 9:24 ` [U-Boot] (no subject) mohamed.haneef at lntinfotech.com
2012-04-23 9:31 ` [U-Boot] msm7630 mainline request mohamed.haneef at lntinfotech.com
2012-05-03 0:09 ` Marek Vasut
2012-02-16 2:59 ` [U-Boot] [PATCH 2/5] msm7x30: Add support for interprocessor communication mohamed.haneef at lntinfotech.com
2012-02-28 23:46 ` Albert ARIBAUD
2012-03-05 14:33 ` Mohamed Haneef
2012-02-16 2:59 ` [U-Boot] [PATCH 3/5] msm7x30: Add support for Qualcomm msm7630 soc mohamed.haneef at lntinfotech.com
2012-02-29 0:00 ` Albert ARIBAUD [this message]
2012-03-05 14:39 ` [U-Boot] [PATCH v2 3/5] msm7x30: Add support for msm7x30 SoC Mohamed Haneef
2012-02-16 2:59 ` [U-Boot] [PATCH 4/5] Add support for mmc read and writes mohamed.haneef at lntinfotech.com
2012-02-29 0:03 ` Albert ARIBAUD
2012-03-05 14:40 ` [U-Boot] [PATCH v2 4/5] Add Support for qc_mmc MMC Controller Mohamed Haneef
2012-05-03 22:05 ` Andy Fleming
2012-05-10 11:37 ` Mohamed Haneef
2012-02-16 2:59 ` [U-Boot] [PATCH 5/5] msm7x30: Add support for msm7630_surf board mohamed.haneef at lntinfotech.com
2012-10-03 8:19 ` Albert ARIBAUD
2012-06-08 17:23 ` [PATCH 1/4] slub: change declare of get_slab() to inline at all times Joonsoo Kim
2012-06-08 17:23 ` Joonsoo Kim
2012-06-08 17:23 ` [PATCH 2/4] slub: use __cmpxchg_double_slab() at interrupt disabled place Joonsoo Kim
2012-06-08 17:23 ` Joonsoo Kim
2012-06-08 17:23 ` [PATCH 3/4] slub: refactoring unfreeze_partials() Joonsoo Kim
2012-06-08 17:23 ` Joonsoo Kim
2012-06-20 7:19 ` Pekka Enberg
2012-06-20 7:19 ` Pekka Enberg
2012-06-08 17:23 ` [PATCH 4/4] slub: deactivate freelist of kmem_cache_cpu all at once in deactivate_slab() Joonsoo Kim
2012-06-08 17:23 ` Joonsoo Kim
2012-06-08 19:04 ` Christoph Lameter
2012-06-08 19:04 ` Christoph Lameter
2012-06-10 10:27 ` JoonSoo Kim
2012-06-10 10:27 ` JoonSoo Kim
2012-06-22 18:34 ` JoonSoo Kim
2012-06-22 18:34 ` JoonSoo Kim
2012-06-08 19:02 ` [PATCH 1/4] slub: change declare of get_slab() to inline at all times Christoph Lameter
2012-06-08 19:02 ` Christoph Lameter
2012-06-09 15:57 ` JoonSoo Kim
2012-06-09 15:57 ` JoonSoo Kim
2012-06-11 15:04 ` Christoph Lameter
2012-06-11 15:04 ` Christoph Lameter
2012-06-22 18:22 ` [PATCH 1/3] slub: prefetch next freelist pointer in __slab_alloc() Joonsoo Kim
2012-06-22 18:22 ` Joonsoo Kim
2012-06-22 18:22 ` [PATCH 2/3] slub: reduce failure of this_cpu_cmpxchg in put_cpu_partial() after unfreezing Joonsoo Kim
2012-06-22 18:22 ` Joonsoo Kim
2012-07-04 13:05 ` Pekka Enberg
2012-07-04 13:05 ` Pekka Enberg
2012-07-05 14:20 ` Christoph Lameter
2012-07-05 14:20 ` Christoph Lameter
2012-08-16 7:06 ` Pekka Enberg
2012-08-16 7:06 ` Pekka Enberg
2012-06-22 18:22 ` [PATCH 3/3] slub: release a lock if freeing object with a lock is failed in __slab_free() Joonsoo Kim
2012-06-22 18:22 ` Joonsoo Kim
2012-07-04 13:10 ` Pekka Enberg
2012-07-04 13:10 ` Pekka Enberg
2012-07-04 14:48 ` JoonSoo Kim
2012-07-04 14:48 ` JoonSoo Kim
2012-07-05 14:26 ` Christoph Lameter
2012-07-05 14:26 ` Christoph Lameter
2012-07-06 14:19 ` JoonSoo Kim
2012-07-06 14:19 ` JoonSoo Kim
2012-07-06 14:34 ` Christoph Lameter
2012-07-06 14:34 ` Christoph Lameter
2012-07-06 14:59 ` JoonSoo Kim
2012-07-06 14:59 ` JoonSoo Kim
2012-07-06 15:10 ` Christoph Lameter
2012-07-06 15:10 ` Christoph Lameter
2012-07-08 16:19 ` JoonSoo Kim
2012-07-08 16:19 ` JoonSoo Kim
2012-06-22 18:45 ` [PATCH 1/3 v2] slub: prefetch next freelist pointer in __slab_alloc() Joonsoo Kim
2012-06-22 18:45 ` Joonsoo Kim
2012-07-04 12:58 ` JoonSoo Kim
2012-07-04 12:58 ` JoonSoo Kim
2012-07-04 13:00 ` Pekka Enberg
2012-07-04 13:00 ` Pekka Enberg
2012-07-04 14:30 ` JoonSoo Kim
2012-07-04 14:30 ` JoonSoo Kim
2012-07-04 15:08 ` Pekka Enberg
2012-07-04 15:08 ` Pekka Enberg
2012-07-04 15:26 ` Eric Dumazet
2012-07-04 15:26 ` Eric Dumazet
2012-07-04 15:48 ` JoonSoo Kim
2012-07-04 15:48 ` JoonSoo Kim
2012-07-04 16:15 ` Eric Dumazet
2012-07-04 16:15 ` Eric Dumazet
2012-07-04 16:24 ` JoonSoo Kim
2012-07-04 16:24 ` JoonSoo Kim
2012-07-04 15:45 ` JoonSoo Kim
2012-07-04 15:45 ` JoonSoo Kim
2012-07-04 15:59 ` Pekka Enberg
2012-07-04 15:59 ` Pekka Enberg
2012-07-04 16:04 ` JoonSoo Kim
2012-07-04 16:04 ` JoonSoo Kim
2012-08-10 9:35 ` [PATCH BlueZ V5 1/5] AVRCP: Add TG Record to support AVRCP Browsing Vani-dineshbhai PATEL
2012-08-13 11:27 ` Luiz Augusto von Dentz
2012-08-13 11:49 ` Michal.Labedzki
2012-08-13 12:15 ` Luiz Augusto von Dentz
2012-09-20 7:28 ` [PATCH] mac80211 : Fix Ibss debug message Tx authentication yes
2012-09-20 7:55 ` Johannes Berg
2012-11-16 8:53 ` [PATCH] python: fix for Security Advisory - python - CVE-2012-2135 yanjun.zhu
2012-11-16 12:21 ` Otavio Salvador
2012-11-19 2:26 ` yzhu1
2012-11-19 2:36 ` yzhu1
2012-11-19 10:21 ` Otavio Salvador
2012-11-29 14:07 ` Paul Eggleton
2012-11-30 2:49 ` yzhu1
2013-02-07 17:33 ` [PATCH 00/10] usb: ehci: more bus glues as separate modules manjunath.goudar at linaro.org
2013-02-07 20:13 ` Ezequiel Garcia
2013-02-08 15:23 ` Alan Stern
[not found] ` <1360258447-27247-1-git-send-email-yes>
2013-02-07 17:33 ` [PATCH 01/10] USB:Changed omap2plus_defconfig to support OMAP USB static driver manjunath.goudar at linaro.org
2013-02-07 17:33 ` [PATCH 02/10] USB: EHCI: make ehci-omap a separate driver manjunath.goudar at linaro.org
2013-02-08 7:42 ` Felipe Balbi
2013-02-08 8:56 ` Roger Quadros
2013-02-07 17:34 ` [PATCH 03/10] USB: EHCI: make ehci-spear " manjunath.goudar at linaro.org
2013-02-08 4:27 ` Viresh Kumar
2013-02-07 17:34 ` [PATCH 04/10] USB: EHCI: make ehci-orion " manjunath.goudar
2013-02-07 17:34 ` manjunath.goudar at linaro.org
2013-02-07 19:41 ` Arnd Bergmann
2013-02-07 19:41 ` Arnd Bergmann
2013-02-08 10:38 ` Florian Fainelli
2013-02-08 10:38 ` Florian Fainelli
2013-02-07 17:34 ` [PATCH 05/10] USB: EHCI: make ehci-atmel " manjunath.goudar
2013-02-07 17:34 ` manjunath.goudar at linaro.org
2013-02-08 2:58 ` Bo Shen
2013-02-08 2:58 ` Bo Shen
2013-06-12 11:53 ` Jean-Christophe PLAGNIOL-VILLARD
2013-06-12 11:53 ` Jean-Christophe PLAGNIOL-VILLARD
2013-02-07 17:34 ` [PATCH 06/10] USB: EHCI: make ehci-s5p " manjunath.goudar at linaro.org
2013-02-07 18:49 ` Stephen Warren
2013-02-07 17:34 ` [PATCH 07/10] USB: EHCI: make ehci-mv " manjunath.goudar
2013-02-07 17:34 ` manjunath.goudar at linaro.org
2013-02-07 17:34 ` [PATCH 08/10] USB: EHCI: make ehci-vt8500 " manjunath.goudar
2013-02-07 17:34 ` manjunath.goudar at linaro.org
2013-02-07 18:54 ` Tony Prisk
2013-02-07 18:54 ` Tony Prisk
2013-02-07 17:34 ` [PATCH 09/10] USB: EHCI: make ehci-msm " manjunath.goudar
2013-02-07 17:34 ` manjunath.goudar at linaro.org
2013-02-07 18:48 ` Stephen Warren
2013-02-07 18:48 ` Stephen Warren
2013-02-07 19:05 ` David Brown
2013-02-07 19:05 ` David Brown
2013-02-07 17:34 ` [PATCH 10/10] USB: EHCI: make ehci-w90X900 " manjunath.goudar
2013-02-07 17:34 ` manjunath.goudar at linaro.org
2013-03-09 15:39 ` [meta-fsl-arm][PATCH] imx-base: add imx6dl mapping for firmware John Weber
2013-03-09 19:05 ` Otavio Salvador
2013-03-12 19:16 ` [fsl-community-bsp-base][PATCH] Add Wandboard Dual to README John Weber
2013-03-12 19:20 ` Otavio Salvador
2013-03-16 13:45 ` [meta-fsl-arm-extra][PATCH] linux-imx (3.0.35): fix sdhc platform data John Weber
2013-03-16 13:45 ` [meta-fsl-arm-extra][PATCH] linux-imx (3.0.35): remove staging driver for brcm80211 John Weber
2013-03-16 14:39 ` Otavio Salvador
2013-03-17 1:08 ` John Weber
2013-03-16 13:45 ` [meta-fsl-arm-extra][PATCH] linux-imx (3.0.35): add brcm80211 driver backported from v3.5 John Weber
2013-03-16 13:45 ` [meta-fsl-arm-extra][PATCH] linux-imx (3.0.35): enable brcm wifi in wandboard dual defconfig John Weber
2013-03-16 14:32 ` Otavio Salvador
2013-03-16 13:45 ` [meta-fsl-arm-extra][PATCH] linux-imx (3.0.35): wandboard: add brcm80211 support to bbappend John Weber
2013-03-16 14:31 ` Otavio Salvador
2013-03-16 13:45 ` [meta-fsl-arm-extra][PATCH] linux-firmware: add support for bcm4329 John Weber
2013-03-16 14:31 ` Otavio Salvador
2013-03-17 0:40 ` John Weber
2013-03-16 13:45 ` [meta-fsl-arm-extra][PATCH] conf/machine: add firmware rrecomends to wandboard-dual John Weber
2013-03-16 14:23 ` [meta-fsl-arm-extra][PATCH] linux-imx (3.0.35): fix sdhc platform data Otavio Salvador
2013-03-18 20:25 ` [meta-fsl-arm-extra][PATCH v2 0/5] Enable wifi support for Wandboard Dual John Weber
2013-03-18 20:25 ` [meta-fsl-arm-extra][PATCH v2 1/5] linux-imx (3.0.35): wandboard: fix sdhc platform data John Weber
2013-03-18 20:25 ` [meta-fsl-arm-extra][PATCH v2 2/5] linux-imx (3.0.35): wandboard: replace brcm80211 driver John Weber
2013-03-18 20:25 ` [meta-fsl-arm-extra][PATCH v2 3/5] linux-firmware: Add bbappend to include Broadcom wifi drivers John Weber
2013-03-18 20:25 ` [meta-fsl-arm-extra][PATCH v2 4/5] wandboard-wifi-support: add nvram file and create firmware links John Weber
2013-03-18 20:25 ` [meta-fsl-arm-extra][PATCH v2 5/5] wandboard-dual: Add wandboard-wifi-support to machine John Weber
2013-03-22 3:05 ` [meta-fsl-arm-extra][PATCH v2 0/5] Enable wifi support for Wandboard Dual Otavio Salvador
2013-03-22 8:13 ` Eric Bénard
2013-03-22 12:30 ` Otavio Salvador
2013-03-22 14:17 ` Eric Bénard
2013-03-22 14:23 ` Eric Bénard
2013-03-23 15:44 ` Otavio Salvador
2013-03-25 2:18 ` Fabio Estevam
2013-03-25 2:20 ` John Weber
2013-06-10 9:17 ` [PATCH v2 00/11] ARM:STixxxx: Add STixxxx platform and board support Srinivas KANDAGATLA
2013-06-10 9:17 ` Srinivas KANDAGATLA
2013-06-10 9:21 ` [PATCH v2 01/11] serial:st-asc: Add ST ASC driver Srinivas KANDAGATLA
2013-06-10 9:21 ` Srinivas KANDAGATLA
2013-06-10 9:35 ` Russell King - ARM Linux
2013-06-10 9:35 ` Russell King - ARM Linux
2013-06-10 9:35 ` Russell King - ARM Linux
2013-06-10 11:53 ` Srinivas KANDAGATLA
2013-06-10 11:53 ` Srinivas KANDAGATLA
2013-06-10 9:21 ` [PATCH v2 02/11] clocksource:global_timer: Add ARM global timer support Srinivas KANDAGATLA
2013-06-10 9:21 ` Srinivas KANDAGATLA
2013-06-10 9:21 ` Srinivas KANDAGATLA
[not found] ` <1370856087-6452-1-git-send-email-srinivas.kandagatla-qxv4g6HH51o@public.gmane.org>
2013-06-10 13:13 ` Linus Walleij
2013-06-10 13:13 ` Linus Walleij
[not found] ` <CACRpkdbQCRKBzRF4HzNsXHwXCLJJcFZ9T36GPmmYsnX1OfgGRg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-06-10 13:41 ` Srinivas KANDAGATLA
2013-06-10 13:41 ` Srinivas KANDAGATLA
2013-06-11 14:05 ` Srinivas KANDAGATLA
2013-06-11 14:05 ` Srinivas KANDAGATLA
[not found] ` <51B72E9A.6070006-qxv4g6HH51o@public.gmane.org>
2013-06-11 20:13 ` Linus Walleij
2013-06-11 20:13 ` Linus Walleij
2013-06-12 10:45 ` Srinivas KANDAGATLA
2013-06-12 10:45 ` Srinivas KANDAGATLA
2013-06-12 10:45 ` Srinivas KANDAGATLA
2013-06-10 9:21 ` [PATCH v2 03/11] regmap: Add regmap_field APIs Srinivas KANDAGATLA
2013-06-10 9:21 ` Srinivas KANDAGATLA
2013-06-10 9:21 ` Srinivas KANDAGATLA
2013-06-11 10:48 ` Mark Brown
2013-06-11 10:48 ` Mark Brown
2013-06-11 10:48 ` Mark Brown
2013-06-11 11:36 ` Srinivas KANDAGATLA
2013-06-11 11:36 ` Srinivas KANDAGATLA
2013-06-11 11:36 ` Srinivas KANDAGATLA
2013-06-10 9:22 ` [PATCH v2 04/11] mfd:stixxxx-syscfg: Add ST System Configuration support Srinivas KANDAGATLA
2013-06-10 9:22 ` Srinivas KANDAGATLA
[not found] ` <1370856147-6552-1-git-send-email-srinivas.kandagatla-qxv4g6HH51o@public.gmane.org>
2013-06-10 13:16 ` Linus Walleij
2013-06-10 13:16 ` Linus Walleij
2013-06-10 13:52 ` Srinivas KANDAGATLA
2013-06-10 13:52 ` Srinivas KANDAGATLA
2013-06-10 13:52 ` Srinivas KANDAGATLA
2013-06-10 14:02 ` Arnd Bergmann
2013-06-10 14:02 ` Arnd Bergmann
2013-06-10 14:02 ` Arnd Bergmann
2013-06-10 15:51 ` Srinivas KANDAGATLA
2013-06-10 15:51 ` Srinivas KANDAGATLA
2013-06-10 15:51 ` Srinivas KANDAGATLA
2013-06-11 7:41 ` Srinivas KANDAGATLA
2013-06-11 7:41 ` Srinivas KANDAGATLA
2013-06-11 7:41 ` Srinivas KANDAGATLA
2013-06-10 9:22 ` [PATCH v2 05/11] pinctrl:stixxxx: Add pinctrl and pinconf support Srinivas KANDAGATLA
2013-06-10 9:22 ` Srinivas KANDAGATLA
[not found] ` <1370856161-6600-1-git-send-email-srinivas.kandagatla-qxv4g6HH51o@public.gmane.org>
2013-06-16 12:17 ` Linus Walleij
2013-06-16 12:17 ` Linus Walleij
2013-06-17 13:31 ` Srinivas KANDAGATLA
2013-06-17 13:31 ` Srinivas KANDAGATLA
[not found] ` <51BF0FC2.4000601-qxv4g6HH51o@public.gmane.org>
2013-06-17 16:27 ` Linus Walleij
2013-06-17 16:27 ` Linus Walleij
2013-06-10 9:26 ` =?yes?q?=5BPATCH=20v2=2006/11=5D=20ARM=3Astixxxx=3A=20Add=20STiH415=20SOC=20support?= Srinivas KANDAGATLA
2013-06-10 9:26 ` =?yes?q?=5BPATCH=20v2=2006/11=5D=20ARM=3Astixxxx=3A=20Add=20STiH415=20SOC=20support?= Srinivas KANDAGATLA
2013-06-10 9:55 ` [PATCH v2 06/11] ARM:stixxxx: Add STiH415 SOC support Michal Simek
2013-06-10 9:55 ` Michal Simek
2013-06-10 11:08 ` Michal Simek
2013-06-10 11:08 ` Michal Simek
[not found] ` <CAHTX3d+dk3W_9b7SVUokWq4KYXnj=Z1=WPj5zJ-gUvJqqwE=+Q@mail.gmail.com>
2013-06-10 11:46 ` Srinivas KANDAGATLA
2013-06-10 11:46 ` Srinivas KANDAGATLA
2013-06-10 11:46 ` Srinivas KANDAGATLA
2013-06-10 23:19 ` Russell King - ARM Linux
2013-06-10 23:19 ` Russell King - ARM Linux
2013-06-10 23:19 ` Russell King - ARM Linux
2013-06-11 6:50 ` Srinivas KANDAGATLA
2013-06-11 6:50 ` Srinivas KANDAGATLA
2013-06-11 6:50 ` Srinivas KANDAGATLA
2013-06-13 11:56 ` Russell King - ARM Linux
2013-06-13 11:56 ` Russell King - ARM Linux
2013-06-13 11:56 ` Russell King - ARM Linux
2013-06-13 12:41 ` Srinivas KANDAGATLA
2013-06-13 12:41 ` Srinivas KANDAGATLA
2013-06-13 12:41 ` Srinivas KANDAGATLA
2013-06-13 12:47 ` Linus Walleij
2013-06-13 12:47 ` Linus Walleij
2013-06-13 12:47 ` Linus Walleij
[not found] ` <1370856381-6644-1-git-send-email-srinivas.kandagatla-qxv4g6HH51o@public.gmane.org>
2013-06-10 12:43 ` Linus Walleij
2013-06-10 12:43 ` Linus Walleij
[not found] ` <CACRpkdZ-xnDO+bte4tyKDWwY4A_qWUhLru3dUmuY9MQwseP3uQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2013-06-10 16:38 ` Srinivas KANDAGATLA
2013-06-10 16:38 ` Srinivas KANDAGATLA
[not found] ` <51B6011E.1060909-qxv4g6HH51o@public.gmane.org>
2013-06-14 7:31 ` Srinivas KANDAGATLA
2013-06-14 7:31 ` Srinivas KANDAGATLA
[not found] ` <51BAC6EC.8000703-qxv4g6HH51o@public.gmane.org>
2013-06-19 18:59 ` Linus Walleij
2013-06-19 18:59 ` Linus Walleij
2013-06-10 9:27 ` [PATCH v2 07/11] ARM:stixxxx: Add STiH416 " Srinivas KANDAGATLA
2013-06-10 9:27 ` Srinivas KANDAGATLA
2013-06-10 13:52 ` Arnd Bergmann
2013-06-10 13:52 ` Arnd Bergmann
2013-06-10 16:17 ` Srinivas KANDAGATLA
2013-06-10 16:17 ` Srinivas KANDAGATLA
2013-06-14 7:12 ` Srinivas KANDAGATLA
2013-06-14 7:12 ` Srinivas KANDAGATLA
2013-06-19 18:34 ` Linus Walleij
2013-06-19 18:34 ` Linus Walleij
2013-06-10 9:27 ` [PATCH v2 08/11] ARM:stixxxx: Add DEBUG_LL console support Srinivas KANDAGATLA
2013-06-10 9:27 ` Srinivas KANDAGATLA
2013-06-10 9:27 ` Srinivas KANDAGATLA
2013-06-10 9:27 ` [PATCH v2 09/11] ARM:stixxxx: Add stixxxx options to multi_v7_defconfig Srinivas KANDAGATLA
2013-06-10 9:27 ` Srinivas KANDAGATLA
2013-06-10 10:40 ` Mark Rutland
2013-06-10 10:40 ` Mark Rutland
2013-06-10 10:40 ` Mark Rutland
2013-06-10 10:58 ` Srinivas KANDAGATLA
2013-06-10 10:58 ` Srinivas KANDAGATLA
2013-06-10 10:58 ` Srinivas KANDAGATLA
2013-06-10 13:15 ` Mark Rutland
2013-06-10 13:15 ` Mark Rutland
2013-06-10 13:15 ` Mark Rutland
2013-06-13 9:24 ` Srinivas KANDAGATLA
2013-06-13 9:24 ` Srinivas KANDAGATLA
2013-06-13 9:24 ` Srinivas KANDAGATLA
2013-06-17 9:32 ` Mark Rutland
2013-06-17 9:32 ` Mark Rutland
2013-06-17 9:32 ` Mark Rutland
2013-06-10 9:28 ` [PATCH v2 10/11] ARM:stih41x: Add B2000 board support Srinivas KANDAGATLA
2013-06-10 9:28 ` Srinivas KANDAGATLA
2013-06-10 9:28 ` Srinivas KANDAGATLA
2013-06-10 9:28 ` [PATCH v2 11/11] ARM:stih41x: Add B2020 " Srinivas KANDAGATLA
2013-06-10 9:28 ` Srinivas KANDAGATLA
2013-06-10 9:28 ` Srinivas KANDAGATLA
2013-09-10 9:25 ` [PATCH 0/1] ideas to improve the write performance of cluster dm-raid1 dongmao zhang
2013-09-10 9:25 ` [PATCH 1/1] improve the performance of dm-log-userspace dongmao zhang
2013-09-12 8:42 ` [PATCH 1/1] OMAPDSS: Return right error during connector probe Sathya Prakash M R
2013-09-16 9:41 ` Tomi Valkeinen
2013-10-28 10:07 ` [PATCH 0/1] patches to improve cluster raid1 performance [V3] dongmao zhang
2013-10-28 10:07 ` [PATCH 1/1] improve the performance of dm-log-userspace dongmao zhang
2013-10-30 1:35 ` Brassow Jonathan
2013-10-28 10:17 ` [PATCH 0/2] cmirror patch to improve cluster raid1 performance[v3] dongmao zhang
2013-10-28 10:17 ` [PATCH 1/2] add integrated_flush support to device-mapper dongmao zhang
2013-10-28 10:17 ` [PATCH 2/2] cmirrord support DM_INTEGRATED_FLUSH dongmao zhang
2013-10-30 1:48 ` Brassow Jonathan
2013-10-30 1:47 ` [PATCH 1/2] add integrated_flush support to device-mapper Brassow Jonathan
2014-01-13 6:51 ` [PATCH 0/2] Optimization on intel HDMI detect and get_modes Ramalingam C
2014-01-13 6:51 ` [PATCH 1/2] drm/i915: HDMI detection based on HPD pin live status Ramalingam C
2014-01-13 6:51 ` [PATCH 2/2] drm/i915: Optimize EDID retrival on detect and get_modes Ramalingam C
2014-01-13 7:29 ` [PATCH 0/2] Optimization on intel HDMI " Daniel Vetter
2014-01-13 9:39 ` Sharma, Shashank
2014-01-13 13:26 ` Daniel Vetter
2014-01-13 17:19 ` Sharma, Shashank
2014-04-09 6:19 ` Wang, Quanxian
2014-04-09 6:50 ` Sharma, Shashank
2014-04-10 6:46 ` Sharma, Shashank
2014-04-10 8:08 ` Daniel Vetter
2014-04-10 8:10 ` Sharma, Shashank
2014-04-10 10:42 ` Wang, Quanxian
[not found] ` <FF3DDC77922A8A4BB08A3BC48A1EA8CB01692A7B@BGSMSX101.gar.corp.intel.com>
2014-04-11 12:58 ` Daniel Vetter
2014-04-11 13:23 ` Sharma, Shashank
2014-04-11 14:22 ` Daniel Vetter
2014-04-11 14:48 ` Sharma, Shashank
2014-07-16 14:29 ` Kumar, Shobhit
2014-02-07 23:23 ` [U-Boot] [U-Boot: RESEND][PATCH 0/7] Add support for Keystone2 SoC and K2HK EVM Murali Karicheri
2014-02-07 23:23 ` [U-Boot] [U-Boot:RESEND][[PATCH 1/7] fdt: call ft_board_setup_ex() at the end of image_setup_libfdt() Murali Karicheri
2014-02-10 21:25 ` Tom Rini
2014-02-11 1:05 ` Vitaly Andrianov
2014-02-07 23:23 ` [U-Boot] [U-Boot:RESEND][[PATCH 2/7] tools: sort the entries in Makefile Murali Karicheri
2014-02-07 23:23 ` [U-Boot] [U-Boot:RESEND][[PATCH 3/7 v1] tools: mkimage: add support for gpimage format Murali Karicheri
2014-02-07 23:23 ` [U-Boot] [U-Boot:RESEND][[PATCH 4/7 v1] arm: add support for arch timer Murali Karicheri
2014-02-07 23:23 ` [U-Boot] [U-Boot:RESEND][[PATCH 5/7 v1] NAND: DaVinci: allow forced disable of subpage writes Murali Karicheri
2014-02-07 23:23 ` [U-Boot] [U-Boot:RESEND][[PATCH 6/7] k2hk: add support for k2hk SOC and EVM Murali Karicheri
2014-02-10 21:25 ` Tom Rini
2014-02-11 1:44 ` Vitaly Andrianov
2014-02-12 12:53 ` Tom Rini
2014-02-17 21:19 ` Andrianov, Vitaly
2014-02-17 21:57 ` Tom Rini
2014-02-20 17:27 ` Andrianov, Vitaly
2014-02-10 8:32 ` [U-Boot] [U-Boot: RESEND][PATCH 0/7] Add support for Keystone2 SoC and K2HK EVM Albert ARIBAUD
2014-02-10 17:22 ` Murali Karicheri
2014-02-10 18:01 ` Albert ARIBAUD
2014-02-10 19:42 ` Murali Karicheri
2014-02-10 19:58 ` Albert ARIBAUD
2014-02-10 21:23 ` Tom Rini
2014-02-20 17:55 ` [U-Boot] [U-Boot PATCH v2 00/12] Add support for keystone2 " Murali Karicheri
2014-02-20 17:55 ` [U-Boot] [U-Boot PATCH v2 01/12] fdt: call ft_board_setup_ex() at the end of image_setup_libfdt() Murali Karicheri
2014-02-25 22:10 ` Tom Rini
2014-02-20 17:55 ` [U-Boot] [U-Boot PATCH v2 02/12] tools: sort the entries in Makefile Murali Karicheri
2014-02-25 22:10 ` Tom Rini
2014-02-20 17:55 ` [U-Boot] [U-Boot PATCH v2 03/12] tools: mkimage: add support for gpimage format Murali Karicheri
2014-02-25 22:11 ` Tom Rini
2014-02-20 17:55 ` [U-Boot] [U-Boot PATCH v2 04/12] arm: add support for arch timer Murali Karicheri
2014-02-25 22:11 ` Tom Rini
2014-02-20 17:55 ` [U-Boot] [U-Boot PATCH v2 05/12] NAND: DaVinci: allow forced disable of subpage writes Murali Karicheri
2014-02-25 22:11 ` Tom Rini
2014-02-26 4:01 ` Scott Wood
2014-02-27 16:38 ` Murali Karicheri
[not found] ` <3E54258959B69E4282D79E01AB1F32B7046C27D5@DFLE11.ent.ti.com>
2014-02-27 19:21 ` Scott Wood
2014-02-27 21:20 ` Murali Karicheri
2014-02-20 17:55 ` [U-Boot] [U-Boot PATCH v2 06/12] i2c, davinci: move i2c_defs.h to the drivers/i2c directory Murali Karicheri
2014-02-25 22:11 ` Tom Rini
2014-02-20 17:55 ` [U-Boot] [U-Boot PATCH v2 07/12] i2c, davinci: add support for multiple i2c buses Murali Karicheri
2014-02-25 22:11 ` Tom Rini
2014-02-20 17:55 ` [U-Boot] [U-Boot PATCH v2 08/12] k2hk: add support for k2hk SOC and EVM Murali Karicheri
2014-02-25 22:11 ` Tom Rini
2014-03-03 18:20 ` Murali Karicheri
2014-03-03 18:29 ` Tom Rini
2014-03-06 19:09 ` Andrianov, Vitaly
2014-03-06 19:29 ` Tom Rini
2014-03-07 16:41 ` Andrianov, Vitaly
2014-03-07 16:50 ` Tom Rini
2014-03-07 21:21 ` Murali Karicheri
2014-03-07 21:27 ` Tom Rini
2014-02-20 17:55 ` [U-Boot] [U-Boot PATCH v2 09/12] keystone2: add keystone multicore navigator driver Murali Karicheri
2014-02-25 22:12 ` Tom Rini
2014-02-20 17:55 ` [U-Boot] [U-Boot PATCH v2 10/12] keystone2: net: add keystone ethernet driver Murali Karicheri
2014-02-25 22:11 ` Tom Rini
2014-03-12 19:04 ` Murali Karicheri
2014-03-12 20:01 ` Tom Rini
2014-02-20 17:55 ` [U-Boot] [U-Boot PATCH v2 11/12] spi: davinci: add support for multiple bus and chip select Murali Karicheri
2014-02-25 22:12 ` Tom Rini
2014-02-20 17:55 ` [U-Boot] [U-Boot PATCH v2 12/12] k2hk-evm: add configuration for spi1 and spi2 support Murali Karicheri
2014-02-25 22:12 ` Tom Rini
2014-02-25 22:10 ` [U-Boot] [U-Boot PATCH v2 00/12] Add support for keystone2 SoC and K2HK EVM Tom Rini
2014-02-27 16:18 ` Karicheri, Muralidharan
2014-03-12 19:21 ` Murali Karicheri
2014-03-12 19:35 ` Tom Rini
2014-02-25 22:49 ` Karicheri, Muralidharan
2014-02-25 22:51 ` Tom Rini
2014-08-12 6:40 ` [PATCH v3] uas: replace WARN_ON_ONCE() with lockdep_assert_held() Sanjeev Sharma
2014-08-12 6:40 ` Sanjeev Sharma
2014-08-12 6:28 ` Hans de Goede
2014-08-12 6:37 ` Sharma, Sanjeev
2014-08-19 6:33 ` Sharma, Sanjeev
2014-08-19 6:33 ` Sharma, Sanjeev
2014-08-19 9:30 ` gregkh
2014-08-19 9:38 ` Sharma, Sanjeev
2014-08-19 9:38 ` Sharma, Sanjeev
2014-09-04 7:06 ` Sharma, Sanjeev
2014-09-04 13:50 ` [PATCH] Staging: rtl8192u: fix brace style coding issue in r819xU_firmware.c linux.delve
2014-09-04 13:51 ` [PATCH] Staging: rtl8192u: fix brace style coding issue in r819xU_firmware.c This is a patch to the file r819xU_firmware.c that fixes a brace warning found by checkpatch.pl tool linux.delve
2014-09-04 14:09 ` [PATCH] Staging: rtl8192u: fix brace style coding issue in r819xU_firmware.c Chaitra Ramaiah
2014-09-04 14:09 ` [PATCH] Staging: rtl8192u: fix brace style coding issue in r819xU_firmware.c This is a patch to the file r819xU_firmware.c that fixes a brace warning found by checkpatch.pl tool Chaitra Ramaiah
2014-09-04 14:28 ` Greg KH
2014-09-04 14:33 ` Dan Carpenter
2014-09-04 14:27 ` [PATCH] Staging: rtl8192u: fix brace style coding issue in r819xU_firmware.c Greg KH
2014-10-29 20:28 ` [PATCH v2 0/4] Enable PCI controller for Keystone SoCs Murali Karicheri
2014-10-29 20:28 ` Murali Karicheri
2014-10-29 20:28 ` Murali Karicheri
2014-10-29 20:28 ` [PATCH v2 1/4] ARM: keystone: add pcie related options Murali Karicheri
2014-10-29 20:28 ` Murali Karicheri
2014-10-29 20:28 ` [PATCH v2 2/4] ARM: keystone: defconfig: add options to enable PCI controller Murali Karicheri
2014-10-29 20:28 ` Murali Karicheri
2014-10-29 20:28 ` [PATCH v2 3/4] ARM: dts: keystone: add DT bindings for PCI controller for port 0 Murali Karicheri
2014-10-29 20:28 ` Murali Karicheri
2014-10-29 20:28 ` Murali Karicheri
2014-10-29 20:28 ` [PATCH v2 4/4] ARM: dts: keystone-k2e: add DT bindings for PCI controller for port 1 Murali Karicheri
2014-10-29 20:28 ` Murali Karicheri
2014-10-29 20:28 ` Murali Karicheri
2014-10-29 21:10 ` [PATCH v2 0/4] Enable PCI controller for Keystone SoCs santosh shilimkar
2014-10-29 21:10 ` santosh shilimkar
2015-02-12 7:56 ` [PATCH] pinctrl: mediatek: Fix build error in Mediatek pinctrl driver Hongzhou Yang
2015-02-20 10:04 ` Linus Walleij
2015-02-20 10:04 ` Linus Walleij
2015-02-20 10:04 ` Linus Walleij
2015-02-20 10:04 ` Linus Walleij
2015-07-27 8:16 ` [PATCH v1] mmc: sprd: add MMC host driver for Spreadtrum SoC Billows Wu
2015-10-19 2:27 ` [RFC PATCH] qspinlock: Improve performance by reducing load instruction rollback ling.ma.program
2015-10-19 7:58 ` Ingo Molnar
2015-10-19 9:34 ` Peter Zijlstra
2015-10-19 11:24 ` Ingo Molnar
2015-10-19 17:24 ` Waiman Long
2015-10-20 2:57 ` Ling Ma
2015-10-20 8:48 ` Ingo Molnar
2015-10-21 5:28 ` Ling Ma
2015-10-21 7:54 ` Peter Zijlstra
2015-10-20 9:15 ` Peter Zijlstra
2015-10-19 9:33 ` Peter Zijlstra
2015-10-19 17:20 ` Waiman Long
2015-10-20 3:00 ` Ling Ma
2015-10-19 9:46 ` Peter Zijlstra
2015-10-20 3:03 ` Ling Ma
2015-10-20 3:24 ` Ling Ma
2015-10-20 9:16 ` Peter Zijlstra
2015-10-21 5:30 ` Ling Ma
2015-10-19 17:18 ` Waiman Long
2015-10-20 3:12 ` Ling Ma
2015-10-20 18:55 ` Waiman Long
2015-10-21 5:43 ` Ling Ma
2015-12-31 8:09 ` [RFC PATCH] alispinlock: acceleration from lock integration on multi-core platform ling.ma.program
2016-01-05 18:46 ` Waiman Long
2016-01-08 22:48 ` Ling Ma
2016-01-05 21:18 ` Peter Zijlstra
2016-01-05 21:42 ` One Thousand Gnomes
2016-01-06 8:16 ` Peter Zijlstra
2016-01-06 8:21 ` Peter Zijlstra
2016-01-06 11:24 ` One Thousand Gnomes
2016-01-08 22:44 ` Ling Ma
2016-01-12 13:50 ` One Thousand Gnomes
2016-01-14 8:10 ` Ling Ma
2016-01-19 8:52 ` Ling Ma
2016-01-19 15:36 ` Waiman Long
2016-02-03 4:40 ` Ling Ma
2016-02-03 6:00 ` Ling Ma
2016-02-03 21:42 ` Waiman Long
2016-02-04 7:07 ` Ling Ma
2016-04-05 3:44 ` Ling Ma
2016-04-11 8:00 ` Ling Ma
2016-01-08 23:01 ` Ling Ma
2016-01-08 22:56 ` Ling Ma
2018-12-12 11:35 ` [PATCH] doc: add meson ut enhancements in prog guide Hari Kumar Vemula
2019-01-20 12:04 ` Thomas Monjalon
2019-01-23 6:37 ` [PATCH v2] doc: add meson ut info " Hari Kumar Vemula
2019-01-23 10:53 ` Bruce Richardson
2019-01-24 13:41 ` [PATCH v3] " Hari Kumar Vemula
2019-01-24 14:15 ` Richardson, Bruce
2019-01-25 6:20 ` [PATCH v4] " Hari Kumar Vemula
2019-01-31 14:49 ` Bruce Richardson
2019-02-02 10:28 ` [PATCH v5] " Hari Kumar Vemula
2019-03-04 17:05 ` Bruce Richardson
2019-04-22 22:35 ` [dpdk-dev] " Thomas Monjalon
2019-05-01 11:39 ` Mcnamara, John
2019-06-06 11:59 ` [dpdk-dev] [PATCH v6] " Hari Kumar Vemula
2019-07-08 19:40 ` Thomas Monjalon
2019-07-08 20:18 ` Aaron Conole
2019-07-09 18:57 ` Michael Santana Francisco
2019-07-22 12:39 ` Parthasarathy, JananeeX M
2019-07-22 12:53 ` Thomas Monjalon
2019-07-22 13:53 ` Bruce Richardson
2019-07-23 11:34 ` Parthasarathy, JananeeX M
2019-08-07 13:56 ` [dpdk-dev] [PATCH v7] " Agalya Babu RadhaKrishnan
2019-08-07 14:16 ` Jerin Jacob Kollanukkaran
2019-08-07 15:47 ` Michael Santana Francisco
2019-08-12 12:40 ` [dpdk-dev] [PATCH v8] " Jananee Parthasarathy
2020-02-16 10:28 ` Thomas Monjalon
2019-01-03 12:28 ` [PATCH v2] eal: fix core number validation Hari kumar Vemula
2019-01-03 13:03 ` David Marchand
2019-01-07 7:05 ` Hari Kumar Vemula
2019-01-07 10:25 ` [PATCH v3] " Hari Kumar Vemula
2019-01-10 10:11 ` David Marchand
2019-01-11 14:15 ` [PATCH v4] " Hari Kumar Vemula
2019-01-11 15:06 ` David Marchand
2019-01-14 10:28 ` [PATCH v5] " Hari Kumar Vemula
2019-01-14 14:39 ` David Marchand
2019-01-17 12:13 ` [PATCH v6] " Hari Kumar Vemula
2019-01-17 12:19 ` Bruce Richardson
2019-01-17 12:32 ` David Marchand
2019-01-17 16:31 ` [dpdk-stable] " Thomas Monjalon
2019-01-07 13:01 ` [PATCH] net/bonding: fix create bonded device test failure Hari Kumar Vemula
2019-01-07 18:44 ` Chas Williams
2019-01-08 10:27 ` [dpdk-stable] " Ferruh Yigit
2019-01-08 11:14 ` Vemula, Hari KumarX
2019-01-15 17:37 ` Pattan, Reshma
2019-01-28 7:28 ` [PATCH v2] " Hari Kumar Vemula
2019-01-31 23:40 ` Chas Williams
2019-02-05 13:39 ` [PATCH v3] " Hari Kumar Vemula
2019-02-07 13:34 ` [dpdk-stable] " Ferruh Yigit
2019-12-04 9:36 ` [PATCH] i386: pass CLZERO to guests with EPYC CPU model on AMD ZEN platform Ani Sinha
2019-12-16 9:31 ` Ani Sinha
[not found] ` <20220630112644.3682066-1-Shreyas.Karmahe@toshiba-tsip.com>
2022-07-01 11:32 ` [isar-cip-core] postinst:Added lines to verify Local and Remote Multi-factor Authentication Jan Kiszka
2022-07-01 11:33 ` Jan Kiszka
2022-07-04 16:51 ` Shreyas.Karmahe
2022-07-05 10:02 ` Jan Kiszka
2022-07-07 10:46 ` Shreyas.Karmahe
2011-05-02 5:59 ARM: pxa168: Add board support for gplugD Tanmay Upadhyay
2011-05-02 5:59 ` [PATCH 1/3] ARM: pxa168: Add support for UART3 Tanmay Upadhyay
2011-05-02 5:59 ` [PATCH 2/3] ARM: pxa168: Add support for Ethernet Tanmay Upadhyay
2011-06-10 13:31 ` Eric Miao
2011-05-02 6:00 ` [PATCH 3/3] ARM: pxa168: Add board support for gplugD Tanmay Upadhyay
2011-06-20 5:55 ` Eric Miao
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