From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:38620) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7W4q-00070h-03 for qemu-devel@nongnu.org; Tue, 13 Mar 2012 14:04:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S7W4P-00071G-0L for qemu-devel@nongnu.org; Tue, 13 Mar 2012 14:04:03 -0400 Received: from mail-gy0-f173.google.com ([209.85.160.173]:48547) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7W4O-00070z-RV for qemu-devel@nongnu.org; Tue, 13 Mar 2012 14:03:36 -0400 Received: by ghrr14 with SMTP id r14so965147ghr.4 for ; Tue, 13 Mar 2012 11:03:35 -0700 (PDT) Message-ID: <4F5F8BF3.2020807@codemonkey.ws> Date: Tue, 13 Mar 2012 13:03:31 -0500 From: Anthony Liguori MIME-Version: 1.0 References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331346496-10736-1-git-send-email-afaerber@suse.de> <1331346496-10736-5-git-send-email-afaerber@suse.de> In-Reply-To: <1331346496-10736-5-git-send-email-afaerber@suse.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH RFC v4 04/44] monitor: Avoid CPUState in read/write functions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= Cc: qemu-devel@nongnu.org On 03/09/2012 08:27 PM, Andreas Färber wrote: > Signed-off-by: Andreas Färber Reviewed-by: Anthony Liguori Regards, Anthony Liguori > --- > gdbstub.c | 56 ++++++++++++++++++++++++++++---------------------------- > 1 files changed, 28 insertions(+), 28 deletions(-) > > diff --git a/gdbstub.c b/gdbstub.c > index 7d470b6..054e16c 100644 > --- a/gdbstub.c > +++ b/gdbstub.c > @@ -533,7 +533,7 @@ static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; > #define IDX_XMM_REGS (IDX_FP_REGS + 16) > #define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS) > > -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_read_register(CPUX86State *env, uint8_t *mem_buf, int n) > { > if (n< CPU_NB_REGS) { > if (TARGET_LONG_BITS == 64&& env->hflags& HF_CS64_MASK) { > @@ -590,7 +590,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > return 0; > } > > -static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf) > +static int cpu_x86_gdb_load_seg(CPUX86State *env, int sreg, uint8_t *mem_buf) > { > uint16_t selector = ldl_p(mem_buf); > > @@ -615,7 +615,7 @@ static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf) > return 4; > } > > -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_write_register(CPUX86State *env, uint8_t *mem_buf, int n) > { > uint32_t tmp; > > @@ -703,7 +703,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > #define GDB_CORE_XML "power-core.xml" > #endif > > -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_read_register(CPUPPCState *env, uint8_t *mem_buf, int n) > { > if (n< 32) { > /* gprs */ > @@ -740,7 +740,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > return 0; > } > > -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_write_register(CPUPPCState *env, uint8_t *mem_buf, int n) > { > if (n< 32) { > /* gprs */ > @@ -801,7 +801,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > #define GET_REGA(val) GET_REGL(val) > #endif > > -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_read_register(CPUSPARCState *env, uint8_t *mem_buf, int n) > { > if (n< 8) { > /* g0..g7 */ > @@ -860,7 +860,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > return 0; > } > > -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_write_register(CPUSPARCState *env, uint8_t *mem_buf, int n) > { > #if defined(TARGET_ABI32) > abi_ulong tmp; > @@ -944,7 +944,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > #define NUM_CORE_REGS 26 > #define GDB_CORE_XML "arm-core.xml" > > -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_read_register(CPUARMState *env, uint8_t *mem_buf, int n) > { > if (n< 16) { > /* Core integer register. */ > @@ -971,7 +971,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > return 0; > } > > -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_write_register(CPUARMState *env, uint8_t *mem_buf, int n) > { > uint32_t tmp; > > @@ -1014,7 +1014,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > > #define GDB_CORE_XML "cf-core.xml" > > -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_read_register(CPUM68KState *env, uint8_t *mem_buf, int n) > { > if (n< 8) { > /* D0-D7 */ > @@ -1033,7 +1033,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > return 0; > } > > -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_write_register(CPUM68KState *env, uint8_t *mem_buf, int n) > { > uint32_t tmp; > > @@ -1058,7 +1058,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > > #define NUM_CORE_REGS 73 > > -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_read_register(CPUMIPSState *env, uint8_t *mem_buf, int n) > { > if (n< 32) { > GET_REGL(env->active_tc.gpr[n]); > @@ -1104,7 +1104,7 @@ static unsigned int ieee_rm[] = > #define RESTORE_ROUNDING_MODE \ > set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31& 3],&env->active_fpu.fp_status) > > -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_write_register(CPUMIPSState *env, uint8_t *mem_buf, int n) > { > target_ulong tmp; > > @@ -1163,7 +1163,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > > #define NUM_CORE_REGS 59 > > -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_read_register(CPUSH4State *env, uint8_t *mem_buf, int n) > { > if (n< 8) { > if ((env->sr& (SR_MD | SR_RB)) == (SR_MD | SR_RB)) { > @@ -1197,7 +1197,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > return 0; > } > > -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_write_register(CPUSH4State *env, uint8_t *mem_buf, int n) > { > uint32_t tmp; > > @@ -1244,7 +1244,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > > #define NUM_CORE_REGS (32 + 5) > > -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_read_register(CPUMBState *env, uint8_t *mem_buf, int n) > { > if (n< 32) { > GET_REG32(env->regs[n]); > @@ -1254,7 +1254,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > return 0; > } > > -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_write_register(CPUMBState *env, uint8_t *mem_buf, int n) > { > uint32_t tmp; > > @@ -1275,7 +1275,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > #define NUM_CORE_REGS 49 > > static int > -read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n) > +read_register_crisv10(CPUCRISState *env, uint8_t *mem_buf, int n) > { > if (n< 15) { > GET_REG32(env->regs[n]); > @@ -1307,7 +1307,7 @@ read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n) > return 0; > } > > -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_read_register(CPUCRISState *env, uint8_t *mem_buf, int n) > { > uint8_t srs; > > @@ -1337,7 +1337,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > return 0; > } > > -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_write_register(CPUCRISState *env, uint8_t *mem_buf, int n) > { > uint32_t tmp; > > @@ -1370,7 +1370,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > > #define NUM_CORE_REGS 67 > > -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_read_register(CPUAlphaState *env, uint8_t *mem_buf, int n) > { > uint64_t val; > CPU_DoubleU d; > @@ -1404,7 +1404,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > GET_REGL(val); > } > > -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_write_register(CPUAlphaState *env, uint8_t *mem_buf, int n) > { > target_ulong tmp = ldtul_p(mem_buf); > CPU_DoubleU d; > @@ -1440,7 +1440,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > > #define NUM_CORE_REGS S390_NUM_TOTAL_REGS > > -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_read_register(CPUS390XState *env, uint8_t *mem_buf, int n) > { > switch (n) { > case S390_PSWM_REGNUM: GET_REGL(env->psw.mask); break; > @@ -1464,7 +1464,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > return 0; > } > > -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_write_register(CPUS390XState *env, uint8_t *mem_buf, int n) > { > target_ulong tmpl; > uint32_t tmp32; > @@ -1494,7 +1494,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > #include "hw/lm32_pic.h" > #define NUM_CORE_REGS (32 + 7) > > -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_read_register(CPULM32State *env, uint8_t *mem_buf, int n) > { > if (n< 32) { > GET_REG32(env->regs[n]); > @@ -1527,7 +1527,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > return 0; > } > > -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_write_register(CPULM32State *env, uint8_t *mem_buf, int n) > { > uint32_t tmp; > > @@ -1573,7 +1573,7 @@ static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > #define NUM_CORE_REGS (env->config->gdb_regmap.num_regs) > #define num_g_regs NUM_CORE_REGS > > -static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_read_register(CPUXtensaState *env, uint8_t *mem_buf, int n) > { > const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n; > > @@ -1610,7 +1610,7 @@ static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n) > } > } > > -static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n) > +static int cpu_gdb_write_register(CPUXtensaState *env, uint8_t *mem_buf, int n) > { > uint32_t tmp; > const XtensaGdbReg *reg = env->config->gdb_regmap.reg + n;