From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:38899) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7W63-0000Ya-Ud for qemu-devel@nongnu.org; Tue, 13 Mar 2012 14:05:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S7W60-0007l8-Mk for qemu-devel@nongnu.org; Tue, 13 Mar 2012 14:05:19 -0400 Received: from mail-pz0-f47.google.com ([209.85.210.47]:64813) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7W60-0007kp-GO for qemu-devel@nongnu.org; Tue, 13 Mar 2012 14:05:16 -0400 Received: by dado14 with SMTP id o14so1350936dad.34 for ; Tue, 13 Mar 2012 11:05:14 -0700 (PDT) Message-ID: <4F5F8C56.5090209@codemonkey.ws> Date: Tue, 13 Mar 2012 13:05:10 -0500 From: Anthony Liguori MIME-Version: 1.0 References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331346496-10736-1-git-send-email-afaerber@suse.de> <1331346496-10736-9-git-send-email-afaerber@suse.de> In-Reply-To: <1331346496-10736-9-git-send-email-afaerber@suse.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH RFC v4 08/44] target-unicore32: Rename to CPUUniCore32State List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= Cc: qemu-devel@nongnu.org On 03/09/2012 08:27 PM, Andreas Färber wrote: > This aids in refactoring CPUState by adopting the common naming scheme. > > Signed-off-by: Andreas Färber Reviewed-by: Anthony Liguori Regards, Anthony Liguori > --- > target-unicore32/cpu.h | 8 ++++---- > 1 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h > index f725634..923db05 100644 > --- a/target-unicore32/cpu.h > +++ b/target-unicore32/cpu.h > @@ -18,7 +18,7 @@ > > #define ELF_MACHINE EM_UNICORE32 > > -#define CPUState struct CPUState_UniCore32 > +#define CPUState struct CPUUniCore32State > > #include "config.h" > #include "qemu-common.h" > @@ -27,7 +27,7 @@ > > #define NB_MMU_MODES 2 > > -typedef struct CPUState_UniCore32 { > +typedef struct CPUUniCore32State { > /* Regs for current mode. */ > uint32_t regs[32]; > /* Frequently accessed ASR bits are stored separately for efficiently. > @@ -71,7 +71,7 @@ typedef struct CPUState_UniCore32 { > /* Internal CPU feature flags. */ > uint32_t features; > > -} CPUState_UniCore32; > +} CPUUniCore32State; > > #define ASR_M (0x1f) > #define ASR_MODE_USER (0x10) > @@ -179,7 +179,7 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, > > void uc32_translate_init(void); > void do_interrupt(CPUState *); > -void switch_mode(CPUState_UniCore32 *, int); > +void switch_mode(CPUUniCore32State *, int); > > static inline bool cpu_has_work(CPUState *env) > {