From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([208.118.235.92]:59486) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7WBG-00080h-0J for qemu-devel@nongnu.org; Tue, 13 Mar 2012 14:10:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1S7WB7-0000V8-Jd for qemu-devel@nongnu.org; Tue, 13 Mar 2012 14:10:41 -0400 Received: from mail-pz0-f47.google.com ([209.85.210.47]:55063) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1S7WB7-0000Uh-5Z for qemu-devel@nongnu.org; Tue, 13 Mar 2012 14:10:33 -0400 Received: by dado14 with SMTP id o14so1357913dad.34 for ; Tue, 13 Mar 2012 11:10:31 -0700 (PDT) Message-ID: <4F5F8D93.80203@codemonkey.ws> Date: Tue, 13 Mar 2012 13:10:27 -0500 From: Anthony Liguori MIME-Version: 1.0 References: <1330893156-26569-1-git-send-email-afaerber@suse.de> <1331346496-10736-1-git-send-email-afaerber@suse.de> <1331346496-10736-14-git-send-email-afaerber@suse.de> In-Reply-To: <1331346496-10736-14-git-send-email-afaerber@suse.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH RFC v4 13/44] target-alpha: Don't overuse CPUState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?UTF-8?B?QW5kcmVhcyBGw6RyYmVy?= Cc: qemu-devel@nongnu.org On 03/09/2012 08:27 PM, Andreas Färber wrote: > Scripted conversion: > sed -i "s/CPUState/CPUAlphaState/g" target-alpha/*.[hc] > sed -i "s/#define CPUAlphaState/#define CPUState/" target-alpha/cpu.h Acked-by: Anthony Liguori For 13-42. I reviewed the target-i386 changes pretty closely and I'm confident that if the conversion went bad, we'll pick it up very quickly via a build or smoke test. Regards, Anthony Liguori > > Signed-off-by: Andreas Färber > --- > target-alpha/cpu.h | 24 ++++++++++---------- > target-alpha/helper.c | 18 +++++++------- > target-alpha/machine.c | 44 ++++++++++++++++++------------------ > target-alpha/op_helper.c | 6 ++-- > target-alpha/translate.c | 56 +++++++++++++++++++++++----------------------- > 5 files changed, 74 insertions(+), 74 deletions(-) > > diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h > index 5cd6fd8..ecc2a35 100644 > --- a/target-alpha/cpu.h > +++ b/target-alpha/cpu.h > @@ -375,7 +375,7 @@ enum { > PS_USER_MODE = 8 > }; > > -static inline int cpu_mmu_index(CPUState *env) > +static inline int cpu_mmu_index(CPUAlphaState *env) > { > if (env->pal_mode) { > return MMU_KERNEL_IDX; > @@ -430,16 +430,16 @@ int cpu_alpha_exec(CPUAlphaState *s); > is returned if the signal was handled by the virtual CPU. */ > int cpu_alpha_signal_handler(int host_signum, void *pinfo, > void *puc); > -int cpu_alpha_handle_mmu_fault (CPUState *env, uint64_t address, int rw, > +int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, uint64_t address, int rw, > int mmu_idx); > #define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault > -void do_interrupt (CPUState *env); > +void do_interrupt (CPUAlphaState *env); > > -uint64_t cpu_alpha_load_fpcr (CPUState *env); > -void cpu_alpha_store_fpcr (CPUState *env, uint64_t val); > +uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env); > +void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val); > #ifndef CONFIG_USER_ONLY > -void swap_shadow_regs(CPUState *env); > -QEMU_NORETURN void cpu_unassigned_access(CPUState *env1, > +void swap_shadow_regs(CPUAlphaState *env); > +QEMU_NORETURN void cpu_unassigned_access(CPUAlphaState *env1, > target_phys_addr_t addr, int is_write, > int is_exec, int unused, int size); > #endif > @@ -459,7 +459,7 @@ enum { > TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH<< TB_FLAGS_AMASK_SHIFT, > }; > > -static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, > +static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc, > target_ulong *cs_base, int *pflags) > { > int flags = 0; > @@ -481,7 +481,7 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, > } > > #if defined(CONFIG_USER_ONLY) > -static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) > +static inline void cpu_clone_regs(CPUAlphaState *env, target_ulong newsp) > { > if (newsp) { > env->ir[IR_SP] = newsp; > @@ -490,13 +490,13 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) > env->ir[IR_A3] = 0; > } > > -static inline void cpu_set_tls(CPUState *env, target_ulong newtls) > +static inline void cpu_set_tls(CPUAlphaState *env, target_ulong newtls) > { > env->unique = newtls; > } > #endif > > -static inline bool cpu_has_work(CPUState *env) > +static inline bool cpu_has_work(CPUAlphaState *env) > { > /* Here we are checking to see if the CPU should wake up from HALT. > We will have gotten into this state only for WTINT from PALmode. */ > @@ -513,7 +513,7 @@ static inline bool cpu_has_work(CPUState *env) > > #include "exec-all.h" > > -static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) > +static inline void cpu_pc_from_tb(CPUAlphaState *env, TranslationBlock *tb) > { > env->pc = tb->pc; > } > diff --git a/target-alpha/helper.c b/target-alpha/helper.c > index 06d2565..3f2e7c3 100644 > --- a/target-alpha/helper.c > +++ b/target-alpha/helper.c > @@ -24,7 +24,7 @@ > #include "cpu.h" > #include "softfloat.h" > > -uint64_t cpu_alpha_load_fpcr (CPUState *env) > +uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env) > { > uint64_t r = 0; > uint8_t t; > @@ -94,7 +94,7 @@ uint64_t cpu_alpha_load_fpcr (CPUState *env) > return r; > } > > -void cpu_alpha_store_fpcr (CPUState *env, uint64_t val) > +void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val) > { > uint8_t t; > > @@ -159,7 +159,7 @@ void cpu_alpha_store_fpcr (CPUState *env, uint64_t val) > } > > #if defined(CONFIG_USER_ONLY) > -int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw, > +int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, target_ulong address, int rw, > int mmu_idx) > { > env->exception_index = EXCP_MMFAULT; > @@ -167,7 +167,7 @@ int cpu_alpha_handle_mmu_fault (CPUState *env, target_ulong address, int rw, > return 1; > } > #else > -void swap_shadow_regs(CPUState *env) > +void swap_shadow_regs(CPUAlphaState *env) > { > uint64_t i0, i1, i2, i3, i4, i5, i6, i7; > > @@ -200,7 +200,7 @@ void swap_shadow_regs(CPUState *env) > } > > /* Returns the OSF/1 entMM failure indication, or -1 on success. */ > -static int get_physical_address(CPUState *env, target_ulong addr, > +static int get_physical_address(CPUAlphaState *env, target_ulong addr, > int prot_need, int mmu_idx, > target_ulong *pphys, int *pprot) > { > @@ -306,7 +306,7 @@ static int get_physical_address(CPUState *env, target_ulong addr, > return ret; > } > > -target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) > +target_phys_addr_t cpu_get_phys_page_debug(CPUAlphaState *env, target_ulong addr) > { > target_ulong phys; > int prot, fail; > @@ -315,7 +315,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) > return (fail>= 0 ? -1 : phys); > } > > -int cpu_alpha_handle_mmu_fault(CPUState *env, target_ulong addr, int rw, > +int cpu_alpha_handle_mmu_fault(CPUAlphaState *env, target_ulong addr, int rw, > int mmu_idx) > { > target_ulong phys; > @@ -336,7 +336,7 @@ int cpu_alpha_handle_mmu_fault(CPUState *env, target_ulong addr, int rw, > } > #endif /* USER_ONLY */ > > -void do_interrupt (CPUState *env) > +void do_interrupt (CPUAlphaState *env) > { > int i = env->exception_index; > > @@ -453,7 +453,7 @@ void do_interrupt (CPUState *env) > #endif /* !USER_ONLY */ > } > > -void cpu_dump_state (CPUState *env, FILE *f, fprintf_function cpu_fprintf, > +void cpu_dump_state (CPUAlphaState *env, FILE *f, fprintf_function cpu_fprintf, > int flags) > { > static const char *linux_reg_names[] = { > diff --git a/target-alpha/machine.c b/target-alpha/machine.c > index 76d70d9..1c9edd1 100644 > --- a/target-alpha/machine.c > +++ b/target-alpha/machine.c > @@ -21,8 +21,8 @@ static const VMStateInfo vmstate_fpcr = { > }; > > static VMStateField vmstate_cpu_fields[] = { > - VMSTATE_UINTTL_ARRAY(ir, CPUState, 31), > - VMSTATE_UINTTL_ARRAY(fir, CPUState, 31), > + VMSTATE_UINTTL_ARRAY(ir, CPUAlphaState, 31), > + VMSTATE_UINTTL_ARRAY(fir, CPUAlphaState, 31), > /* Save the architecture value of the fpcr, not the internally > expanded version. Since this architecture value does not > exist in memory to be stored, this requires a but of hoop > @@ -37,33 +37,33 @@ static VMStateField vmstate_cpu_fields[] = { > .flags = VMS_SINGLE, > .offset = 0 > }, > - VMSTATE_UINTTL(pc, CPUState), > - VMSTATE_UINTTL(unique, CPUState), > - VMSTATE_UINTTL(lock_addr, CPUState), > - VMSTATE_UINTTL(lock_value, CPUState), > + VMSTATE_UINTTL(pc, CPUAlphaState), > + VMSTATE_UINTTL(unique, CPUAlphaState), > + VMSTATE_UINTTL(lock_addr, CPUAlphaState), > + VMSTATE_UINTTL(lock_value, CPUAlphaState), > /* Note that lock_st_addr is not saved; it is a temporary > used during the execution of the st[lq]_c insns. */ > > - VMSTATE_UINT8(ps, CPUState), > - VMSTATE_UINT8(intr_flag, CPUState), > - VMSTATE_UINT8(pal_mode, CPUState), > - VMSTATE_UINT8(fen, CPUState), > + VMSTATE_UINT8(ps, CPUAlphaState), > + VMSTATE_UINT8(intr_flag, CPUAlphaState), > + VMSTATE_UINT8(pal_mode, CPUAlphaState), > + VMSTATE_UINT8(fen, CPUAlphaState), > > - VMSTATE_UINT32(pcc_ofs, CPUState), > + VMSTATE_UINT32(pcc_ofs, CPUAlphaState), > > - VMSTATE_UINTTL(trap_arg0, CPUState), > - VMSTATE_UINTTL(trap_arg1, CPUState), > - VMSTATE_UINTTL(trap_arg2, CPUState), > + VMSTATE_UINTTL(trap_arg0, CPUAlphaState), > + VMSTATE_UINTTL(trap_arg1, CPUAlphaState), > + VMSTATE_UINTTL(trap_arg2, CPUAlphaState), > > - VMSTATE_UINTTL(exc_addr, CPUState), > - VMSTATE_UINTTL(palbr, CPUState), > - VMSTATE_UINTTL(ptbr, CPUState), > - VMSTATE_UINTTL(vptptr, CPUState), > - VMSTATE_UINTTL(sysval, CPUState), > - VMSTATE_UINTTL(usp, CPUState), > + VMSTATE_UINTTL(exc_addr, CPUAlphaState), > + VMSTATE_UINTTL(palbr, CPUAlphaState), > + VMSTATE_UINTTL(ptbr, CPUAlphaState), > + VMSTATE_UINTTL(vptptr, CPUAlphaState), > + VMSTATE_UINTTL(sysval, CPUAlphaState), > + VMSTATE_UINTTL(usp, CPUAlphaState), > > - VMSTATE_UINTTL_ARRAY(shadow, CPUState, 8), > - VMSTATE_UINTTL_ARRAY(scratch, CPUState, 24), > + VMSTATE_UINTTL_ARRAY(shadow, CPUAlphaState, 8), > + VMSTATE_UINTTL_ARRAY(scratch, CPUAlphaState, 24), > > VMSTATE_END_OF_LIST() > }; > diff --git a/target-alpha/op_helper.c b/target-alpha/op_helper.c > index cc102db..c77f009 100644 > --- a/target-alpha/op_helper.c > +++ b/target-alpha/op_helper.c > @@ -1329,7 +1329,7 @@ static void QEMU_NORETURN do_unaligned_access(target_ulong addr, int is_write, > helper_excp(EXCP_UNALIGN, 0); > } > > -void QEMU_NORETURN cpu_unassigned_access(CPUState *env1, > +void QEMU_NORETURN cpu_unassigned_access(CPUAlphaState *env1, > target_phys_addr_t addr, int is_write, > int is_exec, int unused, int size) > { > @@ -1360,10 +1360,10 @@ void QEMU_NORETURN cpu_unassigned_access(CPUState *env1, > NULL, it means that the function was called in C code (i.e. not > from generated code or from helper.c) */ > /* XXX: fix it to restore all registers */ > -void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx, > +void tlb_fill(CPUAlphaState *env1, target_ulong addr, int is_write, int mmu_idx, > void *retaddr) > { > - CPUState *saved_env; > + CPUAlphaState *saved_env; > int ret; > > saved_env = env; > diff --git a/target-alpha/translate.c b/target-alpha/translate.c > index 1d2142b..b51fe5c 100644 > --- a/target-alpha/translate.c > +++ b/target-alpha/translate.c > @@ -105,35 +105,35 @@ static void alpha_translate_init(void) > for (i = 0; i< 31; i++) { > sprintf(p, "ir%d", i); > cpu_ir[i] = tcg_global_mem_new_i64(TCG_AREG0, > - offsetof(CPUState, ir[i]), p); > + offsetof(CPUAlphaState, ir[i]), p); > p += (i< 10) ? 4 : 5; > > sprintf(p, "fir%d", i); > cpu_fir[i] = tcg_global_mem_new_i64(TCG_AREG0, > - offsetof(CPUState, fir[i]), p); > + offsetof(CPUAlphaState, fir[i]), p); > p += (i< 10) ? 5 : 6; > } > > cpu_pc = tcg_global_mem_new_i64(TCG_AREG0, > - offsetof(CPUState, pc), "pc"); > + offsetof(CPUAlphaState, pc), "pc"); > > cpu_lock_addr = tcg_global_mem_new_i64(TCG_AREG0, > - offsetof(CPUState, lock_addr), > + offsetof(CPUAlphaState, lock_addr), > "lock_addr"); > cpu_lock_st_addr = tcg_global_mem_new_i64(TCG_AREG0, > - offsetof(CPUState, lock_st_addr), > + offsetof(CPUAlphaState, lock_st_addr), > "lock_st_addr"); > cpu_lock_value = tcg_global_mem_new_i64(TCG_AREG0, > - offsetof(CPUState, lock_value), > + offsetof(CPUAlphaState, lock_value), > "lock_value"); > > cpu_unique = tcg_global_mem_new_i64(TCG_AREG0, > - offsetof(CPUState, unique), "unique"); > + offsetof(CPUAlphaState, unique), "unique"); > #ifndef CONFIG_USER_ONLY > cpu_sysval = tcg_global_mem_new_i64(TCG_AREG0, > - offsetof(CPUState, sysval), "sysval"); > + offsetof(CPUAlphaState, sysval), "sysval"); > cpu_usp = tcg_global_mem_new_i64(TCG_AREG0, > - offsetof(CPUState, usp), "usp"); > + offsetof(CPUAlphaState, usp), "usp"); > #endif > > /* register helpers */ > @@ -611,7 +611,7 @@ static void gen_qual_roundmode(DisasContext *ctx, int fn11) > tcg_gen_movi_i32(tmp, float_round_down); > break; > case QUAL_RM_D: > - tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUState, fpcr_dyn_round)); > + tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUAlphaState, fpcr_dyn_round)); > break; > } > > @@ -620,7 +620,7 @@ static void gen_qual_roundmode(DisasContext *ctx, int fn11) > With CONFIG_SOFTFLOAT that expands to an out-of-line call that just > sets the one field. */ > tcg_gen_st8_i32(tmp, cpu_env, > - offsetof(CPUState, fp_status.float_rounding_mode)); > + offsetof(CPUAlphaState, fp_status.float_rounding_mode)); > #else > gen_helper_setroundmode(tmp); > #endif > @@ -641,7 +641,7 @@ static void gen_qual_flushzero(DisasContext *ctx, int fn11) > tmp = tcg_temp_new_i32(); > if (fn11) { > /* Underflow is enabled, use the FPCR setting. */ > - tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUState, fpcr_flush_to_zero)); > + tcg_gen_ld8u_i32(tmp, cpu_env, offsetof(CPUAlphaState, fpcr_flush_to_zero)); > } else { > /* Underflow is disabled, force flush-to-zero. */ > tcg_gen_movi_i32(tmp, 1); > @@ -649,7 +649,7 @@ static void gen_qual_flushzero(DisasContext *ctx, int fn11) > > #if defined(CONFIG_SOFTFLOAT_INLINE) > tcg_gen_st8_i32(tmp, cpu_env, > - offsetof(CPUState, fp_status.flush_to_zero)); > + offsetof(CPUAlphaState, fp_status.flush_to_zero)); > #else > gen_helper_setflushzero(tmp); > #endif > @@ -677,7 +677,7 @@ static void gen_fp_exc_clear(void) > #if defined(CONFIG_SOFTFLOAT_INLINE) > TCGv_i32 zero = tcg_const_i32(0); > tcg_gen_st8_i32(zero, cpu_env, > - offsetof(CPUState, fp_status.float_exception_flags)); > + offsetof(CPUAlphaState, fp_status.float_exception_flags)); > tcg_temp_free_i32(zero); > #else > gen_helper_fp_exc_clear(); > @@ -696,7 +696,7 @@ static void gen_fp_exc_raise_ignore(int rc, int fn11, int ignore) > > #if defined(CONFIG_SOFTFLOAT_INLINE) > tcg_gen_ld8u_i32(exc, cpu_env, > - offsetof(CPUState, fp_status.float_exception_flags)); > + offsetof(CPUAlphaState, fp_status.float_exception_flags)); > #else > gen_helper_fp_exc_get(exc); > #endif > @@ -1456,11 +1456,11 @@ static void gen_rx(int ra, int set) > TCGv_i32 tmp; > > if (ra != 31) { > - tcg_gen_ld8u_i64(cpu_ir[ra], cpu_env, offsetof(CPUState, intr_flag)); > + tcg_gen_ld8u_i64(cpu_ir[ra], cpu_env, offsetof(CPUAlphaState, intr_flag)); > } > > tmp = tcg_const_i32(set); > - tcg_gen_st8_i32(tmp, cpu_env, offsetof(CPUState, intr_flag)); > + tcg_gen_st8_i32(tmp, cpu_env, offsetof(CPUAlphaState, intr_flag)); > tcg_temp_free_i32(tmp); > } > > @@ -1504,7 +1504,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) > break; > case 0x2D: > /* WRVPTPTR */ > - tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env, offsetof(CPUState, vptptr)); > + tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env, offsetof(CPUAlphaState, vptptr)); > break; > case 0x31: > /* WRVAL */ > @@ -1521,19 +1521,19 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) > > /* Note that we already know we're in kernel mode, so we know > that PS only contains the 3 IPL bits. */ > - tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUState, ps)); > + tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUAlphaState, ps)); > > /* But make sure and store only the 3 IPL bits from the user. */ > tmp = tcg_temp_new(); > tcg_gen_andi_i64(tmp, cpu_ir[IR_A0], PS_INT_MASK); > - tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUState, ps)); > + tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUAlphaState, ps)); > tcg_temp_free(tmp); > break; > } > > case 0x36: > /* RDPS */ > - tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUState, ps)); > + tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUAlphaState, ps)); > break; > case 0x38: > /* WRUSP */ > @@ -1546,7 +1546,7 @@ static ExitStatus gen_call_pal(DisasContext *ctx, int palcode) > case 0x3C: > /* WHAMI */ > tcg_gen_ld32s_i64(cpu_ir[IR_V0], cpu_env, > - offsetof(CPUState, cpu_index)); > + offsetof(CPUAlphaState, cpu_index)); > break; > > default: > @@ -1654,7 +1654,7 @@ static ExitStatus gen_mtpr(DisasContext *ctx, int rb, int regno) > case 253: > /* WAIT */ > tmp = tcg_const_i64(1); > - tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUState, halted)); > + tcg_gen_st32_i64(tmp, cpu_env, offsetof(CPUAlphaState, halted)); > return gen_excp(ctx, EXCP_HLT, 0); > > case 252: > @@ -3107,7 +3107,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) > address from EXC_ADDR. This turns out to be useful for our > emulation PALcode, so continue to accept it. */ > TCGv tmp = tcg_temp_new(); > - tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUState, exc_addr)); > + tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUAlphaState, exc_addr)); > gen_helper_hw_ret(tmp); > tcg_temp_free(tmp); > } else { > @@ -3325,7 +3325,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn) > return ret; > } > > -static inline void gen_intermediate_code_internal(CPUState *env, > +static inline void gen_intermediate_code_internal(CPUAlphaState *env, > TranslationBlock *tb, > int search_pc) > { > @@ -3450,12 +3450,12 @@ static inline void gen_intermediate_code_internal(CPUState *env, > #endif > } > > -void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb) > +void gen_intermediate_code (CPUAlphaState *env, struct TranslationBlock *tb) > { > gen_intermediate_code_internal(env, tb, 0); > } > > -void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) > +void gen_intermediate_code_pc (CPUAlphaState *env, struct TranslationBlock *tb) > { > gen_intermediate_code_internal(env, tb, 1); > } > @@ -3522,7 +3522,7 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model) > return env; > } > > -void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos) > +void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb, int pc_pos) > { > env->pc = gen_opc_pc[pc_pos]; > }