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From: Alexander Graf <agraf@suse.de>
In-Reply-To: <20100911071203.GA25515@laped.lan>
Date: Sat, 11 Sep 2010 12:30:50 +0200
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Subject: [Qemu-devel] Re: [PATCH 0/2] PowerPC fixes
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To: "Edgar E.Iglesias" <edgar.iglesias@gmail.com>
Cc: Thomas Monjalon <thomas@monjalon.net>, QEMU Developers <qemu-devel@nongnu.org>


On 11.09.2010, at 09:12, Edgar E. Iglesias wrote:

> On Sat, Sep 11, 2010 at 03:08:32AM +0200, Alexander Graf wrote:
>> There goes another round of PowerPC fixes. Originally this should =
only have
>> been a fix for the MSR_POW issue (bug 608107), but I also stumbed =
over recent
>> Linux kernels not booting in qemu-system-ppc64. So a fix for that is =
also
>> included.
>>=20
>> With this new logic I didn't really took care of all HV corner cases, =
but HV
>> mode is not properly implemented anyways (read: we should probably =
rip it out
>> or do it properly, whichever is easier). I'm also fairly sure that =
the way
>> things are now BookE doesn't work at all, so things again haven't =
become worse.
>>=20
>> Alexander Graf (2):
>>  PPC: Enable hint bits for lwarx/ldarx
>>  PPC: Redesign interrupt trigger path
>=20
>=20
> FWIW the MSR parts look good to me.
> Also, none of this seems to break anything on my Virtex5 PPC-440 BookE
> board (Im working on cleaning that up so it eventually can be =
submitted).

You have a working 440 MMU implementation? FWIW on 440 (which is BookE) =
the whole interrupt stuff works differently, giving two different =
registers for status bits and saved MSR. Have you changed any bits =
there?


Alex