From: robherring2@gmail.com (Rob Herring)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/8] arm: mach-armada: add headers
Date: Tue, 15 May 2012 08:21:30 -0500 [thread overview]
Message-ID: <4FB2585A.2030302@gmail.com> (raw)
In-Reply-To: <1337072084-21967-2-git-send-email-thomas.petazzoni@free-electrons.com>
On 05/15/2012 03:54 AM, Thomas Petazzoni wrote:
> From: Gregory CLEMENT <gregory.clement@free-electrons.com>
>
> This patch adds basic header files for Armada SoCs.
The split of patch 1 and 2 doesn't really make sense.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Signed-off-by: Lior Amsalem <alior@marvell.com>
> ---
> arch/arm/mach-armada/include/mach/armada.h | 234 +++++++++++++++++++++++
> arch/arm/mach-armada/include/mach/bridge-regs.h | 28 +++
> arch/arm/mach-armada/include/mach/debug-macro.S | 23 +++
> arch/arm/mach-armada/include/mach/gpio.h | 13 ++
> arch/arm/mach-armada/include/mach/hardware.h | 18 ++
> arch/arm/mach-armada/include/mach/io.h | 24 +++
> arch/arm/mach-armada/include/mach/irqs.h | 96 ++++++++++
> arch/arm/mach-armada/include/mach/system.h | 21 ++
> arch/arm/mach-armada/include/mach/timex.h | 13 ++
> arch/arm/mach-armada/include/mach/uncompress.h | 41 ++++
> 10 files changed, 511 insertions(+)
> create mode 100644 arch/arm/mach-armada/include/mach/armada.h
> create mode 100644 arch/arm/mach-armada/include/mach/bridge-regs.h
> create mode 100644 arch/arm/mach-armada/include/mach/debug-macro.S
> create mode 100644 arch/arm/mach-armada/include/mach/gpio.h
> create mode 100644 arch/arm/mach-armada/include/mach/hardware.h
> create mode 100644 arch/arm/mach-armada/include/mach/io.h
> create mode 100644 arch/arm/mach-armada/include/mach/irqs.h
> create mode 100644 arch/arm/mach-armada/include/mach/system.h
> create mode 100644 arch/arm/mach-armada/include/mach/timex.h
> create mode 100644 arch/arm/mach-armada/include/mach/uncompress.h
>
> diff --git a/arch/arm/mach-armada/include/mach/armada.h b/arch/arm/mach-armada/include/mach/armada.h
> new file mode 100644
> index 0000000..be12667
> --- /dev/null
> +++ b/arch/arm/mach-armada/include/mach/armada.h
> @@ -0,0 +1,234 @@
> +/*
> + * Generic definitions for Marvell Armada SoCs
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#ifndef __MACH_ARMADA_H
> +#define __MACH_ARMADA_H
> +
> +/*
> + * Marvell ARMADA address maps.
> + *
> + * phys virt size
> + * d0000000 feb00000 1M internal registers
> + * d0100000 @runtime 1M uart
> + * d0200000 fec00000 1M PCIe-0 I/O (port 0.0)
> + * d0300000 fed00000 1M PCIe-1 I/O (port 1.0)
> + * d0400000 fee00000 1M PCIe-2 I/O (port 2.0)
> + * d0500000 fef00000 1M PCIe-3 I/O (port 3.0)
> + * d0600000 @runtime 1M cryptographic sram-0
> + * d0700000 @runtime 1M cryptographic sram-1
> + * d0800000 reserved 8M reserved for future
> + * d1000000 @runtime 16M device bus cs-0
> + * d2000000 @runtime 16M device bus cs-0
> + * d3000000 @runtime 16M device bus cs-0
> + * d4000000 @runtime 16M device bus cs-0
> + * d5000000 @runtime 16M device bus boot cs
> + * d6000000 @runtime 16M spi-0 flash
> + * d7000000 @runtime 16M spi-1 flash
> + * d8000000 @runtime 64M PCIe-0 Memory (port 0.0)
> + * dc000000 @runtime 64M PCIe-1 Memory (port 1.0)
> + * e0000000 @runtime 64M PCIe-2 Memory (port 2.0)
> + * e4000000 @runtime 64M PCIe-3 Memory (port 3.0)
> + * fff00000 @runtime 1M internal bootrom
> + */
> +
> +#define ARMADA_REGS_PHYS_BASE 0xd0000000
> +#define ARMADA_REGS_VIRT_BASE 0xfeb00000
> +#define ARMADA_REGS_SIZE SZ_1M
> +
> +#define ARMADA_UART_REGS_BASE 0xd0100000
> +#define ARMADA_UART_SIZE _1M
> +
> +#define ARMADA_PCIE0_IO_PHYS_BASE 0xd0200000
> +#define ARMADA_PCIE0_IO_VIRT_BASE 0xfec00000
> +#define ARMADA_PCIE0_IO_BUS_BASE 0x00100000
> +#define ARMADA_PCIE0_IO_SIZE SZ_1M
> +
> +#define ARMADA_PCIE1_IO_PHYS_BASE 0xd0300000
> +#define ARMADA_PCIE1_IO_VIRT_BASE 0xfed00000
> +#define ARMADA_PCIE1_IO_BUS_BASE 0x00200000
> +#define ARMADA_PCIE1_IO_SIZE SZ_1M
> +
> +#define ARMADA_PCIE2_IO_PHYS_BASE 0xd0400000
> +#define ARMADA_PCIE2_IO_VIRT_BASE 0xfee00000
> +#define ARMADA_PCIE2_IO_BUS_BASE 0x00300000
> +#define ARMADA_PCIE2_IO_SIZE SZ_1M
> +
> +#define ARMADA_PCIE3_IO_PHYS_BASE 0xd0500000
> +#define ARMADA_PCIE3_IO_VIRT_BASE 0xfef00000
> +#define ARMADA_PCIE3_IO_BUS_BASE 0x00400000
> +#define ARMADA_PCIE3_IO_SIZE SZ_1M
> +
> +#define ARMADA_CESA0_PHYS_BASE 0xd0600000
> +#define ARMADA_CESA0_SIZE SZ_1M
> +
> +#define ARMADA_CESA1_PHYS_BASE 0xd0700000
> +#define ARMADA_CESA1_SIZE SZ_1M
> +
> +#define ARMADA_DEVICE_CS0_PHYS_BASE 0xd1000000
> +#define ARMADA_DEVICE_CS0_SIZE SZ_16M
> +
> +#define ARMADA_DEVICE_CS1_PHYS_BASE 0xd2000000
> +#define ARMADA_DEVICE_CS1_SIZE SZ_16M
> +
> +#define ARMADA_DEVICE_CS2_PHYS_BASE 0xd3000000
> +#define ARMADA_DEVICE_CS2_SIZE SZ_16M
> +
> +#define ARMADA_DEVICE_CS3_PHYS_BASE 0xd4000000
> +#define ARMADA_DEVICE_CS3_SIZE SZ_16M
> +
> +#define ARMADA_DEVICE_BOOT_CS_PHYS_BASE 0xd5000000
> +#define ARMADA_DEVICE_BOOT_CS_SIZE SZ_16M
> +
> +#define ARMADA_SPI0_CS0_PHYS_BASE 0xd6000000
> +#define ARMADA_SPI0_CS0_SIZE SZ_16M
> +
> +#define ARMADA_SPI1_CS0_PHYS_BASE 0xd7000000
> +#define ARMADA_SPI1_CS0_SIZE SZ_16M
> +
> +#define ARMADA_PCIE0_MEM_PHYS_BASE 0xd8000000
> +#define ARMADA_PCIE0_MEM_SIZE SZ_64M
> +
> +#define ARMADA_PCIE1_MEM_PHYS_BASE 0xdc000000
> +#define ARMADA_PCIE1_MEM_SIZE SZ_64M
> +
> +#define ARMADA_PCIE2_MEM_PHYS_BASE 0xe0000000
> +#define ARMADA_PCIE2_MEM_SIZE SZ_64M
> +
> +#define ARMADA_PCIE3_MEM_PHYS_BASE 0xe4000000
> +#define ARMADA_PCIE3_MEM_SIZE SZ_64M
> +
> +#define ARMADA_BOOTROM_PHYS_BASE 0xFFF00000
> +#define ARMADA_BOOTROM_SIZE SZ_1M
> +
> +/*
> + * Core Registers Map
> + */
> +
> +/* DRAM */
> +#define ARMADA_DRAM_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x0)
> +#define ARMADA_DRAM_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x0)
> +
> +/* L2 Cache */
> +#define ARMADA_L2_CACHE_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x8000)
> +#define ARMADA_L2_CACHE_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x8000)
> +
> +/* RTC */
> +#define ARMADA_RTC_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x10300)
> +#define ARMADA_RTC_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x10300)
> +
> +/* SPI */
> +#define ARMADA_SPI0_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x10600)
> +#define ARMADA_SPI0_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x10600)
> +#define ARMADA_SPI1_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x10680)
> +#define ARMADA_SPI1_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x10680)
> +
> +/* I2C */
> +#define ARMADA_I2C0_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x11000)
> +#define ARMADA_I2C0_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x11000)
> +#define ARMADA_I2C1_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x11100)
> +#define ARMADA_I2C1_VIRT_BASE (ARMADA_REGS_PHYS_BASE | 0x11100)
> +
> +/* UART */
> +#define ARMADA_UART0_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x12000)
> +#define ARMADA_UART0_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x12000)
> +#define ARMADA_UART1_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x12100)
> +#define ARMADA_UART1_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x12100)
> +
> +/* MPP (pin muxing) */
> +#define ARMADA_MPP_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x18000)
> +#define ARMADA_MPP_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x18000)
> +
> +/* GPIO */
> +#define ARMADA_GPIO_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x18100)
> +#define ARMADA_GPIO_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x18100)
> +
> +/* Misc registers */
> +#define ARMADA_SYSTEM_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x18200)
> +#define ARMADA_SYSTEM_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x18200)
> +
> +/* CPU */
> +#define ARMADA_CPU_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x20000)
> +#define ARMADA_CPU_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x20000)
> +
> +/* Audio */
> +#define ARMADA_AUDIO_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x30000)
> +#define ARMADA_AUDIO_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x30000)
> +
> +/* PCIe */
> +#define ARMADA_PCIE0_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x40000)
> +#define ARMADA_PCIE0_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x40000)
> +#define ARMADA_PCIE1_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x80000)
> +#define ARMADA_PCIE1_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x80000)
> +#define ARMADA_PCIE2_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x42000)
> +#define ARMADA_PCIE2_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x42000)
> +#define ARMADA_PCIE3_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x82000)
> +#define ARMADA_PCIE3_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x82000)
> +
> +/* USB */
> +#define ARMADA_USB0_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x50000)
> +#define ARMADA_USB0_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x50000)
> +#define ARMADA_USB1_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x51000)
> +#define ARMADA_USB1_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x51000)
> +
> +/* XOR Engines */
> +#define ARMADA_XOR0_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x60900)
> +#define ARMADA_XOR0_HIGH_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x60B00)
> +#define ARMADA_XOR1_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0xF0900)
> +#define ARMADA_XOR1_HIGH_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0xF0B00)
> +
> +/* Cryptographic Engine */
> +#define ARMADA_CRYPT_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x30000)
> +
> +/* Gigabit Ethernet */
> +#define ARMADA_GE00_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x70000)
> +#define ARMADA_GE01_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x74000)
> +#define ARMADA_GE10_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x30000)
> +#define ARMADA_GE11_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x34000)
> +
> +/* SDIO */
> +#define ARMADA_SDIO0_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x92000)
> +
> +/* SATA */
> +#define ARMADA_SATA_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0xa0000)
> +
> +/* NAND Flash Controller */
> +#define ARMADA_NFC_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0xd0000)
> +
> +/* MPP, GPIO, Reset Sampling */
> +#define ARMADA_MPP_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x18000)
> +#define ARMADA_GPIO0_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x18100)
> +#define ARMADA_GPIO1_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x18140)
> +#define ARMADA_GPIO2_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x18180)
> +
> +/* Power Management */
> +#define ARMADA_PMU_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x1c000)
> +
> +/* Real Time Clock */
> +#define ARMADA_RTC_PHYS_BASE (ARMADA_REGS_PHYS_BASE | 0x10300)
> +
> +/* Memory Controller */
> +#define ARMADA_MC_VIRT_BASE (ARMADA_REGS_VIRT_BASE | 0x20180)
> +
> +/* Timers */
> +#define ARMADA_TIMER_VIRT_BASE (ARMADA_CPU_VIRT_BASE | 0x0300)
> +#define ARMADA_TIMERS_INT_TIMER1_CLR (~0x0100)
> +#define TIMER_VIRT_BASE ARMADA_TIMER_VIRT_BASE
> +
> +/* Main Interrupt Controller Control and Configuration */
> +#define ARMADA_MAIN_INT_CNTL_BASE (ARMADA_CPU_VIRT_BASE | 0x0)
> +
> +/* Per CPU Interrupt Controller Control and Configuration */
> +#define ARMADA_PER_CPU_INT_CNTL_BASE (ARMADA_CPU_VIRT_BASE | 0x1000)
> +
As Ben pointed out, all this should come from DT.
> +#endif /* __MACH_ARMADA_H */
> diff --git a/arch/arm/mach-armada/include/mach/bridge-regs.h b/arch/arm/mach-armada/include/mach/bridge-regs.h
> new file mode 100644
> index 0000000..0eaefbd
> --- /dev/null
> +++ b/arch/arm/mach-armada/include/mach/bridge-regs.h
> @@ -0,0 +1,28 @@
> +/*
> + * Mbus-L to Mbus Bridge Registers
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + * Gregory CLEMENT <gregory.clement@free-electrons.com>
> + * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#ifndef __ASM_ARCH_BRIDGE_REGS_H
> +#define __ASM_ARCH_BRIDGE_REGS_H
> +
> +#include <mach/armada.h>
> +
> +#define RSTOUTn_MASK (ARMADA_SYSTEM_VIRT_BASE | 0x60)
> +#define SOFT_RESET_OUT_EN 0x00000001
> +
> +#define SYSTEM_SOFT_RESET (ARMADA_SYSTEM_VIRT_BASE | 0x64)
> +#define SOFT_RESET 0x00000001
> +
> +#define SOC_ID (ARMADA_MISC_VIRT_BASE | 0x3C)
> +
> +#endif
> diff --git a/arch/arm/mach-armada/include/mach/debug-macro.S b/arch/arm/mach-armada/include/mach/debug-macro.S
> new file mode 100644
> index 0000000..1c7c52f
> --- /dev/null
> +++ b/arch/arm/mach-armada/include/mach/debug-macro.S
> @@ -0,0 +1,23 @@
> +/*
> + * Early serial output macro for Marvell Armada SoC
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> +*/
> +
> +#include <mach/armada.h>
> +
> + .macro addruart, rp, rv, tmp
> + ldr \rp, =ARMADA_REGS_PHYS_BASE
> + ldr \rv, =ARMADA_REGS_VIRT_BASE
> + orr \rp, \rp, #0x00012000
> + orr \rv, \rv, #0x00012000
> + .endm
> +
> +#define UART_SHIFT 2
> +#include <asm/hardware/debug-8250.S>
> diff --git a/arch/arm/mach-armada/include/mach/gpio.h b/arch/arm/mach-armada/include/mach/gpio.h
> new file mode 100644
> index 0000000..e62f38a
> --- /dev/null
> +++ b/arch/arm/mach-armada/include/mach/gpio.h
> @@ -0,0 +1,13 @@
> +/*
> + * Marvell Armada SoC GPIO definitions
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <plat/gpio.h>
New platforms should probably have empty gpio.h.
> diff --git a/arch/arm/mach-armada/include/mach/hardware.h b/arch/arm/mach-armada/include/mach/hardware.h
> new file mode 100644
> index 0000000..829111b
> --- /dev/null
> +++ b/arch/arm/mach-armada/include/mach/hardware.h
You should not have a hardware.h. Include armada.h directly or ideally
remove the need for it.
> @@ -0,0 +1,18 @@
> +/*
> + * Marvell Armada SoC hardware definitions
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#ifndef __ASM_ARCH_HARDWARE_H
> +#define __ASM_ARCH_HARDWARE_H
> +
> +#include <mach/armada.h>
> +
> +#endif
> diff --git a/arch/arm/mach-armada/include/mach/io.h b/arch/arm/mach-armada/include/mach/io.h
> new file mode 100644
> index 0000000..48716c1
> --- /dev/null
> +++ b/arch/arm/mach-armada/include/mach/io.h
> @@ -0,0 +1,24 @@
> +/*
> + * Basic I/O macros
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#ifndef __ASM_ARCH_IO_H
> +#define __ASM_ARCH_IO_H
> +
> +#include <mach/armada.h>
> +
> +#define IO_SPACE_LIMIT 0xffffffff
Your i/o window should really not be full 32-bit address space.
> +
> +#define __io(a) ((void __iomem *)(((a) - ARMADA_PCIE0_IO_BUS_BASE) + \
> + ARMADA_PCIE0_IO_VIRT_BASE))
Are you including PCI in initial patches? This is not needed.
> +#define __mem_pci(a) (a)
Not needed.
In other words, remove io.h. It's no longer needed except for a few
cases like PCI and that will be fixed soon (hopefully).
> +
> +#endif
> diff --git a/arch/arm/mach-armada/include/mach/irqs.h b/arch/arm/mach-armada/include/mach/irqs.h
> new file mode 100644
> index 0000000..48844a4
> --- /dev/null
> +++ b/arch/arm/mach-armada/include/mach/irqs.h
> @@ -0,0 +1,96 @@
> +/*
> + * IRQ definitions for Marvell Armada SoC
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#ifndef __ASM_ARCH_IRQS_H
> +#define __ASM_ARCH_IRQS_H
> +
> +/*
> + * Per-cpu Interrupts
> + */
> +#define IRQ_ARMADA_DRBL_LOW 0
> +#define IRQ_ARMADA_DRBL_HI 1
> +#define IRQ_ARMADA_DRBL_SUM 2
> +#define IRQ_ARMADA_FABRIC 3
> +#define IRQ_ARMADA_SOC_ERR 4
> +#define IRQ_ARMADA_LCL_TIMER0 5
> +#define IRQ_ARMADA_LCL_TIMER1 6
> +#define IRQ_ARMADA_LCL_WD 7
> +#define IRQ_ARMADA_GE0_TH_RXTX 8
> +#define IRQ_ARMADA_GE0_RXTX 9
> +#define IRQ_ARMADA_GE1_TH_RXTX 10
> +#define IRQ_ARMADA_GE1_RXTX 11
> +#define IRQ_ARMADA_GE2_TH_RXTX 12
> +#define IRQ_ARMADA_GE2_RXTX 13
> +#define IRQ_ARMADA_GE3_TH_RXTX 14
> +#define IRQ_ARMADA_GE3_RXTX 15
> +
> +/*
> + * Global interrupts
> + */
> +#define IRQ_ARMADA_LCD 29
> +#define IRQ_ARMADA_SPI0 30
> +#define IRQ_ARMADA_I2C0 31
> +#define IRQ_ARMADA_I2C1 32
> +#define IRQ_ARMADA_GLBL_TIMER0 37
> +#define IRQ_ARMADA_GLBL_TIMER1 38
> +#define IRQ_ARMADA_GLBL_TIMER2 39
> +#define IRQ_ARMADA_GLBL_TIMER3 40
> +#define IRQ_ARMADA_UART0 41
> +#define IRQ_ARMADA_UART1 42
> +#define IRQ_ARMADA_UART2 43
> +#define IRQ_ARMADA_UART3 44
> +#define IRQ_ARMADA_USB0 45
> +#define IRQ_ARMADA_USB1 46
> +#define IRQ_ARMADA_USB2 47
> +#define IRQ_ARMADA_CESA0 48
> +#define IRQ_ARMADA_CESA1 49
> +#define IRQ_ARMADA_RTC 50
> +#define IRQ_ARMADA_XOR0_CH0 51
> +#define IRQ_ARMADA_XOR0_CH1 52
> +#define IRQ_ARMADA_SDIO 54
> +#define IRQ_ARMADA_SATA0 55
> +#define IRQ_ARMADA_TDM 56
> +#define IRQ_ARMADA_SATA1 57
> +#define IRQ_ARMADA_PCIE0 61
> +#define IRQ_ARMADA_PCIE1 62
> +#define IRQ_ARMADA_GPIO_0_7 82
> +#define IRQ_ARMADA_GPIO_8_15 83
> +#define IRQ_ARMADA_GPIO_16_23 84
> +#define IRQ_ARMADA_GPIO_24_31 85
> +#define IRQ_ARMADA_GPIO_32_39 87
> +#define IRQ_ARMADA_GPIO_40_47 88
> +#define IRQ_ARMADA_GPIO_48_55 89
> +#define IRQ_ARMADA_GPIO_56_63 90
> +#define IRQ_ARMADA_GPIO_64_66 91
> +#define IRQ_ARMADA_SPI1 92
> +#define IRQ_ARMADA_WD 93
> +#define IRQ_ARMADA_XOR1_CH0 94
> +#define IRQ_ARMADA_XOR1_CH1 95
> +#define IRQ_ARMADA_PCIE2 99
> +#define IRQ_ARMADA_PCIE3 103
> +#define IRQ_ARMADA_DRAM 108
> +#define IRQ_ARMADA_GE0_WKUP 109
> +#define IRQ_ARMADA_GE1_WKUP 110
> +#define IRQ_ARMADA_GE2_WKUP 111
> +#define IRQ_ARMADA_GE3_WKUP 112
> +#define IRQ_ARMADA_NFC 113
> +
> +/*
> + * ARMADA General Purpose Pins
> + */
> +#define IRQ_ARMADA_GPIO_START 82
> +#define NR_GPIO_IRQS 64
> +
> +#define NR_IRQS (115)
> +
All this should come from DT. Enable SPARSE_IRQ.
> +
> +#endif
> diff --git a/arch/arm/mach-armada/include/mach/system.h b/arch/arm/mach-armada/include/mach/system.h
> new file mode 100644
> index 0000000..f920ef0
> --- /dev/null
> +++ b/arch/arm/mach-armada/include/mach/system.h
This header is gone now. You don't need anything if you just use the
default cpu_do_idle.
> @@ -0,0 +1,21 @@
> +/*
> + * Marvell Armada SoC system defines
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#ifndef __ASM_ARCH_SYSTEM_H
> +#define __ASM_ARCH_SYSTEM_H
> +
> +static inline void arch_idle(void)
> +{
> + cpu_do_idle();
> +}
> +
> +#endif
> diff --git a/arch/arm/mach-armada/include/mach/timex.h b/arch/arm/mach-armada/include/mach/timex.h
> new file mode 100644
> index 0000000..ab324a3
> --- /dev/null
> +++ b/arch/arm/mach-armada/include/mach/timex.h
> @@ -0,0 +1,13 @@
> +/*
> + * Marvell Armada SoC time definitions
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#define CLOCK_TICK_RATE (100 * HZ)
> diff --git a/arch/arm/mach-armada/include/mach/uncompress.h b/arch/arm/mach-armada/include/mach/uncompress.h
> new file mode 100644
> index 0000000..611ebf3
> --- /dev/null
> +++ b/arch/arm/mach-armada/include/mach/uncompress.h
> @@ -0,0 +1,41 @@
> +/*
> + * Marvell Armada SoC kernel uncompression UART routines
> + *
> + * Copyright (C) 2012 Marvell
> + *
> + * Lior Amsalem <alior@marvell.com>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <mach/armada.h>
> +
> +#define UART_THR ((volatile unsigned char *)(ARMADA_UART0_PHYS_BASE + 0x0))
> +#define UART_LSR ((volatile unsigned char *)(ARMADA_UART0_PHYS_BASE + 0x14))
> +
> +#define LSR_THRE 0x20
> +
> +static void putc(const char c)
> +{
> + int i;
> +
> + for (i = 0; i < 0x1000; i++) {
> + /* Transmit fifo not full? */
> + if (*UART_LSR & LSR_THRE)
> + break;
> + }
> +
> + *UART_THR = c;
> +}
> +
> +static void flush(void)
> +{
> +}
> +
> +/*
> + * nothing to do
> + */
> +#define arch_decomp_setup()
> +#define arch_decomp_wdog()
next prev parent reply other threads:[~2012-05-15 13:21 UTC|newest]
Thread overview: 140+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-05-15 8:54 [PATCH] arm: Add basic support for new Marvell Armada SoC family Thomas Petazzoni
2012-05-15 8:54 ` [PATCH 1/8] arm: mach-armada: add headers Thomas Petazzoni
2012-05-15 9:16 ` Ben Dooks
2012-05-15 10:57 ` Ben Dooks
2012-05-15 13:21 ` Rob Herring [this message]
2012-05-15 18:42 ` Nicolas Pitre
2012-05-15 8:54 ` [PATCH 2/8] arm: mach-armada: add source files Thomas Petazzoni
2012-05-15 9:12 ` Andrew Lunn
2012-05-15 9:17 ` Thomas Petazzoni
2012-05-15 9:54 ` Ben Dooks
2012-05-15 10:00 ` Arnaud Patard (Rtp)
2012-05-15 10:37 ` Ben Dooks
2012-05-15 9:27 ` Andrew Lunn
2012-05-15 9:54 ` Ben Dooks
2012-05-15 12:46 ` Lior Amsalem
2012-05-15 9:46 ` Ben Dooks
2012-05-15 9:59 ` Gregory CLEMENT
2012-05-15 10:03 ` Andrew Lunn
2012-05-19 6:21 ` Grant Likely
2012-05-16 14:27 ` Ben Dooks
2012-05-16 15:06 ` Ben Dooks
2012-05-15 8:54 ` [PATCH 3/8] arm: mach-armada: add documentation for new device tree bindings Thomas Petazzoni
2012-05-15 11:31 ` Ben Dooks
2012-05-15 8:54 ` [PATCH 4/8] arm: mach-armada: add compilation/configuration changes Thomas Petazzoni
2012-05-15 8:54 ` [PATCH 5/8] arm: mach-armada: add support for Armada 370 board with device tree Thomas Petazzoni
2012-05-15 8:54 ` [PATCH 6/8] arm: mach-armada: add support for Armada XP " Thomas Petazzoni
2012-05-15 9:58 ` Ben Dooks
2012-05-15 13:10 ` Lior Amsalem
2012-05-15 13:19 ` Andrew Lunn
2012-05-15 14:23 ` Arnd Bergmann
2012-05-15 18:37 ` Nicolas Pitre
2012-05-17 23:31 ` Jason Cooper
2012-05-15 13:33 ` Ben Dooks
2012-05-15 13:31 ` Rob Herring
2012-05-15 13:53 ` Ben Dooks
2012-05-15 14:16 ` Thomas Petazzoni
2012-05-15 14:25 ` Arnd Bergmann
2012-05-15 14:29 ` Thomas Petazzoni
2012-05-15 14:35 ` Ben Dooks
2012-05-15 14:53 ` Rob Herring
2012-05-15 15:01 ` Ben Dooks
2012-05-15 15:30 ` Russell King - ARM Linux
2012-05-15 14:32 ` Ben Dooks
2012-05-15 14:37 ` Arnd Bergmann
2012-05-15 16:31 ` Stephen Warren
2012-05-15 19:41 ` Arnd Bergmann
2012-05-15 14:58 ` Thomas Petazzoni
2012-05-15 15:07 ` Ben Dooks
2012-05-15 15:32 ` Arnd Bergmann
2012-05-15 15:46 ` Thomas Petazzoni
2012-05-15 21:22 ` Rob Herring
2012-05-15 15:49 ` Ben Dooks
2012-05-15 19:06 ` Arnd Bergmann
2012-05-15 15:41 ` Russell King - ARM Linux
2012-05-15 15:59 ` Ben Dooks
2012-05-15 16:03 ` Russell King - ARM Linux
2012-05-17 23:35 ` Jason Cooper
2012-05-18 2:12 ` Rob Herring
2012-05-22 12:00 ` Ben Dooks
2012-05-22 13:34 ` Jason Cooper
2012-05-22 17:06 ` Arnd Bergmann
2012-05-23 2:02 ` Haojian Zhuang
2012-05-15 8:54 ` [PATCH 7/8] arm: mach-armada: add defconfig Thomas Petazzoni
2012-05-15 9:58 ` Ben Dooks
2012-05-15 12:54 ` Thomas Petazzoni
2012-05-15 8:54 ` [PATCH 8/8] arm: mach-armada: add entry to MAINTAINERS Thomas Petazzoni
2012-05-15 9:18 ` [PATCH] arm: Add basic support for new Marvell Armada SoC family Andrew Lunn
2012-05-15 9:44 ` Thomas Petazzoni
2012-05-15 9:51 ` Ben Dooks
2012-05-15 9:55 ` Thomas Petazzoni
2012-05-15 13:15 ` Andrew Lunn
2012-05-15 14:35 ` Rob Herring
2012-05-15 14:44 ` Thomas Petazzoni
2012-05-15 15:27 ` Arnd Bergmann
2012-05-15 15:39 ` Thomas Petazzoni
2012-05-15 16:26 ` Arnd Bergmann
2012-05-15 21:35 ` Arnd Bergmann
2012-05-16 0:25 ` Nicolas Pitre
2012-05-16 5:07 ` Andrew Lunn
2012-05-16 6:57 ` Arnd Bergmann
2012-05-16 6:57 ` Haojian Zhuang
2012-05-16 17:30 ` Andrew Lunn
2012-05-15 18:20 ` Nicolas Pitre
2012-05-15 16:22 ` Andrew Lunn
2012-05-15 16:25 ` Ben Dooks
2012-05-15 16:30 ` Andrew Lunn
2012-05-15 16:37 ` Ben Dooks
2012-05-16 11:12 ` Lior Amsalem
2012-05-16 11:36 ` Andrew Lunn
2012-05-16 12:00 ` Arnd Bergmann
2012-05-16 14:55 ` Lior Amsalem
2012-05-16 15:20 ` Nicolas Pitre
2012-05-16 15:28 ` Arnd Bergmann
2012-05-16 16:49 ` Nicolas Pitre
2012-05-16 19:46 ` Arnd Bergmann
2012-05-16 20:20 ` Nicolas Pitre
2012-05-16 20:34 ` Arnd Bergmann
2012-05-18 19:20 ` Jason Cooper
2012-05-22 12:03 ` Ben Dooks
2012-05-18 19:18 ` Jason Cooper
2012-05-18 20:44 ` Arnd Bergmann
2012-05-18 22:51 ` Nicolas Pitre
2012-05-19 11:24 ` Jason Cooper
2012-05-19 17:32 ` Arnd Bergmann
2012-05-20 0:45 ` Nicolas Pitre
2012-05-20 9:55 ` Russell King - ARM Linux
2012-05-20 10:58 ` Arnd Bergmann
2012-05-20 11:10 ` Russell King - ARM Linux
2012-05-21 1:30 ` Jason Cooper
2012-05-21 7:58 ` Arnd Bergmann
2012-05-21 9:30 ` Russell King - ARM Linux
2012-05-21 15:35 ` Jason Cooper
2012-05-21 16:11 ` Russell King - ARM Linux
2012-05-21 16:58 ` Jason Cooper
2012-05-21 19:40 ` Arnd Bergmann
2012-05-22 14:25 ` Nicolas Pitre
2012-05-22 16:03 ` Jason Cooper
2012-05-22 16:06 ` Ben Dooks
2012-05-22 16:16 ` Jason Cooper
2012-05-24 11:18 ` Ben Dooks
2012-05-22 17:09 ` Arnd Bergmann
2012-05-21 8:55 ` Ben Dooks
2012-05-21 9:16 ` Andrew Lunn
2012-05-21 9:27 ` Ben Dooks
2012-05-21 9:40 ` Andrew Lunn
2012-05-21 15:39 ` Jason Cooper
2012-05-21 17:27 ` Andrew Lunn
2012-05-15 11:06 ` Arnd Bergmann
2012-05-15 12:50 ` Thomas Petazzoni
2012-05-15 16:03 ` Ben Dooks
2012-05-15 11:18 ` Ben Dooks
2012-05-15 12:26 ` Lior Amsalem
2012-05-15 12:51 ` Thomas Petazzoni
2012-05-15 11:20 ` Ben Dooks
2012-05-15 12:29 ` Lior Amsalem
2012-05-15 14:55 ` Ben Dooks
2012-05-15 15:00 ` Thomas Petazzoni
2012-05-15 15:07 ` Ben Dooks
2012-05-15 15:36 ` Ben Dooks
2012-05-15 15:39 ` Thomas Petazzoni
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